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1. 发明授权

US10052591B2 System and method for filtration 有权
公开(公告)号：US10052591B2
公开(公告)日：2018-08-21
申请号：US13876334
申请日：2011-09-27
申请人： Kwang-Jin Lee , Ah Reum Lee , Yong-Cheol Shin , Joon Yul Yang
发明人： Kwang-Jin Lee , Ah Reum Lee , Yong-Cheol Shin , Joon Yul Yang
IPC分类号： B01D65/08 , B01D65/02
CPC分类号： B01D65/02 , B01D65/08 , B01D2313/26 , B01D2315/06 , B01D2321/185
摘要： Disclosed are system and method for filtration which can minimize the contamination of the filtering membrane through a pretreatment and perform the pretreatment and the filtration with a filtering membrane in a single filtering unit so that any need for separate and additional space and facility for the pretreatment can be obviated. The system for filtration of the present invention comprises a fine bubble supplier for providing fine bubbles into the feed water. The pretreatment is performed by supplying the feed water to be treated into the filtering unit through a dynamic filtration layer which is formed in the filtering unit as the fine bubbles rise.

2. 发明授权

US08248860B2 Memory device using a variable resistive element 有权
标题翻译：使用可变电阻元件的存储器件
公开(公告)号：US08248860B2
公开(公告)日：2012-08-21
申请号：US12659840
申请日：2010-03-23
申请人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
发明人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
IPC分类号： G11C16/04
CPC分类号： G11C13/0097 , G11C13/0004 , G11C13/0069 , G11C2013/0088 , G11C2211/5646
摘要： A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.
摘要翻译：存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。第一擦除模式可以包括第一擦除单元和第一擦除数据模式。第二擦除模式可以包括第二擦除单元和第二擦除模式。第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

3. 发明授权

US08194447B2 Non-volatile memory device using variable resistance element with an improved write performance 有权
标题翻译：使用可变电阻元件的非易失性存储器件具有改进的写入性能
公开(公告)号：US08194447B2
公开(公告)日：2012-06-05
申请号：US12314513
申请日：2008-12-11
申请人： Hye-Jin Kim , Kwang-Jin Lee , Du-Eung Kim , Hung-Jun An
发明人： Hye-Jin Kim , Kwang-Jin Lee , Du-Eung Kim , Hung-Jun An
IPC分类号： G11C16/04
CPC分类号： G11C7/1078 , G11C5/14 , G11C7/1096 , G11C13/00 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A non-volatile memory device using a variable resistive element includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator generating a first voltage, a voltage pad receiving an external voltage that has a level higher than the first voltage, a sense amplifier supplied with the first voltage and reading data from the non-volatile memory cells selected from the memory cell array, and a write driver supplied with the external voltage and writing data to the non-volatile memory cells selected from the memory cell array.
摘要翻译：使用可变电阻元件的非易失性存储器件包括具有多个非易失性存储器单元的存储单元阵列，产生第一电压的第一电压发生器，接收高于第一电压的电平的外部电压的电压焊盘电压，提供有第一电压的读出放大器和从存储单元阵列中选择的非易失性存储器单元读取数据，以及提供有外部电压的写入驱动器，并将数据写入从存储器中选择的非易失性存储器单元单元格阵列。

4. 发明授权

US08139432B2 Variable resistance memory device and system thereof 有权
标题翻译：可变电阻存储器件及其系统
公开(公告)号：US08139432B2
公开(公告)日：2012-03-20
申请号：US12901168
申请日：2010-10-08
申请人： Byung-gil Choi , Beak-hyung Cho , Jun-Soo Bae , Kwang-Jin Lee
发明人： Byung-gil Choi , Beak-hyung Cho , Jun-Soo Bae , Kwang-Jin Lee
IPC分类号： G11C7/04
CPC分类号： G11C7/18 , G11C7/04 , G11C8/12 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C2013/0054 , G11C2029/2602 , H01L27/24
摘要： A nonvolatile memory device comprising: a plurality of memory banks, each of which operates independently and includes a plurality of resistance memory cells, each cell including a variable resistive element having a resistance varying depending on stored data; a plurality of global bit lines, each global bit line being shared by the plurality of memory banks; a temperature compensation circuit including one or more reference cells; and a data read circuit which is electrically connected to the plurality of global bit lines and performs a read operation by supplying at least one of the resistance memory cells with a current varying according to resistances of the reference cells.
摘要翻译：一种非易失性存储器件，包括：多个存储体，每个存储体各自独立地操作并且包括多个电阻存储器单元，每个单元包括具有根据存储的数据而变化的电阻的可变电阻元件; 多个全局位线，每个全局位线由多个存储体共享; 包括一个或多个参考单元的温度补偿电路; 以及数据读取电路，其电连接到所述多个全局位线，并且通过向所述电阻存储单元中的至少一个提供根据所述参考单元的电阻而变化的电流来执行读取操作。

5. 发明授权

US08050084B2 Nonvolatile memory device, storage system having the same, and method of driving the nonvolatile memory device 有权
标题翻译：非易失性存储器件，具有相同的存储系统以及驱动非易失性存储器件的方法
公开(公告)号：US08050084B2
公开(公告)日：2011-11-01
申请号：US12893413
申请日：2010-09-29
申请人： Jun-Soo Bae , Kwang-Jin Lee , Beak-Hyung Cho
发明人： Jun-Soo Bae , Kwang-Jin Lee , Beak-Hyung Cho
IPC分类号： G11C11/00
CPC分类号： G11C8/12 , G11C7/04 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2211/5634
摘要： A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells each having a resistance corresponding to one of a plurality of first resistance distributions, a temperature compensation circuit including one or more reference cells each having a resistance corresponding to one among one or more second resistance distributions, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit being adapted to supply compensation current to a sensing node, an amount of the compensation current varying based on the resistance of each reference cell, and the sense amplifier being adapted to compare the level of the sensing node with a reference level and to output a comparison result.
摘要翻译：非易失性存储器件包括存储单元阵列，其包括多个非易失性存储单元，每个非易失性存储单元具有对应于多个第一电阻分布之一的电阻，温度补偿电路包括一个或多个参考单元，每个参考单元具有对应于一个或更多的第二电阻分布，以及包括补偿单元和读出放大器的数据读取电路，所述补偿单元适于向感测节点提供补偿电流，所述补偿电流的量基于每个参考单元的电阻而变化，并且所述读出放大器适于将感测节点的电平与参考电平进行比较并输出比较结果。

6. 发明申请

US20100192976A1 APPARATUS FOR CLEANING A MEMBRANE MODULE AND A METHOD THEREFOR 审中-公开
标题翻译：用于清洁膜模块的装置及其方法
公开(公告)号：US20100192976A1
公开(公告)日：2010-08-05
申请号：US12669392
申请日：2008-08-11
申请人： Kwang-Jin Lee , Sung-Hak Choi , Moo-Seok Lee
发明人： Kwang-Jin Lee , Sung-Hak Choi , Moo-Seok Lee
IPC分类号： B08B7/04 , B08B3/00
CPC分类号： B01D65/025 , B01D2321/02 , B01D2321/16
摘要： Disclosed are an apparatus for cleaning a membrane module and a method therefor, which can minimize consumption of chemicals required to clean the membrane module while maximizing a recovery cleaning rate of the membrane module without completely stopping a water treatment operation. The cleaning apparatus includes a first flushing bath for flushing a membrane module transferred from a water treatment tank, and a first chemical cleaning bath for cleaning the membrane module, which has been completely flushed and transferred from the first flushing bath, by use of a first chemical solution.
摘要翻译：公开了一种用于清洁膜组件的设备及其方法，其可以最大限度地提高膜组件的回收清洁率而不会完全停止水处理操作来最小化清洁膜组件所需的化学品的消耗。清洗装置包括用于冲洗从水处理槽传送的膜组件的第一冲洗槽和用于清洗已经被完全冲洗并从第一冲洗槽传送的膜组件的第一化学清洗槽，化学溶液。

7. 发明授权

US07751234B2 Phase change memory device and program method thereof 有权
标题翻译：相变存储器件及其编程方法
公开(公告)号：US07751234B2
公开(公告)日：2010-07-06
申请号：US12168742
申请日：2008-07-07
申请人： Kwang-Jin Lee , Du-Eung Kim , Sang-Beom Kang , Woo-Yeong Cho
发明人： Kwang-Jin Lee , Du-Eung Kim , Sang-Beom Kang , Woo-Yeong Cho
IPC分类号： G11C11/56
CPC分类号： G11C5/145 , G11C7/1078 , G11C7/1096 , G11C11/5678 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2213/79
摘要： A phase change memory device includes a memory cell having a phase change material, a write driver adapted to supply a program current to the memory cell during a programming interval, and a pump circuit adapted to enhance a current supply capacity of the write driver during the programming interval. The pump circuit is activated prior to the programming interval in response to an external control signal.
摘要翻译：相变存储器件包括具有相变材料的存储单元，适于在编程间隔期间向存储单元提供编程电流的写入驱动器，以及用于在写入驱动器期间增强写入驱动器的电流供应容量的泵电路编程间隔。泵电路响应于外部控制信号在编程间隔之前被激活。

8. 发明申请

US20100118593A1 VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM THEREOF 有权
标题翻译：可变电阻存储器件及其系统
公开(公告)号：US20100118593A1
公开(公告)日：2010-05-13
申请号：US12619016
申请日：2009-11-16
申请人： Woo-Yeong Cho , Jong-Soo Seo , Young-Kug Moon , Jun-Soo Bae , Kwang-Jin Lee
发明人： Woo-Yeong Cho , Jong-Soo Seo , Young-Kug Moon , Jun-Soo Bae , Kwang-Jin Lee
IPC分类号： G11C11/00 , G11C7/04 , G11C7/02 , G11C8/00
CPC分类号： G11C13/0064 , G11C7/04 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0076 , G11C2013/0078 , G11C2213/72 , H01L27/2409 , H01L29/868 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/148
摘要： A phase-change random access memory device is provided. The phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit, multiple local bit lines, each being connected to multiple phase-change memory cells, and multiple column select transistors selectively connecting the global bit line with each of the multiple local bit lines, each column select transistor having a resistance that varies depending on its distance from the write circuit and the read circuit.
摘要翻译：提供了相变随机存取存储器件。相变随机存取存储器件包括连接到写入电路和读取电路的全局位线，每个连接到多个相变存储器单元的多个局部位线，以及选择性地连接全局位线的多个列选择晶体管对于多个局部位线中的每一个，每个列选择晶体管具有根据其与写入电路和读取电路的距离而变化的电阻。

9. 发明授权

US07548467B2 Bias voltage generator and method generating bias voltage for semiconductor memory device 有权
标题翻译：用于半导体存储器件的偏置电压发生器和产生偏置电压的方法
公开(公告)号：US07548467B2
公开(公告)日：2009-06-16
申请号：US11955562
申请日：2007-12-13
申请人： Hye-Jin Kim , Kwang-Jin Lee , Woo-Yeong Cho , Mu-Hui Park
发明人： Hye-Jin Kim , Kwang-Jin Lee , Woo-Yeong Cho , Mu-Hui Park
IPC分类号： G11C5/14
CPC分类号： G11C13/004 , G11C5/147 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0038 , G11C16/30 , G11C2013/0054 , G11C2213/72
摘要： There are provided a bias voltage generator, a semiconductor memory device having the bias voltage generator, and a method for generating the bias voltage. The bias voltage generator which generates the bias voltage to control a sensing current supplied to a memory cell for sensing data is characterized in that the bias voltage is output in response to an input voltage being applied, so that a slope of the bias voltage to the input voltage is different in at least two sections divided corresponding to a level of the input voltage.
摘要翻译：提供了偏置电压发生器，具有偏置电压发生器的半导体存储器件以及用于产生偏置电压的方法。产生用于控制提供给存储单元的感测电流以感测数据的偏置电压的偏置电压发生器的特征在于，响应于所施加的输入电压而输出偏置电压，使得偏置电压的斜率至少两个部分的输入电压不同，对应于输入电压的电平。

10. 发明申请

US20080109700A1 SEMICONDUCTOR MEMORY DEVICE AND DATA ERROR DETECTION AND CORRECTION METHOD OF THE SAME 失效
标题翻译：半导体存储器件及其数据错误检测及校正方法
公开(公告)号：US20080109700A1
公开(公告)日：2008-05-08
申请号：US11773214
申请日：2007-07-03
申请人： Kwang-Jin Lee , Won-Seok Lee , Du-Eung Kim
发明人： Kwang-Jin Lee , Won-Seok Lee , Du-Eung Kim
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F11/1076 , G11C8/04 , G11C8/12
摘要： A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.
摘要翻译：半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为检测并输出校正的读取数据。

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