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1. 发明授权

US06403416B1 Method for making a double-cylinder-capacitor structure for dynamic random access memory (DRAM) 有权
标题翻译：制造用于动态随机存取存储器（DRAM）的双缸电容器结构的方法
公开(公告)号：US06403416B1
公开(公告)日：2002-06-11
申请号：US09226279
申请日：1999-01-07
申请人： Kuo Ching Huang , Yu-Hua Lee , James (Cheng-Ming) Wu , Wen-Chuan Chiang
发明人： Kuo Ching Huang , Yu-Hua Lee , James (Cheng-Ming) Wu , Wen-Chuan Chiang
IPC分类号： H01L218242
CPC分类号： H01L28/91
摘要： A method using a single masking step for making double-cylinder stacked capacitors for DRAMs which increases capacitance while eliminating erosion of an underlying oxide insulating layer when the masking step is misaligned is described. A planar silicon oxide (SiO2) first insulating layer is formed over device areas, and a first silicon nitride (Si3N4) etch-stop layer is deposited, and openings are etched for capacitor node contacts. A first polysilicon layer is deposited to a thickness sufficient to fill the openings and to form an essentially planar surface. A second insulating layer is deposited and patterned to form portions with vertical sidewalls over the node contacts. A conformal second Si3N4 layer is deposited and etched back to form spacers on the vertical sidewalls, and the first polysilicon layer is etched to the first Si3N4 layer. The second insulating layer is selectively removed using HF acid while the first polysilicon and first Si3N4 layers prevent etching of the underlying first SiO2 layer. A second polysilicon layer is deposited and etched back to form double-cylinder sidewalls for the capacitor bottom electrodes. The first and second Si3N4 layers are removed in hot phosphoric acid. The capacitors are completed by forming an interelectrode dielectric layer on the bottom electrodes, and depositing a third polysilicon layer for top electrodes.
摘要翻译：描述了一种使用单个掩模步骤来制造用于DRAM的双圆柱体堆叠电容器的方法，其在掩蔽步骤未对准时消除了下面的氧化物绝缘层的侵蚀，同时增加了电容。在器件区域上形成平面氧化硅（SiO 2）第一绝缘层，并沉积第一氮化硅（Si 3 N 4）蚀刻停止层，并且蚀刻用于电容器节点接触的开口。第一多晶硅层被沉积到足以填充开口并形成基本平坦的表面的厚度。沉积和图案化第二绝缘层以在节点接触件上形成具有垂直侧壁的部分。沉积保形第二Si 3 N 4层并回蚀刻以在垂直侧壁上形成间隔物，并且将第一多晶硅层蚀刻到第一Si 3 N 4层。使用HF酸选择性地除去第二绝缘层，而第一多晶硅和第一Si 3 N 4层防止蚀刻下面的第一SiO 2层。沉积第二多晶硅层并将其回蚀以形成用于电容器底部电极的双气缸侧壁。在热磷酸中除去第一和第二Si 3 N 4层。电容器通过在底部电极上形成电极间电介质层而形成，并且为顶部电极沉积第三多晶硅层。

2. 发明授权

US06103455A Method to form a recess free deep contact 失效
标题翻译：形成无凹陷深层接触的方法
公开(公告)号：US06103455A
公开(公告)日：2000-08-15
申请号：US73947
申请日：1998-05-07
申请人： Kuo Ching Huang , Wen-Chuan Chiang , Cheng-Ming Wu , Yu-Hua Lee
发明人： Kuo Ching Huang , Wen-Chuan Chiang , Cheng-Ming Wu , Yu-Hua Lee
IPC分类号： H01L21/768 , G03F7/26
CPC分类号： H01L21/76876 , H01L21/76802 , H01L21/7684 , H01L21/76843 , H01L21/7688
摘要： A method of forming a deep contact by forming a dielectric layer 20 over a semiconductor structure 10. A main point is that the hard mask 30 is removed after the plug 52 is formed. A hard mask layer 30 is formed over the dielectric layer 20. A contact photoresist layer 36 is formed over the hard mask layer 30. The hard mask layer 30 is etched through the contact photoresist opening 39 to form a contact hard mask opening 41 exposing the dielectric layer 20. The dielectric layer 20 is etched using a high density plasma etch process using the contact photoresist layer 36 and the hard mask layer 30 as an etch mask forming a contact hole 40 in the dielectric layer 20. The contact photoresist layer 36 is removed. A metal layer 50 is formed filling the contact hole 40 and covering over the hard mask layer 30. The metal layer 50 is etched back forming a plug 52 filling the contact hole 40. Now, the hard mask layer 30 is removed. The removal of the hard mask 30 after the metal layer 50 deposition: (a) prevents the contact hole 40 from being contaminated from photoresist and other contamination formed during the hard mask 30 removal steps; and (b) creates a plug 52 that does not have a recess.
摘要翻译：通过在半导体结构10上形成电介质层20来形成深度接触的方法。主要的一点是在形成插头52之后去除硬掩模30。在电介质层20上形成硬掩模层30.在硬掩模层30之上形成接触光刻胶层36.硬掩模层30通过接触光致抗蚀剂开口39蚀刻以形成接触硬掩模开口41，电介质层20.使用接触光致抗蚀剂层36和硬掩模层30作为在电介质层20中形成接触孔40的蚀刻掩模的高密度等离子体蚀刻工艺来蚀刻电介质层20.接触光致抗蚀剂层36是删除。形成填充接触孔40并覆盖在硬掩模层30上的金属层50.金属层50被回蚀，形成填充接触孔40的插塞52.现在，去除硬掩模层30。在金属层50沉积之后去除硬掩模30：（a）防止接触孔40在硬掩模30去除步骤期间被光致抗蚀剂和其它污染物污染; 和（b）产生不具有凹部的插头52。

3. 发明授权

US6015734A Method for improving the yield on dynamic random access memory (DRAM) with cylindrical capacitor structures 有权
标题翻译：用于提高具有圆柱形电容器结构的动态随机存取存储器（DRAM）的产量的方法
公开(公告)号：US6015734A
公开(公告)日：2000-01-18
申请号：US148561
申请日：1998-09-04
申请人： Kuo Ching Huang , Yu Hua Lee , Cheng-Ming Wu
发明人： Kuo Ching Huang , Yu Hua Lee , Cheng-Ming Wu
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A new method for forming stacked capacitors for DRAMs having improved yields when the bottom electrode is misaligned to the node contact is achieved. A planar silicon oxide (SiO.sub.2) first insulating layer, a Si.sub.3 N.sub.4 etch-stop layer, and a disposable second insulating layer are deposited. First openings for node contacts are etched in the insulating layers. A polysilicon layer is deposited and etched back to form node contacts in the first openings. The node contacts are recessed in the second insulating layer, but above the etch-stop layer to form node contacts abutting the etch-stop layer. A disposable third SiO.sub.2 layer is deposited. Second openings for bottom electrodes are etched over and to the node contacts. A conformal second polysilicon layer is deposited and chem/mech polished back to form the bottom electrodes in the second openings. The third and second insulating layers are removed by wet etching to the etch-stop layer. When the second openings are misaligned over the node contact openings, the polysilicon plugs abutting the Si.sub.3 N.sub.4 etch-stop layer protect the SiO.sub.2 first insulating layer from being eroded over the devices on the substrate. The capacitors are completed by forming a thin dielectric layer on the bottom electrodes, and forming top electrodes from a patterned third polysilicon layer.
摘要翻译：实现了当底电极不对准节点接触时，用于形成具有提高的产量的DRAM的叠层电容器的新方法。沉积平面氧化硅（SiO 2）第一绝缘层，Si 3 N 4蚀刻停止层和一次性第二绝缘层。在绝缘层中蚀刻用于节点接触的第一开口。沉积多晶硅层并回蚀刻以在第一开口中形成节点接触。节点触点凹陷在第二绝缘层中，但在蚀刻停止层之上，以形成邻接蚀刻停止层的节点触点。沉积一次性第三SiO 2层。底部电极的第二个开口被蚀刻到节点触点上。沉积保形的第二多晶硅层，并在第二开口中化学/机械抛光以形成底部电极。第三绝缘层和第二绝缘层通过湿法蚀刻去除蚀刻停止层。当第二开口在节点接触开口上不对准时，邻接Si 3 N 4蚀刻停止层的多晶硅栓保护SiO 2第一绝缘层免受衬底上的器件的侵蚀。通过在底部电极上形成薄的电介质层，并从图案化的第三多晶硅层形成顶部电极来完成电容器。

4. 发明授权

US06307213B1 Method for making a fuse structure for improved repaired yields on semiconductor memory devices 有权
标题翻译：制造用于提高半导体存储器件修复产量的熔丝结构的方法
公开(公告)号：US06307213B1
公开(公告)日：2001-10-23
申请号：US09617427
申请日：2000-07-14
申请人： Kuo Ching Huang , Tse-Liang Ying , Cheng Yeh Shih , Yu Hua Lee , Cheng-Ming Wu
发明人： Kuo Ching Huang , Tse-Liang Ying , Cheng Yeh Shih , Yu Hua Lee , Cheng-Ming Wu
IPC分类号： H01L2904
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： This invention relates to a novel fuse structure and method for deleting redundant circuit elements on integrated circuits. This fuse structure is useful for increasing the repair yield on RAM chips by deleting defective rows of memory cells. The method involves forming a fuse area in a patterned electrically conducting layer also used to form interconnections. A relatively thin (0.4 um) insulating layer is deposited having a uniform thickness across the substrate. The next level of patterned interconnections is formed with a portion of the layer aligned over the fuse area to serve as an etch-stop layer. For example, the conducting layers can be the first and second poly-silicon layers on a RAM chip. The remaining multilevel of interconnections is then formed having a number of relatively thick interlevel dielectric (ILD) layers interposed which can have an accumulative large variation in thickness across the substrate. Fuse windows (openings) are then selectively etched in the ILD layers to the etch-stop layer and the etch-stop layer is selectively etched in the fuse window to the insulating layer over the fuse area. This process allows fuse structures to be built without overetching that can cause fuse damage. The uniform thick insulating layer allows repeatable and reliable laser abrading (evaporation) to open the desired fuses.
摘要翻译：本发明涉及一种用于删除集成电路上的冗余电路元件的新型熔丝结构和方法。该熔丝结构可用于通过删除存储单元的有缺陷的行来增加RAM芯片的修复产量。该方法包括在也用于形成互连的图案化导电层中形成熔丝区域。沉积相对薄的（0.4μm）绝缘层，其跨越衬底具有均匀的厚度。下一级图案互连形成，其中一部分层在保险丝区域上对齐以用作蚀刻停止层。例如，导电层可以是RAM芯片上的第一和第二多晶硅层。然后形成剩余的多层互连件，其具有插入的多个相对较厚的层间电介质层（ILD）层，其可跨越衬底具有累积的厚度变化。然后在ILD层中选择性地将保险丝窗（开口）蚀刻到蚀刻停止层，并且将蚀刻停止层选择性地在保险丝窗口中蚀刻到保险丝区域上的绝缘层。该过程允许熔断器结构被建立，而不会导致熔断器损坏。均匀的厚绝缘层允许可重复且可靠的激光研磨（蒸发）来打开所需的保险丝。

5. 发明授权

US6121073A Method for making a fuse structure for improved repaired yields on semiconductor memory devices 失效
标题翻译：制造用于提高半导体存储器件修复产量的熔丝结构的方法
公开(公告)号：US6121073A
公开(公告)日：2000-09-19
申请号：US24479
申请日：1998-02-17
申请人： Kuo Ching Huang , Tse-Liang Ying , Cheng Yeh Shih , Yu Hua Lee , Cheng-Ming Wu
发明人： Kuo Ching Huang , Tse-Liang Ying , Cheng Yeh Shih , Yu Hua Lee , Cheng-Ming Wu
IPC分类号： H01L23/525 , H01L21/82 , H01L27/10
CPC分类号： H01L23/5258 , H01L2924/0002
摘要： This invention relates to a novel fuse structure and method for deleting redundant circuit elements on integrated circuits. This fuse structure is useful for increasing the repair yield on RAM chips by deleting defective rows of memory cells. The method involves forming a fuse area in a patterned electrically conducting layer also used to form interconnections. A relatively thin (0.4 um) insulating layer is deposited having a uniform thickness across the substrate. The next level of patterned interconnections is formed with a portion of the layer aligned over the fuse area to serve as an etch-stop layer. For example, the conducting layers can be the first and second polysilicon layers on a RAM chip. The remaining multilevel of interconnections is then formed having a number of relatively thick interlevel dielectric (ILD) layers interposed which can have an accumulative large variation in thickness across the substrate. Fuse windows (openings) are then selectively etched in the ILD layers to the etch-stop layer and the etch-stop layer is selectively etched in the fuse window to the insulating layer over the fuse area. This process allows fuse structures to be built without overetching that can cause fuse damage. The uniform thick insulating layer allows repeatable and reliable laser abrading (evaporation) to open the desired fuses.
摘要翻译：本发明涉及一种用于删除集成电路上的冗余电路元件的新型熔丝结构和方法。该熔丝结构可用于通过删除存储单元的有缺陷的行来增加RAM芯片的修复产量。该方法包括在也用于形成互连的图案化导电层中形成熔丝区域。沉积相对薄的（0.4μm）绝缘层，其跨越衬底具有均匀的厚度。下一级图案互连形成，其中一部分层在保险丝区域上对齐以用作蚀刻停止层。例如，导电层可以是RAM芯片上的第一和第二多晶硅层。然后形成剩余的多层互连件，其具有插入的多个相对较厚的层间电介质层（ILD）层，其可跨越衬底具有累积的厚度变化。然后在ILD层中选择性地将保险丝窗（开口）蚀刻到蚀刻停止层，并且将蚀刻停止层选择性地在保险丝窗口中蚀刻到保险丝区域上的绝缘层。该过程允许熔断器结构被建立，而不会导致熔断器损坏。均匀的厚绝缘层允许可重复且可靠的激光研磨（蒸发）来打开所需的保险丝。

6. 发明授权

US06287939B1 Method for fabricating a shallow trench isolation which is not susceptible to buried contact trench formation 有权
标题翻译：用于制造不易于埋入接触沟槽形成的浅沟槽隔离的方法
公开(公告)号：US06287939B1
公开(公告)日：2001-09-11
申请号：US09216789
申请日：1998-12-21
申请人： Kuo Ching Huang , Tse-Liang Ying , Wen-Chuan Chiang
发明人： Kuo Ching Huang , Tse-Liang Ying , Wen-Chuan Chiang
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/76895
摘要： The invention provides a method for fabricating a shallow trench isolation which is not susceptable to buried contact trench formation. The invention also provides immunity from the STI “kink effect,” as well as benefits associated with nitridation. The process begins by forming a pad oxide layer on a semiconductor substrate. A nitride layer is formed on the pad oxide layer. The nitride layer, the pad oxide layer, and the semiconductor substrate are patterned to form trenches. Next, a fill oxide layer is formed over the nitride layer, the pad oxide layer, and the semiconductor substrate. The fill oxide layer is chemical-mechanical polished, stopping on the nitride layer to form fill oxide regions. N2 ions are implanted into the fill oxide regions. An anneal is performed to form a buried oxynitride layer. The buried oxynitride layer is partially above the level of the top surface of the semiconductor substrate and partially below the level of the top surface of the semiconductor substrate. The nitride layer is removed. Then, the pad oxide layer and portions of the fill oxide regions are removed using the buried oxynitride layer as an etch stop, forming shallow trench isolations.
摘要翻译：本发明提供一种用于制造不易于埋入接触沟槽形成的浅沟槽隔离的方法。本发明还提供了对STI“扭结效应”的免疫力以及与氮化相关的益处。该过程开始于在半导体衬底上形成衬垫氧化物层。在衬垫氧化物层上形成氮化物层。图案化氮化物层，衬垫氧化物层和半导体衬底以形成沟槽。接下来，在氮化物层，衬垫氧化物层和半导体衬底之上形成填充氧化物层。填充氧化物层进行化学机械抛光，在氮化物层上停止形成填充氧化物区域。将N 2离子注入填充氧化物区域。进行退火以形成掩埋的氮氧化物层。掩埋的氧氮化物层部分地高于半导体衬底的顶表面的高度，并且部分地低于半导体衬底的顶表面的水平。去除氮化物层。然后，使用掩埋氧氮化物层作为蚀刻停止层，去除衬垫氧化物层和填充氧化物区域的部分，形成浅沟槽隔离。

7. 发明授权

US6080637A Shallow trench isolation technology to eliminate a kink effect 有权
标题翻译：浅沟槽隔离技术消除扭结效应
公开(公告)号：US6080637A
公开(公告)日：2000-06-27
申请号：US206736
申请日：1998-12-07
申请人： Kuo Ching Huang , Tse-Liang Ying , Wen-Chuan Chiang , Cheng-Yeh Shih
发明人： Kuo Ching Huang , Tse-Liang Ying , Wen-Chuan Chiang , Cheng-Yeh Shih
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A process for creating an insulator filled, shallow trench, in a semiconductor substrate, in which the insulator layer in the shallow trench, is not exposed to procedures used to remove defining composite insulator layers, has been developed. The process features creating a lateral recess, in a thick silicon nitride layer, used as a component of a composite insulator layer, where the composite insulator layer is used for subsequent definition of the shallow trench, in the semiconductor substrate. An insulator deposition, filling openings, and recesses, in the composite insulator layer, and filling the shallow trench, followed by removal of excess insulator fill, on the top surface of the composite insulator layer, results in the formation of a "T" shape insulator, comprised of an insulator shape, in the shallow trench, and comprised of a wider insulator shape, located in the composite insulator shape, with the lateral recess in the thick silicon nitride layer, and with the wider insulator shape, overlying the narrow, insulator shape, in the shallow trench. The insulator, in the shallow trench, is protected from the procedure used to remove components of the composite insulator layer, by the wider insulator shape.
摘要翻译：已经开发了在半导体衬底中形成绝缘体填充的浅沟槽的方法，其中浅沟槽中的绝缘体层不暴露于用于移除限定复合绝缘体层的程序。该工艺的特征是在半导体衬底中产生在厚氮化硅层中用作复合绝缘体层的组分的横向凹槽，其中复合绝缘体层用于随后定义浅沟槽。在复合绝缘体层中的绝缘体沉积，填充开口和凹陷，以及填充浅沟槽，然后在复合绝缘体层的顶表面上除去多余的绝缘体填充物，导致形成“T”形绝缘体，由绝缘体形状构成，位于浅沟槽中，并且由更宽的绝缘体形状组成，位于复合绝缘体形状中，侧壁凹陷在厚氮化硅层中，并且具有更宽的绝缘体形状，绝缘体形状，在浅沟槽。通过更宽的绝缘体形状，在浅沟槽中的绝缘体被保护以避免用于去除复合绝缘体层的部件的程序。

8. 发明授权

US6080647A Process to form a trench-free buried contact 失效
标题翻译：形成无沟槽埋层接触的工艺
公开(公告)号：US6080647A
公开(公告)日：2000-06-27
申请号：US34927
申请日：1998-03-05
申请人： Kuo Ching Huang , Yean-Kuen Fang , Mong-Song Liang , Jhon-Jhy Liaw , Cheng-Ming Wu , Dun-Nian Yaung
发明人： Kuo Ching Huang , Yean-Kuen Fang , Mong-Song Liang , Jhon-Jhy Liaw , Cheng-Ming Wu , Dun-Nian Yaung
IPC分类号： H01L21/336 , H01L21/768 , H01L21/3205
CPC分类号： H01L29/6659 , H01L21/76895 , H01L29/66545
摘要： A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact. A tungsten layer is selectively deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines to form polycide gate electrodes and interconnection lines. The dielectric material layer is anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.
摘要翻译：描述了形成改进的埋地接触结的新方法。在半导体衬底的表面上设置栅极氧化硅层。沉积在栅极氧化物层上的多晶硅层。覆盖多晶硅层的硬掩模层被沉积。硬掩模和多晶硅层被蚀刻掉，在那里它们不被掩模覆盖以形成多晶硅栅电极和具有其上的氮化硅层的互连线，其中在栅电极和互连线之间留有间隙。介电材料层沉积在衬底上以填充间隙。去除了掩模层。此后，多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。将离子注入到开口内的半导体衬底中以形成掩埋接触。选择性地沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的钨层以形成多晶硅栅极电极和互连线。电介质材料层被各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

9. 发明授权

US06271570B1 Trench-free buried contact 有权
标题翻译：无沟槽埋地接触
公开(公告)号：US06271570B1
公开(公告)日：2001-08-07
申请号：US09578414
申请日：2000-05-26
申请人： Kuo Ching Huang , Yean-Kuen Fang , Mong-Song Liang , Jhon-Jhy Liaw , Cheng-Ming Wu , Dun-Nian Yaung
发明人： Kuo Ching Huang , Yean-Kuen Fang , Mong-Song Liang , Jhon-Jhy Liaw , Cheng-Ming Wu , Dun-Nian Yaung
IPC分类号： H01L2976
CPC分类号： H01L29/6659 , H01L21/76895 , H01L29/66545
摘要： A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact. A tungsten layer is selectively deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines to form polycide gate electrodes and interconnection lines. The dielectric material layer is anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.
摘要翻译：描述了形成改进的埋地接触结的新方法。在半导体衬底的表面上设置栅极氧化硅层。沉积在栅极氧化物层上的多晶硅层。覆盖多晶硅层的硬掩模层被沉积。硬掩模和多晶硅层被蚀刻掉，在那里它们不被掩模覆盖以形成多晶硅栅电极和具有其上的氮化硅层的互连线，其中在栅电极和互连线之间留有间隙。介电材料层沉积在衬底上以填充间隙。去除了掩模层。此后，多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。将离子注入到开口内的半导体衬底中以形成掩埋接触。选择性地沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的钨层以形成多晶硅栅极电极和互连线。电介质材料层被各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

10. 发明授权

US6162686A Method for forming a fuse in integrated circuit application 有权
标题翻译：集成电路应用中形成保险丝的方法
公开(公告)号：US6162686A
公开(公告)日：2000-12-19
申请号：US156362
申请日：1998-09-18
申请人： Kuo Ching Huang , Tse-Liang Ying , Yu-Hua Lee , Ming-Hsin Li
发明人： Kuo Ching Huang , Tse-Liang Ying , Yu-Hua Lee , Ming-Hsin Li
IPC分类号： H01L23/525 , H01L21/336 , H01L21/00 , H01L21/331 , H01L21/44 , H01L21/82
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a grooved fuse (plug fuse) in the same step that via plugs are formed in the guard ring area 14 and in product device areas. A key point of the invention is to form fuses from the via plug layer, not from the metal layers. Also, key guard rings are formed around the plug guise. The invention can include the following: a semiconductor structure is provided having a fuse area, a guard ring area surrounding the fuse area; and a device area. First and second conductive strips are formed. First and second insulating layers are formed over the first and second conductive strips. Plug contacts and fuse plugs are formed through the first and second insulating layers to the first and second conductive strips. A third insulating layer is formed over the second insulating layer. Metal lines are formed over the third insulating layer in the device area. A fuse via opening is formed in the third insulating layer. A plug fuse is formed in the fuse via opening. A fourth insulating layer is formed over the plug fuse and the third insulating layer. A fuse opening is formed at least partially though the fourth insulating layer over the fuse area.
摘要翻译：在通过塞子形成在保护环区域14和产品装置区域中的相同步骤中形成带槽保险丝（插头保险丝）的方法。本发明的一个关键点是从通孔塞层而不是金属层形成保险丝。此外，围绕插头形状形成关键保护环。本发明可以包括：提供具有保险丝区域的半导体结构，围绕保险丝区域的保护环区域; 和设备区域。形成第一和第二导电条。第一和第二绝缘层形成在第一和第二导电条上。插头触点和熔丝插头通过第一和第二绝缘层形成到第一和第二导电条。在第二绝缘层上形成第三绝缘层。金属线形成在器件区域中的第三绝缘层上。在第三绝缘层中形成保险丝通孔。保险丝通过开口形成插头保险丝。在插头熔断器和第三绝缘层上形成第四绝缘层。保险丝开口至少部分地通过保险丝区域上的第四绝缘层形成。

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