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1. 发明申请

US20130179716A1 Dynamically Adjusting Power Of Non-Core Processor Circuitry 审中-公开
标题翻译：动态调整非核心处理器电路的功率
公开(公告)号：US20130179716A1
公开(公告)日：2013-07-11
申请号：US13780052
申请日：2013-02-28
申请人： Krishnakanth Sistla , Dean Mulla , Vivek Garg , Mark Rowland , Suresh Doraiswamy , Ganapati Srinivasa , Jeffrey D. Gilbert
发明人： Krishnakanth Sistla , Dean Mulla , Vivek Garg , Mark Rowland , Suresh Doraiswamy , Ganapati Srinivasa , Jeffrey D. Gilbert
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F13/4022 , Y02D10/126
摘要： In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有包括多个核心的可变频域和该处理器的至少一部分非核心电路的多核处理器。该非核心部分可以包括高速缓冲存储器，高速缓存控制器和互连结构。除了该可变频域之外，处理器还可以具有包括功率控制单元（PCU）的固定频域。该单元可以被配置为引起对可变频域的频率改变，而不会排除待处理事务的非核心部分。描述和要求保护其他实施例。

2. 发明申请

US20130080795A1 Dynamically Adjusting Power Of Non-Core Processor Circuitry 有权
公开(公告)号：US20130080795A1
公开(公告)日：2013-03-28
申请号：US13247594
申请日：2011-09-28
申请人： Krishnakanth Sistla , Dean Mulla , Vivek Garg , Mark Rowland , Suresh Doraiswamy , Ganapati Srinivasa , Jeffrey D. Gilbert
发明人： Krishnakanth Sistla , Dean Mulla , Vivek Garg , Mark Rowland , Suresh Doraiswamy , Ganapati Srinivasa , Jeffrey D. Gilbert
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F13/4022 , Y02D10/126
摘要： In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.

3. 发明授权

US08914650B2 Dynamically adjusting power of non-core processor circuitry including buffer circuitry 有权
标题翻译：动态调整包括缓冲电路在内的非核心处理器电路的功率
公开(公告)号：US08914650B2
公开(公告)日：2014-12-16
申请号：US13247594
申请日：2011-09-28
申请人： Krishnakanth Sistla , Dean Mulla , Vivek Garg , Mark Rowland , Suresh Doraiswamy , Ganapati Srinivasa , Jeffrey D. Gilbert
发明人： Krishnakanth Sistla , Dean Mulla , Vivek Garg , Mark Rowland , Suresh Doraiswamy , Ganapati Srinivasa , Jeffrey D. Gilbert
IPC分类号： G06F1/32 , G06F13/40
CPC分类号： G06F1/324 , G06F13/4022 , Y02D10/126
摘要： In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有包括多个核心的可变频域和该处理器的至少一部分非核心电路的多核处理器。该非核心部分可以包括高速缓冲存储器，高速缓存控制器和互连结构。除了该可变频域之外，处理器还可以具有包括功率控制单元（PCU）的固定频域。该单元可以被配置为引起对可变频域的频率改变，而不会排除待处理事务的非核心部分。描述和要求保护其他实施例。

4. 发明申请

US20130311804A1 MASTER SLAVE QPI PROTOCOL FOR COORDINATED IDLE POWER MANAGEMENT IN GLUELESS AND CLUSTERED SYSTEMS 审中-公开
标题翻译：用于协调无障碍和集群系统中的空闲电源管理的主从QPI协议
公开(公告)号：US20130311804A1
公开(公告)日：2013-11-21
申请号：US13994294
申请日：2012-04-30
申请人： Vivek Garg , Krishnakanth KK Sistla , Robert Rob Blankenship , Dean Mulla , Daniel Dan Borkowski , Shaun Conrad , Ganapati Gans Srinivasa
发明人： Vivek Garg , Krishnakanth KK Sistla , Robert Rob Blankenship , Dean Mulla , Daniel Dan Borkowski , Shaun Conrad , Ganapati Gans Srinivasa
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3234 , Y02D50/20
摘要： Methods, apparatus, and systems for implementing coordinated idle power management in glueless and clustered systems. Components for facilitating coordination of package idle power state between sockets in a glueless system such as a server platform include a master entity in one socket (i.e., processor) and a slave entity in each socket participating in the power management coordination. Each slave collects idle status inputs from various sources and when the socket cores are sufficiently idle, it makes a request to the master to enter a deeper idle power state. The master coordinates global power management operations in response to the slave requests, including broadcasting a command with a target latency to all of the slaves to allow the processors to enter reduced power (i.e., idle) states in a coordinated manner. Communications between the entities is facilitated using messages transported over existing interconnects and corresponding protocols, enabling the benefits associated with the disclosed embodiments to be implemented using existing designs.
摘要翻译：在无缝和集群系统中实现协调空闲电源管理的方法，设备和系统。在诸如服务器平台的无胶纸系统中的用于促进协调包间歇功率状态的组件包括一个插座（即，处理器）中的主实体和参与电力管理协调的每个插座中的从实体。每个从机从各种来源收集空闲状态输入，当插座内核足够空闲时，它要求主机进入更深的空闲电源状态。主机响应于从机请求来协调全局功率管理操作，包括向所有从机广播具有目标延迟的命令，以允许处理器以协调的方式进入降低的功率（即空闲）状态。使用通过现有互连和相应协议传输的消息来促进实体之间的通信，从而能够使用现有设计实现与公开的实施例相关联的益处。

5. 发明授权

US08769295B2 Computing system feature activation mechanism 有权
标题翻译：计算系统功能激活机制
公开(公告)号：US08769295B2
公开(公告)日：2014-07-01
申请号：US11195105
申请日：2005-08-01
申请人： Dean Mulla , Rahul Khanna , Keith R. Pflederer
发明人： Dean Mulla , Rahul Khanna , Keith R. Pflederer
IPC分类号： G06F21/00 , G06F21/31 , G06F21/10
CPC分类号： G06F21/31 , G06F21/10 , G06F21/73
摘要： Embodiments of the invention are generally directed to apparatuses, methods, and systems for a computing system feature activation mechanism. In an embodiment, a computing system receives a remotely generated feature activation information. The computing system compares the remotely generated feature activation information with a built-in feature activation mechanism. In an embodiment, a feature of the computing system is activated if the remotely generated feature activation information matches the built-in feature activation mechanism. Other embodiments are described and claimed.
摘要翻译：本发明的实施例一般涉及用于计算系统特征激活机制的装置，方法和系统。在一个实施例中，计算系统接收远程产生的特征激活信息。计算系统将远程生成的特征激活信息与内置的特征激活机制进行比较。在一个实施例中，如果远程生成的特征激活信息与内置特征激活机制匹配，则激活计算系统的特征。描述和要求保护其他实施例。

6. 发明申请

US20050149314A1 Apparatus and method to enable transparent memory hot plug/remove 有权
标题翻译：启用透明内存热插拔/移除的设备和方法
公开(公告)号：US20050149314A1
公开(公告)日：2005-07-07
申请号：US10749929
申请日：2003-12-29
申请人： Lily Looi , Stanley Kulick , Dean Mulla , Ashish Gupta , Keith Pflederer , Shivnandan Kaushik , Mohan Kumar , James Crossland
发明人： Lily Looi , Stanley Kulick , Dean Mulla , Ashish Gupta , Keith Pflederer , Shivnandan Kaushik , Mohan Kumar , James Crossland
IPC分类号： G06F9/455 , G06F11/20 , G06F13/16
CPC分类号： G06F11/1666 , G06F13/16
摘要： In some embodiments, an apparatus includes a processor, an expander memory bridge location, a memory coupled to the expander memory bridge location, and a bus controller including intercept logic to intercept and block communication from the processor to the expander memory bridge location and to emulate an expander memory bridge. In some embodiments, a method includes intercepting and blocking a status request to a device, regardless of whether the device is installed, and responding to the status request.
摘要翻译：在一些实施例中，一种装置包括处理器，扩展器存储器桥位置，耦合到扩展器存储器桥位置的存储器，以及总线控制器，其包括拦截和阻止从处理器到扩展器存储器桥位置的通信的截距逻辑，并且模拟一个扩展记忆桥。在一些实施例中，一种方法包括拦截和阻止对设备的状态请求，而不管该设备是否被安装，以及响应状态请求。

7. 发明申请

US20070039054A1 Computing system feature activation mechanism 有权
标题翻译：计算系统功能激活机制
公开(公告)号：US20070039054A1
公开(公告)日：2007-02-15
申请号：US11195105
申请日：2005-08-01
申请人： Dean Mulla , Rahul Khanna , Keith Pflederer
发明人： Dean Mulla , Rahul Khanna , Keith Pflederer
IPC分类号： H04N7/16
CPC分类号： G06F21/31 , G06F21/10 , G06F21/73
摘要： Embodiments of the invention are generally directed to apparatuses, methods, and systems for a computing system feature activation mechanism. In an embodiment, a computing system receives a remotely generated feature activation information. The computing system compares the remotely generated feature activation information with a built-in feature activation mechanism. In an embodiment, a feature of the computing system is activated if the remotely generated feature activation information matches the built-in feature activation mechanism. Other embodiments are described and claimed.
摘要翻译：本发明的实施例一般涉及用于计算系统特征激活机制的装置，方法和系统。在一个实施例中，计算系统接收远程产生的特征激活信息。计算系统将远程生成的特征激活信息与内置的特征激活机制进行比较。在一个实施例中，如果远程生成的特征激活信息与内置特征激活机制匹配，则激活计算系统的特征。描述和要求保护其他实施例。

8. 发明授权

US06948094B2 Method of correcting a machine check error 有权
标题翻译：纠正机器检查错误的方法
公开(公告)号：US06948094B2
公开(公告)日：2005-09-20
申请号：US09966386
申请日：2001-09-28
申请人： Len Schultz , Nhon Toai Quach , Dean Mulla , Jim Hays , John Fu
发明人： Len Schultz , Nhon Toai Quach , Dean Mulla , Jim Hays , John Fu
IPC分类号： G06F11/00 , G06F11/26
CPC分类号： G06F11/26 , G06F11/0706 , G06F11/0772 , G06F11/0793
摘要： Processor implementation-specific instructions save a processor state in a system memory and attempt to correct the error. Control is then transferred to processor-independent instructions. Control is returned to the processor implementation-specific instructions which then return to an interrupted context of the processor by restoring the processor state.
摘要翻译：处理器实现特定的指令将处理器状态保存在系统内存中，并尝试更正错误。然后控制转移到与处理器无关的指令。控制返回到处理器实现特定的指令，然后通过恢复处理器状态返回到处理器的中断上下文。

9. 发明授权

US5652859A Method and apparatus for handling snoops in multiprocessor caches having internal buffer queues 失效
标题翻译：用于在具有内部缓冲区队列的多处理器高速缓存中处理侦听的方法和装置
公开(公告)号：US5652859A
公开(公告)日：1997-07-29
申请号：US516421
申请日：1995-08-17
申请人： Dean Mulla , Sorin Iacobovici
发明人： Dean Mulla , Sorin Iacobovici
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0831
摘要： A method and apparatus for snooping both cache memory and associated buffer queues in a cache subsystem arrangement. Since there are usually several requests for cache data being handled at any given time under high performance operation of multiple processors, a cache arrangement includes at least one buffer queue for storing the address of the cache data line and the status of the cache data line, which facilitate keeping track of the data requests and handling them efficiently. In response to a snoop request, a snoop address is compared to the address stored in the buffer queue so as to provide a positive comparison result if the snoop address matches the address stored in the buffer queue, thereby indicating a snoop hit condition. The buffer queue of the cache arrangement further has a snoop hit bit for storing a record of the positive comparison result that indicates the snoop hit condition. Even if there is still a pending transaction involving the buffer queue, the snoop request of the cache is satisfied once the comparison result has been stored in the snoop hit bit of the buffer queue, thereby keeping the cache high performance for local code while at the same time providing efficient support for snoop requests.
摘要翻译：一种用于在高速缓存子系统布置中窥探缓存存储器和相关联的缓冲器队列的方法和装置。由于在多个处理器的高性能操作下，在任何给定时间处理高速缓存数据通常需要多个请求，所以高速缓存装置包括用于存储高速缓存数据线的地址和高速缓存数据线的状态的至少一个缓冲器队列，这有助于跟踪数据请求并有效地处理它们。响应于窥探请求，将窥探地址与存储在缓冲器队列中的地址进行比较，以便如果窥探地址与存储在缓冲器队列中的地址匹配，则提供肯定的比较结果，从而指示窥探命中条件。高速缓存装置的缓冲器队列还具有窥探命中位，用于存储指示窥探命中条件的肯定比较结果的记录。即使仍然存在涉及缓冲区队列的待处理事务，一旦将比较结果存储在缓冲区队列的窥探命中中，缓存的窥探请求便被满足，从而保持高速缓存本地代码的性能。同时为窥探请求提供有效的支持。

10. 发明申请

US20180164870A1 INSTRUCTION AND LOGIC FOR PARALLEL MULTI-STEP POWER MANAGEMENT FLOW 审中-公开
公开(公告)号：US20180164870A1
公开(公告)日：2018-06-14
申请号：US15372838
申请日：2016-12-08
申请人： Alexander Gendler , Doron Rajwan , Tal Kuzi , Dean Mulla , Ariel Szapiro , Nir Tell
发明人： Alexander Gendler , Doron Rajwan , Tal Kuzi , Dean Mulla , Ariel Szapiro , Nir Tell
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G06F1/3237 , G06F1/324 , G06F1/3296
摘要： A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.

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