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1. 发明授权

US5576247A Thin layer forming method wherein hydrophobic molecular layers preventing a BPSG layer from absorbing moisture 失效
标题翻译：疏水分子层防止BPSG层吸收水分的薄层形成方法
公开(公告)号：US5576247A
公开(公告)日：1996-11-19
申请号：US97231
申请日：1993-07-27
申请人： Kousaku Yano , Masayuki Endo , Yuka Terai , Noboru Nomura , Tomoyasu Murakami , Tetsuya Ueda , Satoshi Ueda
发明人： Kousaku Yano , Masayuki Endo , Yuka Terai , Noboru Nomura , Tomoyasu Murakami , Tetsuya Ueda , Satoshi Ueda
IPC分类号： H01L21/3105 , H01L21/316
CPC分类号： H01L21/3105 , Y10S438/974
摘要： A BPSG layer serving as a silicon oxide layer is formed on a semiconductor substrate 1. Formed on the surface of the BPSG layer is a hydrophobic molecular layer comprising hydrophobic groups such as methyl, ethyl and the like, by a silylation reaction (in which silyl having hydrophobic groups such as methyl groups, ethyl groups and the like, is reacted with OH groups, and in which the hydrophobic groups are substituted with H of the OH groups to generate --O--Si(CH.sub.3).sub.3 or the like). The molecular layer prevents the BPSG layer from absorbing moisture.
摘要翻译：在半导体衬底1上形成用作氧化硅层的BPSG层。在BPSG层的表面上形成疏水性分子层，其通过甲硅烷基化反应（甲基，具有疏水基团如甲基，乙基等与OH基团反应，并且其中疏水基团被H的OH基团取代以产生-O-Si（CH 3）3等）。分子层防止BPSG层吸湿。

2. 发明授权

US5863338A Apparatus and method for forming thin film 失效
标题翻译：用于形成薄膜的装置和方法
公开(公告)号：US5863338A
公开(公告)日：1999-01-26
申请号：US583662
申请日：1996-01-05
申请人： Yuichiro Yamada , Naoki Suzuki , Ryuzo Houchin , Noboru Nomura , Kousaku Yano , Yuka Terai
发明人： Yuichiro Yamada , Naoki Suzuki , Ryuzo Houchin , Noboru Nomura , Kousaku Yano , Yuka Terai
IPC分类号： H01L21/205 , B05D1/18 , B05D7/24 , C23C16/54 , H01L21/302 , C23C16/00
CPC分类号： B82Y30/00 , B05D1/185 , B05D1/60 , B82Y40/00 , C23C16/54
摘要： A forming apparatus of a thin film, includes a processing chamber where a predetermined process is carried out on a surface of a supplied substrate, and a feeding device, which is provided in the processing chamber, for feeding material to form an organic molecular layer including silicon or germanium on the surface of the substrate. A forming method of a thin film, includes steps of forming a thin film on a surface of a supplied substrate in a processing chamber, and feeding material for forming an organic molecular layer including silicon or germanium on the formed thin film on the surface of the substrate through a feeding device in the processing chamber, and then forming the organic molecular layer on the surface of the substrate.
摘要翻译：薄膜的成形装置包括处理室，其中在所提供的基板的表面上执行预定的处理;以及馈送装置，其设置在处理室中，用于馈送材料以形成有机分子层，所述有机分子层包括硅或锗在基板的表面上。薄膜的形成方法包括以下步骤：在处理室中的供给的基板的表面上形成薄膜，以及在所形成的薄膜上形成包含硅或锗的有机分子层的供给材料基板通过处理室中的进料装置，然后在基板的表面上形成有机分子层。

3. 发明授权

US5501739A Apparatus and method for forming thin film 失效
标题翻译：用于形成薄膜的装置和方法
公开(公告)号：US5501739A
公开(公告)日：1996-03-26
申请号：US158305
申请日：1993-11-29
申请人： Yuichiro Yamada , Naoki Suzuki , Ryuzo Houchin , Noboru Nomura , Kousaku Yano , Yuka Terai
发明人： Yuichiro Yamada , Naoki Suzuki , Ryuzo Houchin , Noboru Nomura , Kousaku Yano , Yuka Terai
IPC分类号： H01L21/205 , B05D1/18 , B05D7/24 , C23C16/54 , H01L21/302 , C23C16/00
CPC分类号： B82Y30/00 , B05D1/185 , B05D1/60 , B82Y40/00 , C23C16/54
摘要： A forming apparatus of a thin film includes a processing chamber where a predetermined process is carried out on a surface of a supplied substrate. A feeding device is provided in the processing chamber for feeding material to form an organic molecular layer including silicon or germanium on the surface of the substrate. A forming method of a thin film includes the steps of forming the thin film on the surface of the supplied substrate in the processing chamber, and feeding material for forming the organic molecular layer, including silicon or germanium, on the formed thin film on the surface of the substrate through a feeding device in the processing chamber, and then forming the organic molecular layer on the surface of the substrate.
摘要翻译：薄膜的形成装置包括处理室，其中在所提供的基板的表面上进行预定的处理。在处理室中设置有供给装置，用于供给材料以在基板的表面上形成包括硅或锗的有机分子层。薄膜的形成方法包括以下步骤：在处理室中供应的基板的表面上形成薄膜，以及在表面上形成的薄膜上形成有机分子层（包括硅或锗）的材料通过处理室中的进料装置，然后在基材表面上形成有机分子层。

4. 发明授权

US06372928B1 Layer forming material and wiring forming method 失效
标题翻译：层形成材料和布线形成方法
公开(公告)号：US06372928B1
公开(公告)日：2002-04-16
申请号：US09003826
申请日：1998-01-07
申请人： Akemi Kawaguchi , Yuka Terai , Kousaku Yano
发明人： Akemi Kawaguchi , Yuka Terai , Kousaku Yano
IPC分类号： C07F108
CPC分类号： H01L21/32051 , C23C16/18 , H01L21/76838 , H01L23/53238 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A layer forming material is a compound which has a structure of six-membered ring coordinated to Cu and containing Si, and of which general formula is represented by the following chemical formula: wherein X1 and X2 are elements of the VI group of the same or different types which are coordinate-bonded to Cu, and of which examples include O, S, Se, Te and the like, at least one of Y1, Y2 and Y3 is Si, L is a group which has a double or triple bond and which is able to supply electrons to Cu, and each of R1 and R2 is any of SiF3, SiH3, CF3 and CH3 for example.
摘要翻译：层形成材料是具有与Cu配位并含有Si的六元环结构的化合物，其通式由以下化学式表示：其中X1和X2是其VI基团的元素，与Cu配位结合的不同类型，其实例包括O，S，Se，Te等，Y1，Y2和Y3中的至少一个为Si，L为具有双键或三键的基团，其能够向Cu提供电子，并且R1和R2中的每一个例如是SiF 3，SiH 3，CF 3和CH 3中的任一种。

5. 发明授权

US5633211A Semiconductor device and process 失效
标题翻译：半导体器件和工艺
公开(公告)号：US5633211A
公开(公告)日：1997-05-27
申请号：US347114
申请日：1994-11-23
申请人： Shinichi Imai , Yuka Terai , Masanori Fukumoto , Kousaku Yano , Hiroyuki Umimoto , Shinji Odanaka , Yasuo Mizuno
发明人： Shinichi Imai , Yuka Terai , Masanori Fukumoto , Kousaku Yano , Hiroyuki Umimoto , Shinji Odanaka , Yasuo Mizuno
IPC分类号： C23C16/40 , H01L21/3105 , H01L21/316 , H01L21/02
CPC分类号： H01L21/02131 , C23C16/401 , H01L21/02126 , H01L21/02129 , H01L21/02142 , H01L21/02148 , H01L21/0215 , H01L21/02271 , H01L21/02321 , H01L21/3105 , H01L21/31625 , H01L21/31629
摘要： The characteristic of semiconductor devices is satisfactorily maintained because the planarization of a dielectric film of a semiconductor device is carried out at a lower flow temperature. In the case of a silicon dioxide film being a dielectric film, a network structure is composed of atoms of silicon which serve as a main constituent, and of atoms of oxygen which serve as a sub-constituent of a matrix of the dielectric film. These oxygen atoms are replaced by non-bridging constituents such as atoms of halogen including fluorine. This breaks a bridge, via an oxygen atom, between the silicon atoms, at a position where such a replacement takes place. In consequence, the viscosity of the dielectric film falls with the flow temperature. If, for example, part of the oxygen in a BPSG film is substituted by fluorine, this allows the dielectric film to flow at a lower temperature of 850.degree. C. The short channel effects can be suppressed.
摘要翻译：由于半导体器件的电介质膜的平坦化在较低的流动温度下进行，因此令人满意地保持半导体器件的特性。在作为电介质膜的二氧化硅膜的情况下，网状结构由作为主要成分的硅原子和作为电介质膜的基体的副成分的氧原子构成。这些氧原子被诸如卤素原子包括氟的非桥连组分替代。在发生这种替换的位置上，这通过氧原子在硅原子之间断开桥。因此，电介质膜的粘度随流动温度而下降。例如，如果BPSG膜中的氧的一部分被氟取代，则允许电介质膜在850℃的较低温度下流动。可以抑制短的通道效应。

6. 发明授权

US5773639A Layer forming material and wiring forming method 失效
标题翻译：层形成材料和布线形成方法
公开(公告)号：US5773639A
公开(公告)日：1998-06-30
申请号：US618165
申请日：1996-03-19
申请人： Akemi Kawaguchi , Yuka Terai , Kousaku Yano
发明人： Akemi Kawaguchi , Yuka Terai , Kousaku Yano
IPC分类号： C23C16/18 , H01L21/3205 , H01L21/768 , H01L23/532 , C07F1/08 , C23C16/00
CPC分类号： H01L21/32051 , C23C16/18 , H01L21/76838 , H01L23/53238 , H01L2924/0002 , H01L2924/3011
摘要： A layer forming material is a compound which has a structure of six-membered ring coordinated to Cu and containing Si, and of which general formula is represented by the following chemical formula: ##STR1## wherein X.sub.1 and X.sub.2 are elements of the VI group of the same or different types which are coordinate-bonded to Cu, and of which examples include O, S, Se, Te and the like, at least one of Y.sub.1, Y.sub.2 and Y.sub.3 is Si, L is a group which has a double or triple bond and which is able to supply electrons to Cu, and each of R.sub.1 and R.sub.2 is any of SiF.sub.3, SiH.sub.3, CF.sub.3 and CH.sub.3 for example.
摘要翻译：成层材料是具有与Cu配位并含有Si的六元环结构的化合物，其通式由以下化学式表示：其中X1和X2是VI基团的元素与Cu配位结合的相同或不同的类型，其实例包括O，S，Se，Te等，Y1，Y2和Y3中的至少一个为Si，L为具有双或三键并且能够向Cu提供电子，并且R1和R2中的每一个例如是SiF 3，SiH 3，CF 3和CH 3中的任一种。

7. 发明授权

US5693557A Method of fabricating a semiconductor device 失效
公开(公告)号：US5693557A
公开(公告)日：1997-12-02
申请号：US590086
申请日：1996-01-24
申请人： Shuji Hirao , Hisashi Ogawa , Yuka Terai , Mitsuru Sekiguchi , Masanori Fukumoto , Isao Miyanaga
发明人： Shuji Hirao , Hisashi Ogawa , Yuka Terai , Mitsuru Sekiguchi , Masanori Fukumoto , Isao Miyanaga
IPC分类号： H01L21/02 , H01L21/3213 , H01L21/768 , H01L21/70
CPC分类号： H01L28/84 , H01L21/3213 , H01L21/32131 , H01L21/76838 , Y10S148/014 , Y10S438/964
摘要： A method of the invention for fabricating a semiconductor device includes the steps of: forming an oxide film having a non-uniform thickness on silicon; reducing at least a portion of the oxide film using gas containing a metal element, and growing a metal film containing the metal element on the silicon by reacting an exposed surface of the silicon with the gas; and removing the metal film.

8. 发明授权

US5314848A Method for manufacturing a semiconductor device using a heat treatment according to a temperature profile that prevents grain or particle precipitation during reflow 失效
标题翻译：根据温度分布的热处理制造半导体器件的方法，该温度分布防止在回流期间晶粒或颗粒沉淀
公开(公告)号：US5314848A
公开(公告)日：1994-05-24
申请号：US764846
申请日：1991-09-24
申请人： Takatoshi Yasui , Chiaki Kudo , Ichiro Nakao , Toyokazu Fujii , Yuka Terai , Shinichi Imai , Hiroshi Yamamoto , Yasushi Naito
发明人： Takatoshi Yasui , Chiaki Kudo , Ichiro Nakao , Toyokazu Fujii , Yuka Terai , Shinichi Imai , Hiroshi Yamamoto , Yasushi Naito
IPC分类号： H01L21/3105 , H01L21/768 , H01L21/00 , H01L21/02 , H01L21/324 , H01L21/477
CPC分类号： H01L21/76819 , H01L21/3105 , Y10S148/133 , Y10S438/909
摘要： Described is a method for manufacturing semiconductor devices which includes a heat treating process for heating and cooling semiconductor substrates mounted on a boat at a predetermined pitch according to a predetermined temperature profile, in order to flatten the surface of each semiconductor substrate by reflowing an insulating film containing impurities, for example, a BPSG film formed on the substrate. In the heat treating process, one of the control factors which affects the formation of grains or particles due to the impurities contained in the insulating film is set so as to prevent the impurities from generating grains or particles during the heat treatment. Also disclosed is a method of preventing the generation of grains or particles by widening the pitch of the mounted substrates.
摘要翻译：描述了一种用于制造半导体器件的方法，其包括根据预定温度分布以预定间距对安装在船上的半导体衬底进行加热和冷却的热处理工艺，以便通过回流绝缘膜来平坦化每个半导体衬底的表面含有杂质，例如在基板上形成的BPSG膜。在热处理过程中，设定影响绝缘膜中含有杂质的晶粒或颗粒形成的控制因素之一，以防止杂质在热处理过程中产生晶粒或颗粒。还公开了通过扩大安装的基板的间距来防止颗粒或颗粒的产生的方法。

9. 发明授权

US07171640B2 System and method for operation verification of semiconductor integrated circuit 有权
标题翻译：半导体集成电路运行验证的系统和方法
公开(公告)号：US07171640B2
公开(公告)日：2007-01-30
申请号：US11138499
申请日：2005-05-27
申请人： Yuka Terai , Kyoji Yamashita
发明人： Yuka Terai , Kyoji Yamashita
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/78 , G06F2217/84
摘要： A system for operation verification of a semiconductor integrated circuit has a central processing unit, a design layout memory unit storing design layout information including the design layout configuration of the semiconductor integrated circuit, and a predicted final layout memory storing a predicted final layout configuration predicted by the central processing unit by adding an optical proximity effect to the design layout configuration. The system further has a netlister which describes a procedure for causing the central processing unit to produce a plurality of net lists in which different physical values are registered for a common element in the predicted final layout configuration, a netlist memory unit the plurality of net lists, and a circuit simulator which describes a procedure for causing the central processing unit to perform operation verification of the semiconductor integrated circuit by using an arbitrary one of the plurality of net lists.
摘要翻译：一种用于半导体集成电路的操作验证的系统具有中央处理单元，存储包括半导体集成电路的设计布局配置的设计布局信息的设计布局存储单元，以及存储预测的最终布局布局的预测的最终布局存储器，中央处理单元通过向设计布局配置添加光学邻近效应。该系统还具有一个网络管理器，其描述了使中央处理单元产生多个网络列表的过程，其中在预测的最终布局配置中为公共元素登记不同的物理值，网表存储单元，多个网络列表以及电路模拟器，其描述使中央处理单元通过使用多个网络列表中的任意一个来执行半导体集成电路的操作验证的过程。

10. 发明申请

US20060010407A1 System and method for operation verification of semiconductor integrated circuit 有权
标题翻译：半导体集成电路运行验证的系统和方法
公开(公告)号：US20060010407A1
公开(公告)日：2006-01-12
申请号：US11138499
申请日：2005-05-27
申请人： Yuka Terai , Kyoji Yamashita
发明人： Yuka Terai , Kyoji Yamashita
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/78 , G06F2217/84
摘要： A system for operation verification of a semiconductor integrated circuit has a central processing unit, a design layout memory unit which stores therein design layout information including the design layout configuration of the semiconductor integrated circuit in which a plurality of semiconductor elements are integrated, and a predicted final layout memory unit which stores therein a predicted final layout configuration that has been predicted by the central processing unit by adding an optical proximity effect to the design layout configuration. The system further has a netlister which describes a procedure for causing the central processing unit to produce, as a net list described based on the predicted final layout configuration, a plurality of net lists in which different physical values are registered for a common element in the predicted final layout configuration, a netlist memory unit which stores therein the plurality of net lists, and a circuit simulator which describes a procedure for causing the central processing unit to perform operation verification of the semiconductor integrated circuit by using an arbitrary one of the plurality of net lists.
摘要翻译：一种用于半导体集成电路的操作验证的系统具有中央处理单元，设计布局存储单元，其存储包括集成了多个半导体元件的半导体集成电路的设计布局配置的设计布局信息，以及预测最终布局存储单元，其中存储由中央处理单元通过向设计布局配置添加光学邻近效应来预测的预测的最终布局配置。该系统进一步具有网络管理器，其描述使中央处理单元产生基于预测的最终布局配置描述的网络列表的多个网络列表的过程，其中不同的物理值被注册在公共元素中预测的最终布局配置，其中存储有多个网表的网表存储单元，以及描述使中央处理单元通过使用多个网列中的任意一个来执行半导体集成电路的操作验证的过程的电路模拟器净列表

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