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1. 发明授权

US07937633B2 Semiconductor device using logic chip 失效
标题翻译：半导体器件采用逻辑芯片
公开(公告)号：US07937633B2
公开(公告)日：2011-05-03
申请号：US12190196
申请日：2008-08-12
申请人： Kouji Takasugi , Noriaki Komatsu , Nobutoshi Tsunesada , Kazunori Yamane
发明人： Kouji Takasugi , Noriaki Komatsu , Nobutoshi Tsunesada , Kazunori Yamane
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C29/56012 , G11C2029/0401 , G11C2029/5602 , H01L2924/0002 , H01L2924/00
摘要： A system-in-package type semiconductor device includes a logic chip; and a memory chip connected with external terminal through the logic chip. The logic chip includes a data holding circuit configured to hold a test data in a test mode, and store the test data supplied through the data input/output terminal in the data holding circuit in response to a test data set command, and writes the test data which has been stored in the data holding circuit in the memory chip in response to the test data write command.
摘要翻译：系统级封装型半导体器件包括逻辑芯片; 以及通过逻辑芯片与外部端子连接的存储芯片。逻辑芯片包括：数据保持电路，被配置为将测试数据保存在测试模式中，并且响应于测试数据设置命令将通过数据输入/输出端子提供的测试数据存储在数据保持电路中，并且将测试响应于测试数据写入命令已经存储在存储器芯片中的数据保持电路中的数据。

2. 发明申请

US20090049349A1 SEMICONDUCTOR DEVICE USING LOGIC CHIP 失效
标题翻译：使用逻辑芯片的半导体器件
公开(公告)号：US20090049349A1
公开(公告)日：2009-02-19
申请号：US12190196
申请日：2008-08-12
申请人： Kouji TAKASUGI , Noriaki Komatsu , Nobutoshi Tsunesada , Kazunori Yamane
发明人： Kouji TAKASUGI , Noriaki Komatsu , Nobutoshi Tsunesada , Kazunori Yamane
IPC分类号： G11C29/00 , G06F11/00
CPC分类号： G11C29/48 , G11C29/56012 , G11C2029/0401 , G11C2029/5602 , H01L2924/0002 , H01L2924/00
摘要： A system-in-package type semiconductor device includes a logic chip; and a memory chip connected with external terminal through the logic chip. The logic chip includes a data holding circuit configured to hold a test data in a test mode, and store the test data supplied through the data input/output terminal in the data holding circuit in response to a test data set command, and writes the test data which has been stored in the data holding circuit in the memory chip in response to the test data write command.
摘要翻译：系统级封装型半导体器件包括逻辑芯片; 以及通过逻辑芯片与外部端子连接的存储芯片。逻辑芯片包括：数据保持电路，被配置为将测试数据保存在测试模式中，并且响应于测试数据设置命令将通过数据输入/输出端子提供的测试数据存储在数据保持电路中，并且将测试响应于测试数据写入命令已经存储在存储器芯片中的数据保持电路中的数据。

3. 发明授权

US08289041B2 Semiconductor integrated circuit device which has first chip and second chip accessed via the first chip and test method thereof 失效
标题翻译：具有通过第一芯片访问的第一芯片和第二芯片的半导体集成电路器件及其测试方法
公开(公告)号：US08289041B2
公开(公告)日：2012-10-16
申请号：US12314689
申请日：2008-12-15
申请人： Kazunori Yamane , Takayuki Kurokawa , Yuji Tada , Hironori Nakamura , Manabu Kitabatake
发明人： Kazunori Yamane , Takayuki Kurokawa , Yuji Tada , Hironori Nakamura , Manabu Kitabatake
IPC分类号： G01R31/3187
CPC分类号： G11C29/48 , G11C29/1201 , G11C2029/0401 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device includes a first chip including an internal circuit, and a second chip capable of being accessed only via the first chip, and a test processor circuit electrically connected internally via the first chip, for accessing the second chip from an external terminal and testing the second chip, and a test circuit where an input/output buffer is installed for signals for accessing the second chip within the test processor circuit, and a bypass line installed for transferring signals from the first chip to the second chip and avoiding the input/output buffer within the test processor circuit, and a switch which switches between signal transfer path via the input/output buffer, and a signal transfer path via the bypass line.
摘要翻译：半导体集成电路器件包括：第一芯片，其包括内部电路;以及第二芯片，其仅能够经由第一芯片访问;以及测试处理器电路，其经由第一芯片内部电连接，用于从外部端子访问第二芯片并且测试第二芯片，以及测试电路，其中安装了用于访问测试处理器电路内的第二芯片的信号的输入/输出缓冲器，以及安装用于将信号从第一芯片传送到第二芯片并且避免测试处理器电路内的输入/输出缓冲器，以及通过输入/输出缓冲器在信号传送路径和通过旁路线路的信号传送路径之间切换的开关。

4. 发明申请

US20110000029A1 BOARDING BRIDGE 有权
标题翻译：板桥
公开(公告)号：US20110000029A1
公开(公告)日：2011-01-06
申请号：US12865699
申请日：2009-01-21
申请人： Yasuaki Shimizu , Kenji Iwamoto , Akira Takarada , Kazunori Yamane
发明人： Yasuaki Shimizu , Kenji Iwamoto , Akira Takarada , Kazunori Yamane
IPC分类号： E01D15/00
CPC分类号： B64F1/3055
摘要： A boarding bridge is provided that has an inexpensive, trouble-free, and strong construction, that eliminates the level differences between the passage portions of adjacent passage sections, and can reduce the occurrence of passengers falling and the like. In the boarding bridge (1), a proximal end tunnel (7) and a distal end tunnel (9) are telescopically fit, and are extended and retracted by moving relative to each other in a longitudinal direction. At the passage portion of the distal end tunnel (9) are provided a passage member (33) having, at a passage portion of the distal end tunnel (9), one end thereof connected to the end portion of the stationary passage (29) of the proximal end tunnel (7), having a distal end passage portion (31) that has at least a predetermined length in a longitudinal direction, and having the other end thereof installed at the proximal end tunnel (7); sprockets (35) that are installed at the lower portion of the distal end tunnel of the distal end tunnel (9) such that the position thereof does not move, and that guide the passage member (33) in a vertical direction; a sheave (37) that is installed at the lower portion of the back end portion of the distal end tunnel (9) such that the position thereof does not move, and that guides the passage member (33) in a vertical direction; and a spring member (39) that applies a tension to the passage member (33).
摘要翻译：提供了一种具有便宜，无故障，结构坚固的登机桥，消除了相邻通道部分的通道部分之间的水平差异，并且可以减少乘客坠落等的发生。在登机桥（1）中，近端通道（7）和远端通道（9）可伸缩地配合，并且通过沿纵向方向相对于彼此移动而延伸和缩回。在远端通道（9）的通道部分设置有通道构件（33），其在远端通道（9）的通道部分处一端连接到固定通道（29）的端部，的近端通道（7），其具有在纵向方向上具有至少预定长度的远端通道部分（31），并且另一端安装在近端通道（7）处; 链轮（35），其安装在远端通道（9）的远端通道的下部，使得其位置不移动，并且在垂直方向上引导通道构件（33）; 安装在远端通道（9）的后端部的下部，使得其位置不移动并且沿着垂直方向引导通道构件（33）的滑轮（37）以及向通道构件（33）施加张力的弹簧构件（39）。

5. 发明申请

US20090167337A1 Semiconductor integrated circuit device which has first chip and second chip accessed via the first chip and test method thereof 失效
标题翻译：具有通过第一芯片访问的第一芯片和第二芯片的半导体集成电路器件及其测试方法
公开(公告)号：US20090167337A1
公开(公告)日：2009-07-02
申请号：US12314689
申请日：2008-12-15
申请人： Kazunori Yamane , Takayuki Kurokawa , Yuji Tada , Hironori Nakamura , Manabu Kitabatake
发明人： Kazunori Yamane , Takayuki Kurokawa , Yuji Tada , Hironori Nakamura , Manabu Kitabatake
IPC分类号： G01R31/303
CPC分类号： G11C29/48 , G11C29/1201 , G11C2029/0401 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device includes a first chip including an internal circuit, and a second chip capable of being accessed only via the first chip, and a test processor circuit electrically connected internally via the first chip, for accessing the second chip from an external terminal and testing the second chip, and a test circuit where an input/output buffer is installed for signals for accessing the second chip within the test processor circuit, and a bypass line installed for transferring signals from the first chip to the second chip and avoiding the input/output buffer within the test processor circuit, and a switch which switches between signal transfer path via the input/output buffer, and a signal transfer path via the bypass line.
摘要翻译：半导体集成电路器件包括：第一芯片，其包括内部电路;以及第二芯片，其仅能够经由第一芯片访问;以及测试处理器电路，其经由第一芯片内部电连接，用于从外部端子访问第二芯片并且测试第二芯片，以及测试电路，其中安装了用于访问测试处理器电路内的第二芯片的信号的输入/输出缓冲器，以及安装用于将信号从第一芯片传送到第二芯片并且避免测试处理器电路内的输入/输出缓冲器，以及通过输入/输出缓冲器在信号传送路径和通过旁路线路的信号传送路径之间切换的开关。

6. 发明授权

US08302237B2 Boarding bridge 有权
标题翻译：登机桥
公开(公告)号：US08302237B2
公开(公告)日：2012-11-06
申请号：US12865699
申请日：2009-01-21
申请人： Yasuaki Shimizu , Kenji Iwamoto , Akira Takarada , Kazunori Yamane
发明人： Yasuaki Shimizu , Kenji Iwamoto , Akira Takarada , Kazunori Yamane
IPC分类号： E01D15/00
CPC分类号： B64F1/3055
摘要： A boarding bridge is provided that has an inexpensive, trouble-free, and strong construction, that eliminates the level differences between the passage portions of adjacent passage sections, and can reduce the occurrence of passengers falling and the like. In the boarding bridge (1), a proximal end tunnel (7) and a distal end tunnel (9) are telescopically fit, and are extended and retracted by moving relative to each other in a longitudinal direction. At the passage portion of the distal end tunnel (9) are provided a passage member (33) having, at a passage portion of the distal end tunnel (9), one end thereof connected to the end portion of the stationary passage (29) of the proximal end tunnel (7), having a distal end passage portion (31) that has at least a predetermined length in a longitudinal direction, and having the other end thereof installed at the proximal end tunnel (7); sprockets (35) that are installed at the lower portion of the distal end tunnel of the distal end tunnel (9) such that the position thereof does not move, and that guide the passage member (33) in a vertical direction; a sheave (37) that is installed at the lower portion of the back end portion of the distal end tunnel (9) such that the position thereof does not move, and that guides the passage member (33) in a vertical direction; and a spring member (39) that applies a tension to the passage member (33).
摘要翻译：提供了一种具有便宜，无故障，结构坚固的登机桥，消除了相邻通道部分的通道部分之间的水平差异，并且可以减少乘客坠落等的发生。在登机桥（1）中，近端通道（7）和远端通道（9）可伸缩地配合，并且通过沿纵向方向相对于彼此移动而延伸和缩回。在远端通道（9）的通道部分设置有通道构件（33），其在远端通道（9）的通道部分处一端连接到固定通道（29）的端部，的近端通道（7），其具有在纵向方向上具有至少预定长度的远端通道部分（31），并且另一端安装在近端通道（7）处; 链轮（35），其安装在远端通道（9）的远端通道的下部，使得其位置不移动，并且在垂直方向上引导通道构件（33）; 安装在远端通道（9）的后端部的下部，使得其位置不移动并且沿着垂直方向引导通道构件（33）的滑轮（37）以及向通道构件（33）施加张力的弹簧构件（39）。

7. 发明授权

US07446594B2 Booster circuit including an oscillator 失效
标题翻译：升压电路包括一个振荡器
公开(公告)号：US07446594B2
公开(公告)日：2008-11-04
申请号：US11496398
申请日：2006-08-01
申请人： Kazunori Yamane , Akira Satou , Toshiharu Okamoto
发明人： Kazunori Yamane , Akira Satou , Toshiharu Okamoto
IPC分类号： G05F3/02 , G05F1/10
CPC分类号： G11C16/30 , G11C5/145 , G11C16/12 , H02M3/073 , H02M2001/0041
摘要： Disclosed is a booster circuit comprising a voltage detection circuit for outputting a decision output signal for detecting a boosted voltage and controlling a voltage boosting operation, an oscillation circuit, and a plurality of charge pump circuits. The oscillation circuit includes an odd number of stages of control-type inverters. When the decision output signal from the voltage detection circuit indicates the voltage boosting operation (oscillation), the odd number of stages of inverters constitute a closed path. Oscillation outputs from outputs of the control-type inverters are thereby extracted, respectively. When the decision output signal indicates a stop of the voltage boosting operation (stop of the oscillation), output values of the control-type inverters are not inverted and held, and the oscillation is thereby stopped. The charge pump circuits receive output signals from the control-type inverters as clock signals, respectively, and operate.
摘要翻译：公开了一种升压电路，其包括用于输出用于检测升压电压的判定输出信号和控制升压操作的电压检测电路，振荡电路和多个电荷泵电路。振荡电路包括奇数级的控制型逆变器。当来自电压检测电路的判定输出信号表示升压操作（振荡）时，奇数级的反相器构成闭合通路。因此，分别提取控制型逆变器的输出的振荡输出。当判定输出信号表示停止升压动作（停止振荡）时，控制型逆变器的输出值不反转并保持，从而停止振荡。电荷泵电路分别接收来自控制型逆变器的输出信号作为时钟信号并进行操作。

8. 发明申请

US20070030082A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20070030082A1
公开(公告)日：2007-02-08
申请号：US11496398
申请日：2006-08-01
申请人： Kazunori Yamane , Akira Satou , Toshiharu Okamoto
发明人： Kazunori Yamane , Akira Satou , Toshiharu Okamoto
IPC分类号： H03K3/03
CPC分类号： G11C16/30 , G11C5/145 , G11C16/12 , H02M3/073 , H02M2001/0041
摘要： Disclosed is a booster circuit comprising a voltage detection circuit for outputting a decision output signal for detecting a boosted voltage and controlling a voltage boosting operation, an oscillation circuit, and a plurality of charge pump circuits. The oscillation circuit includes an odd number of stages of control-type inverters. When the decision output signal from the voltage detection circuit indicates the voltage boosting operation (oscillation), the odd number of stages of inverters constitute a closed path. Oscillation outputs from outputs of the control-type inverters are thereby extracted, respectively. When the decision output signal indicates a stop of the voltage boosting operation (stop of the oscillation), output values of the control-type inverters are not inverted and held, and the oscillation is thereby stopped. The charge pump circuits receive output signals from the control-type inverters as clock signals, respectively, and operate.
摘要翻译：公开了一种升压电路，其包括用于输出用于检测升压电压的判定输出信号和控制升压操作的电压检测电路，振荡电路和多个电荷泵电路。振荡电路包括奇数级的控制型逆变器。当来自电压检测电路的判定输出信号表示升压操作（振荡）时，奇数级的反相器构成闭合通路。因此，分别提取控制型逆变器的输出的振荡输出。当判定输出信号表示停止升压动作（停止振荡）时，控制型逆变器的输出值不被反转并保持，从而停止振荡。电荷泵电路分别接收来自控制型逆变器的输出信号作为时钟信号并进行操作。

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