专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07046566B1 Voltage-based timing control of memory bit lines 有权
标题翻译：存储位线的基于电压的定时控制
公开(公告)号：US07046566B1
公开(公告)日：2006-05-16
申请号：US11005996
申请日：2004-12-06
申请人： Kok Heng Choe , Edwin Yew Fatt Kok , Kar Keng Chua
发明人： Kok Heng Choe , Edwin Yew Fatt Kok , Kar Keng Chua
IPC分类号： G11C7/00
CPC分类号： G11C7/04 , G11C7/12 , G11C7/22 , G11C2207/2254
摘要： Circuitry and methods are provided for controlling memory operation by comparing bit line voltages to preset reference voltages. By relying on bit line voltage levels to determine when to start and end each stage of a read or write operation, reliance on precisely tuned delay chains is removed. Parasitic effects are automatically accounted for, as well as process, voltage, and temperature variations. This precise matching of operation timing to memory bit line conditions results in improved system performance.
摘要翻译：电路和方法用于通过将位线电压与预设参考电压进行比较来控制存储器操作。通过依靠位线电压电平来确定何时开始和结束读取或写入操作的每个阶段，消除对精确调谐的延迟链的依赖。自动考虑寄生效应，以及过程，电压和温度变化。操作时序与存储器位线条件的精确匹配导致系统性能的提高。

2. 发明授权

US08261141B1 Real time feedback compensation of programmable logic memory 有权
标题翻译：可编程逻辑存储器的实时反馈补偿
公开(公告)号：US08261141B1
公开(公告)日：2012-09-04
申请号：US13004133
申请日：2011-01-11
申请人： Kok Heng Choe , Edwin Yew Fatt Kok , Kar Keng Chua
发明人： Kok Heng Choe , Edwin Yew Fatt Kok , Kar Keng Chua
IPC分类号： G11C29/00
CPC分类号： H03K5/13 , H03K19/173 , H03K2005/0013 , H03K2005/00143
摘要： Memory performance in programmable logic is significantly increased by adjusting circuitry operation to adjust for variations in process, voltage, or temperature. A calibration circuit adjusts control signal timing, dynamically and automatically, to compensate real time to process, voltage, and temperature variation. A feedback system using a control block and a dummy mimicking concept are provided.
摘要翻译：通过调整电路操作来调整过程，电压或温度的变化，可编程逻辑中的存储器性能显着增加。校准电路动态和自动地调节控制信号时序，以补偿实时处理，电压和温度变化。提供了使用控制块和虚拟模拟概念的反馈系统。

3. 发明授权

US07071731B1 Programmable Logic with Pipelined Memory Operation 失效
标题翻译：可编程逻辑与流水线存储器操作
公开(公告)号：US07071731B1
公开(公告)日：2006-07-04
申请号：US10905831
申请日：2005-01-21
申请人： Kok Heng Choe , Edwin Yew Fatt Kok , Kar Keng Chua
发明人： Kok Heng Choe , Edwin Yew Fatt Kok , Kar Keng Chua
IPC分类号： G06F7/38 , G11C7/10
CPC分类号： G11C7/1039
摘要： Memory performance of an integrated circuit, such as a programmable logic integrated circuit, is increased by pipelining. In a single clock cycle, more than one operation may be performed on the memory, which improves bandwidth. In an implementation, the memory architecture having one port supports pipelining, so reading from and writing to the memory can be accomplished in a one clock cycle and both Read and Write operation can occupy the full clock cycle at the same time on the same port. The pipelining architecture has relatively minimal circuit changes compared to a standard memory architecture which not supporting simultaneous-clock-cycle reads and writes, without requiring two or more ports.
摘要翻译：诸如可编程逻辑集成电路的集成电路的存储器性能通过流水线增加。在单个时钟周期中，可以对存储器执行多于一个操作，这提高了带宽。在一个实现中，具有一个端口的存储器架构支持流水线，因此可以在一个时钟周期内完成对存储器的读取和写入，并且读取和写入操作可以在同一个端口上同时占用整个时钟周期。与不需要两个或更多个端口的不支持同步时钟周期读取和写入的标准存储器架构相比，流水线架构具有相对较小的电路变化。

4. 发明授权

US07882408B1 Real time feedback compensation of programmable logic memory 有权
标题翻译：可编程逻辑存储器的实时反馈补偿
公开(公告)号：US07882408B1
公开(公告)日：2011-02-01
申请号：US11546743
申请日：2006-10-11
申请人： Kok Heng Choe , Edwin Yew Fatt Kok , Kar Keng Chua
发明人： Kok Heng Choe , Edwin Yew Fatt Kok , Kar Keng Chua
IPC分类号： G11C29/00 , G11B5/00 , G06F11/00
CPC分类号： H03K5/13 , H03K19/173 , H03K2005/0013 , H03K2005/00143
摘要： Memory performance in programmable logic is significantly increased by adjusting a timing of control signals sent to a memory to compensate for variations in process, voltage, or temperature. A calibration circuit can adjust the control signal timing, dynamically and automatically, to provide accurate and high performance memory operations. For example, timing settings for the control signals can be determined such that data written/read from the memory are accurate. The timing setting can also be changed to provide faster memory operations while still providing accuracy. A feedback system using a control block and a dummy mimicking concept are also provided.
摘要翻译：通过调整发送到存储器的控制信号的时序来补偿过程，电压或温度的变化，可编程逻辑中的存储器性能显着增加。校准电路可以动态和自动地调整控制信号时序，以提供精确和高性能的存储器操作。例如，可以确定控制信号的定时设置，使得从存储器写入/读取的数据是准确的。时序设置也可以改变，以提供更快的存储器操作，同时仍然提供准确性。还提供了使用控制块和虚拟模拟概念的反馈系统。

5. 发明授权

US07164289B1 Real time feedback compensation of programmable logic memory 有权
标题翻译：可编程逻辑存储器的实时反馈补偿
公开(公告)号：US07164289B1
公开(公告)日：2007-01-16
申请号：US10905830
申请日：2005-01-21
申请人： Kok Heng Choe , Edwin Yew Fatt Kok , Kar Keng Chua
发明人： Kok Heng Choe , Edwin Yew Fatt Kok , Kar Keng Chua
IPC分类号： G06F7/38
CPC分类号： H03K5/13 , H03K19/173 , H03K2005/0013 , H03K2005/00143
摘要： Memory performance in programmable logic is significantly increased by adjusting circuitry operation to adjust for variations in process, voltage, or temperature. A calibration circuit adjusts control signal timing, dynamically and automatically, to compensate real time to process, voltage, and temperature variation. A feedback system using a control block and a dummy mimicking concept are provided.
摘要翻译：通过调整电路操作来调整过程，电压或温度的变化，可编程逻辑中的存储器性能显着增加。校准电路动态和自动地调节控制信号时序，以补偿实时处理，电压和温度变化。提供了使用控制块和虚拟模拟概念的反馈系统。

6. 发明授权

US08253448B1 Techniques for varying frequencies of periodic signals 有权
标题翻译：周期信号频率变化的技术
公开(公告)号：US08253448B1
公开(公告)日：2012-08-28
申请号：US12839096
申请日：2010-07-19
申请人： Chuan Thim Khor , Chuan Khye Chai , Edwin Yew Fatt Kok
发明人： Chuan Thim Khor , Chuan Khye Chai , Edwin Yew Fatt Kok
IPC分类号： H03B19/00
CPC分类号： H03K5/00006
摘要： A circuit includes first and second frequency divider circuits and first storage circuits. Each of the first and the second frequency divider circuits receives periodic input signals and generates a periodic output signal having a frequency of one of the periodic input signals in a bypass mode. The periodic output signal of each of the first and the second frequency divider circuits has a fraction of a frequency of one of the periodic input signals in a frequency divider mode. Each of the first storage circuits stores an enable signal in response to the periodic output signal of one of the first frequency divider circuits. The enable signals stored in the first storage circuits enable the second frequency divider circuits in the frequency divider mode. The circuit may include second storage circuits storing enable signals that enable a subset of the first frequency divider circuits in the frequency divider mode.
摘要翻译：电路包括第一和第二分频器电路和第一存储电路。第一和第二分频器电路中的每一个接收周期性输入信号，并以旁路模式产生具有周期性输入信号之一的频率的周期性输出信号。第一和第二分频器电路中的每一个的周期性输出信号具有分频器模式中的一个周期性输入信号的频率的一部分。每个第一存储电路响应于第一分频器电路之一的周期性输出信号而存储使能信号。存储在第一存储电路中的使能信号使能分频器模式中的第二分频器电路。该电路可以包括存储启用信号的第二存储电路，其使能分频器模式中的第一分频器电路的子集。

7. 发明申请

US20110285434A1 HETEROGENEOUS PHYSICAL MEDIA ATTACHMENT CIRCUITRY FOR INTEGRATED CIRCUIT DEVICES 有权
标题翻译：用于集成电路设备的异质物理介质连接电路
公开(公告)号：US20110285434A1
公开(公告)日：2011-11-24
申请号：US12785047
申请日：2010-05-21
申请人： Sergey Shumarayev , Edwin Yew Fatt Kok , Lip Kai Soh , Chee Hong Aw , Tee Wee Tan
发明人： Sergey Shumarayev , Edwin Yew Fatt Kok , Lip Kai Soh , Chee Hong Aw , Tee Wee Tan
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , H03K19/1774 , H03K19/17744 , H03L7/0891 , H03L7/095
摘要： An integrated circuit includes physical media attachment (“PMA”) circuitry that includes two different kinds of transceiver channels for serial data signals. One kind of transceiver channel is adapted for transceiving relatively low-speed serial data signals. The other kind of transceiver channel is adapted for transceiving relatively high-speed serial data signals. A high-speed channel is alternatively usable as phase-locked loop (“PLL”) circuitry for providing a clock signal for use by other high- and/or low-speed channels. A low-speed channel can alternatively get a clock signal from separate low-speed PLL circuitry.
摘要翻译：集成电路包括物理介质连接（“PMA”）电路，其包括用于串行数据信号的两种不同类型的收发信道。一种收发信道用于收发相对低速的串行数据信号。另一种收发器通道适用于收发相对高速的串行数据信号。高速通道可用作锁相环（“PLL”）电路，用于提供其它高速和/或低速通道使用的时钟信号。低速通道也可以从单独的低速PLL电路获取时钟信号。

8. 发明授权

US08397096B2 Heterogeneous physical media attachment circuitry for integrated circuit devices 有权
标题翻译：用于集成电路器件的异质物理介质连接电路
公开(公告)号：US08397096B2
公开(公告)日：2013-03-12
申请号：US12785047
申请日：2010-05-21
申请人： Sergey Shumarayev , Edwin Yew Fatt Kok , Lip Kai Soh , Chee Hong Aw , Tee Wee Tan
发明人： Sergey Shumarayev , Edwin Yew Fatt Kok , Lip Kai Soh , Chee Hong Aw , Tee Wee Tan
IPC分类号： G06F1/00 , G06F1/04 , G06F13/14
CPC分类号： H03L7/0805 , H03K19/1774 , H03K19/17744 , H03L7/0891 , H03L7/095
摘要： An integrated circuit includes physical media attachment (“PMA”) circuitry that includes two different kinds of transceiver channels for serial data signals. One kind of transceiver channel is adapted for transceiving relatively low-speed serial data signals. The other kind of transceiver channel is adapted for transceiving relatively high-speed serial data signals. A high-speed channel is alternatively usable as phase-locked loop (“PLL”) circuitry for providing a clock signal for use by other high- and/or low-speed channels. A low-speed channel can alternatively get a clock signal from separate low-speed PLL circuitry.
摘要翻译：集成电路包括物理介质连接（PMA）电路，其包括用于串行数据信号的两种不同类型的收发信道。一种收发信道用于收发相对低速的串行数据信号。另一种收发器通道适用于收发相对高速的串行数据信号。高速通道可用作锁相环（PLL）电路，用于提供时钟信号以供其他高速和/或低速通道使用。低速通道也可以从单独的低速PLL电路获取时钟信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式