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    • 3. 发明授权
    • Image display method and image display device
    • 图像显示方法和图像显示装置
    • US07126572B2
    • 2006-10-24
    • US10396329
    • 2003-03-26
    • Koichi KogaNoboru OkuzonoMachihiko Yamaguchi
    • Koichi KogaNoboru OkuzonoMachihiko Yamaguchi
    • G09G3/36G09G5/10
    • G09G3/2025G09G3/2003G09G3/2077G09G3/2092G09G3/3648G09G5/02G09G2320/0233G09G2320/0247
    • A display panel 13 having a plurality of pixels 14 each divided into P (P=3) sub-pixels 15a, 15b and 15c, and a source driver 12 for driving each pixel 14 in accordance with three J (=8)-bit data values corresponding to the sub-pixels 15a, 15b, and 15c, and a signal processing circuit 12 for distributing K(=12)-bit (K>J) input image data as M (M=6) time-shared frame data values and supplying the frame data values to the source driver 12 are arranged. 2K−J (=16) gray levels insufficient due to the difference between the numbers of bits of K-bit input image data and J-bit driving signals of the source driver 12 is realized by combinations of time-shared frame data of (P×M=18) ways performed for the sub-pixels 15a, 15b, and 15c in accordance with the M time-shared frame data values.
    • 具有分成P(P = 3)个子像素15a,15b和15c的多个像素14的显示面板13以及根据三个J(= 8)驱动每个像素14的源极驱动器12, 对应于子像素15 a,15 b和15 c的位数据值,以及用于将K(= 12)位(K> J)输入图像数据分配为M(M = 6)的信号处理电路12, 布置了时间共享帧数据值并将帧数据值提供给源驱动器12。 由于K位输入图像数据的位数和源极驱动器12的J位驱动信号之间的差异,由于时间 - 频率的组合实现了2kHz(= 16)的灰度级, 根据M个时间共享帧数据值对子像素15 a,15 b和15 c执行的(PxM = 18)方式的共享帧数据。
    • 4. 发明授权
    • Liquid crystal display control circuit
    • 液晶显示控制电路
    • US06894673B2
    • 2005-05-17
    • US10192101
    • 2002-07-10
    • Koichi KogaNoboru OkuzonoMachihiko Yamaguchi
    • Koichi KogaNoboru OkuzonoMachihiko Yamaguchi
    • G02F1/133G09G3/20G09G3/36H04N5/66
    • G09G3/3611G09G3/3677
    • A liquid crystal display control circuit receives a data enable signal DE in synchronization with per-line based display data from a computer, and thereby controls a liquid crystal display. A gate drive signal outputted from a gate driver 23 is generated according to a vertical clock signal VCK in synchronization with a rise of the signal DE. In order to avoid a variation in the period of charging the pixel electrodes which is caused by a delay in the rise timing of the signal DE and a delay in the signal VCK after the last line, a gate enable signal generation circuit 10 is provided in the liquid crystal display control circuit 1, whereby the extended output of the pulse of the gate drive signal caused by the above-mentioned delays is inhibited. This avoids display inhomogeneity caused by a variation in the data enable signal and the like.
    • 液晶显示控制电路与来自计算机的基于行的显示数据同步地接收数据使能信号DE,从而控制液晶显示器。 与信号DE的上升同步地,根据垂直时钟信号VCK产生从栅极驱动器23输出的栅极驱动信号。 为了避免由于信号DE的上升时间的延迟和最后一行之后的信号VCK中的延迟引起的像素电极的充电周期的变化,栅极使能信号生成电路10被设置在 液晶显示控制电路1,由此抑制由上述延迟引起的栅极驱动信号的脉冲的扩展输出。 这避免了由数据使能信号等的变化引起的显示不均匀性。
    • 5. 发明授权
    • Liquid crystal display
    • 液晶显示器
    • US06727878B2
    • 2004-04-27
    • US09772864
    • 2001-01-31
    • Noboru OkuzonoKoichi Koga
    • Noboru OkuzonoKoichi Koga
    • G09G336
    • G09G3/3614G09G3/3648G09G2320/0204G09G2320/0223
    • A liquid crystal display is provided which has low power consumption, and which prevents horizontal stripes from occurring without the circuitry becoming more complex. When the write voltage polarity is inverted every plurality of lines, in the n line where the polarity is inverted, the rise in the drain line waveform dulls due to the charging of the drain line. In the n+1 line, because the drain line has been charged by the writing of the n line, waveform dullness does not occur. A difference between the write states in the two lines causes horizontal stripes. Consequently, the output enable signal is activated at the rise of the clock signal, and the gate line is activated after a predetermined time to start the writing. Therefore, writing is not performed during the period of waveform dullness, and the write state is the same across all scan lines.
    • 提供了具有低功耗的液晶显示器,并且防止水平条纹发生,而电路变得更加复杂。 当写入电压极性每多行反转时,在极性反转的n行中,由于漏极线的充电,漏极线波形的上升变钝。 在n + 1行中,由于通过n行的写入对漏极线进行了充电,因此不会发生波形钝化。 两行之间写入状态之间的差异会导致水平条纹。 因此,在时钟信号的上升时,输出使能信号被激活,并且在开始写入的预定时间之后激活栅极线。 因此,在波形迟钝期间不进行写入,写入状态在所有扫描线上相同。
    • 7. 发明授权
    • Liquid crystal display
    • 液晶显示器
    • US06911967B2
    • 2005-06-28
    • US10762501
    • 2004-01-23
    • Noboru OkuzonoKoichi Koga
    • Noboru OkuzonoKoichi Koga
    • G02F1/133G09G3/20G09G3/36
    • G09G3/3614G09G3/3648G09G2320/0204G09G2320/0223
    • A liquid crystal display is provided which has low power consumption, and which prevents horizontal stripes from occurring without the circuitry becoming more complex. When the write voltage polarity is inverted every plurality of lines, in the n line where the polarity is inverted, the rise in the drain line waveform dulls due to the charging of the drain line. In the n+1 line, because the drain line has been charged by the writing of the n line, waveform dullness does not occur. A difference between the write states in the two lines causes horizontal stripes. Consequently, the output enable signal is activated at the rise of the clock signal, and the gate line is activated after a predetermined time to start the writing. Therefore, writing is not performed during the period of waveform dullness, and the write state is the same across all scan lines.
    • 提供了具有低功耗的液晶显示器,并且防止水平条纹发生,而电路变得更加复杂。 当写入电压极性每多行反转时,在极性反转的n行中,由于漏极线的充电,漏极线波形的上升变钝。 在n + 1行中,由于通过n行的写入对漏极线进行了充电,因此不会发生波形钝化。 两行之间写入状态之间的差异会导致水平条纹。 因此,在时钟信号的上升时,输出使能信号被激活,并且在开始写入的预定时间之后激活栅极线。 因此,在波形迟钝期间不进行写入,写入状态在所有扫描线上相同。
    • 8. 发明授权
    • Liquid crystal display
    • 液晶显示器
    • US06982693B2
    • 2006-01-03
    • US10762502
    • 2004-01-23
    • Noboru OkuzonoKoichi Koga
    • Noboru OkuzonoKoichi Koga
    • G09G3/36
    • G09G3/3614G09G3/3648G09G2320/0204G09G2320/0223
    • A liquid crystal display is provided which has low power consumption, and which prevents horizontal stripes from occurring without the circuitry becoming more complex. When the write voltage polarity is inverted every plurality of lines, in the n line where the polarity is inverted, the rise in the drain line waveform dulls due to the charging of the drain line. In the n+1 line, because the drain line has been charged by the writing of the n line, waveform dullness does not occur. A difference between the write states in the two lines causes horizontal stripes. Consequently, the output enable signal is activated at the rise of the clock signal, and the gate line is activated after a predetermined time to start the writing. Therefore, writing is not performed during the period of waveform dullness, and the write state is the same across all scan lines.
    • 提供了具有低功耗的液晶显示器,并且防止水平条纹发生,而电路变得更加复杂。 当写入电压极性每多行反转时,在极性反转的n行中,由于漏极线的充电,漏极线波形的上升变钝。 在n + 1行中,由于通过n行的写入对漏极线进行了充电,因此不会发生波形钝化。 两行之间写入状态之间的差异会导致水平条纹。 因此,在时钟信号的上升时,输出使能信号被激活,并且在开始写入的预定时间之后激活栅极线。 因此,在波形迟钝期间不进行写入,写入状态在所有扫描线上相同。