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1. 发明授权

US08218373B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
标题翻译：半导体集成电路适用于输出内部操作的通过/失败结果
公开(公告)号：US08218373B2
公开(公告)日：2012-07-10
申请号：US12981063
申请日：2010-12-29
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C7/10
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
摘要翻译：在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否或者不是第二操作是可执行的。

2. 发明申请

US20090080264A1 SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULTS OF INTERNAL OPERATIONS 有权
标题翻译：半导体集成电路适用于输出通过/内部运行失败的结果
公开(公告)号：US20090080264A1
公开(公告)日：2009-03-26
申请号：US12252896
申请日：2008-10-16
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C16/06 , G11C7/10 , G11C7/00
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
摘要翻译：在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否或者不是第二操作是可执行的。

3. 发明授权

US07023741B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
公开(公告)号：US07023741B2
公开(公告)日：2006-04-04
申请号：US10318167
申请日：2002-12-13
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C7/00
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

4. 发明授权

US06977846B2 Non-volatile semiconductor memory device in which one page is set for a plurality of memory cell arrays 有权
公开(公告)号：US06977846B2
公开(公告)日：2005-12-20
申请号：US11046987
申请日：2005-01-31
申请人： Koichi Kawai , Kenichi Imamiya , Hiroshi Nakamura , Koji Hosono
发明人： Koichi Kawai , Kenichi Imamiya , Hiroshi Nakamura , Koji Hosono
IPC分类号： G11C16/02 , G11C16/00 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/34
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/08 , G11C16/3454
摘要： A plurality of memory cell arrays are provided. Each of the memory cell arrays has a plurality of memory cells and the memory cells are connected to a plurality of word lines. Corresponding with the plurality of memory cell arrays, a plurality of word line drive circuits and a plurality of bit line control circuits are provided. Each of the word line drive circuits selects and drives the word lines of the corresponding memory cell array. Each of the bit control circuits carries out verifying reading for the data written in advance in the plurality of memory cells of the corresponding memory cell array, and controls a select and driving operation for the word lines of the corresponding word line drive circuit based on a result of the verifying reading.

5. 发明授权

US06907497B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06907497B2
公开(公告)日：2005-06-14
申请号：US10325714
申请日：2002-12-20
申请人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura , Mikito Nakabayashi , Koichi Kawai
发明人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura , Mikito Nakabayashi , Koichi Kawai
IPC分类号： G11C16/34 , G06F12/00
CPC分类号： G11C16/3463 , G11C16/3454 , G11C16/3459
摘要： A non-volatile semiconductor memory device includes a memory cell array, a data hold circuit, and a controller A program control function applies a program voltage to a selected memory cell to let data shift from a first logic state to a second logic state. A program verify control function verifies that a programmed data of the selected memory cell shifted to the second logic state. An erratic program verify control function checks that a threshold voltage of a memory cell to be held in the first logic state does not exceed a third value set as an upper limit value of a variation of the first logic state. An over-program verify control function checks that a threshold voltage of the selected memory cell shifted to the second logic state does not exceed a fourth value set as an upper limit thereof.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，数据保持电路和控制器。程序控制功能将程序电压施加到所选择的存储器单元，以使数据从第一逻辑状态转换到第二逻辑状态。程序验证控制功能验证所选择的存储器单元的编程数据移动到第二逻辑状态。不稳定的程序验证控制功能检查要保持在第一逻辑状态的存储单元的阈值电压不超过设置为第一逻辑状态的变化的上限值的第三值。过程程序验证控制功能检查所选择的存储单元的阈值电压移动到第二逻辑状态不超过设定为其上限的第四值。

6. 发明授权

US08477541B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
公开(公告)号：US08477541B2
公开(公告)日：2013-07-02
申请号：US13489977
申请日：2012-06-06
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C7/10
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

7. 发明授权

US07916555B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
标题翻译：半导体集成电路适用于输出内部操作的通过/失败结果
公开(公告)号：US07916555B2
公开(公告)日：2011-03-29
申请号：US12252896
申请日：2008-10-16
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C7/10
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
摘要翻译：在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否或者不是第二操作是可执行的。

8. 发明授权

US07123515B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
公开(公告)号：US07123515B2
公开(公告)日：2006-10-17
申请号：US11119744
申请日：2005-05-03
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C11/34
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

9. 发明授权

US07117296B2 Method of programming non-volatile semiconductor memory device having an electrically erasable and programmable memory cell array 失效
标题翻译：编程具有电可擦除可编程存储单元阵列的非易失性半导体存储器件的方法
公开(公告)号：US07117296B2
公开(公告)日：2006-10-03
申请号：US11117669
申请日：2005-04-28
申请人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura , Mikito Nakabayashi , Koichi Kawai
发明人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura , Mikito Nakabayashi , Koichi Kawai
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G11C16/3463 , G11C16/3454 , G11C16/3459
摘要： A non-volatile semiconductor memory device includes a memory cell array in which electrically erasable and programmable memory cells are arrayed, each of the memory cells storing therein a first logic state with a threshold voltage lower than or equal to a first value or a second logic state with a threshold voltage higher than or equal to a second value that is higher than the first value, a data hold circuit for holding program data and sensing data as read out of the memory cell array, and a controller configured to control a program sequence, wherein the controller has the control functions of: a program control function for applying a program voltage to a selected memory cell of the memory cell array to let the data shift from the first logic state to the second logic state; a program verify control function for verifying that the programmed data of the selected memory cell shifted to the second logic state; an erratic program verify control function for checking that the threshold voltage of a memory cell to be held in the first logic state does not exceed a third value set as an upper limit value of a variation of the first logic state; and an over-program verify control function for checking that the threshold voltage of the selected memory cell shifted to the second logic state does not exceed a fourth value set as an upper limit thereof.
摘要翻译：一种非易失性半导体存储器件包括存储单元阵列，其中电可擦除可编程存储单元被排列，每个存储单元存储第一逻辑状态，阈值电压低于或等于第一值或第二逻辑具有高于或等于高于第一值的第二值的阈值电压的状态，用于保存从存储单元阵列读出的程序数据和感测数据的数据保持电路，以及控制器，其被配置为控制程序序列其中所述控制器具有以下控制功能：用于将程序电压施加到所述存储单元阵列的选定存储单元以使数据从第一逻辑状态移位到第二逻辑状态的程序控制功能; 程序验证控制功能，用于验证所选择的存储单元的编程数据移动到第二逻辑状态; 用于检查要保持在第一逻辑状态的存储单元的阈值电压不超过设置为第一逻辑状态的变化的上限值的第三值的不规则程序验证控制功能; 以及用于检查移动到第二逻辑状态的选择的存储单元的阈值电压不超过设定为其上限的第四值的过程序验证控制功能。

10. 发明申请

US20050185468A1 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050185468A1
公开(公告)日：2005-08-25
申请号：US11117669
申请日：2005-04-28
申请人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura , Mikito Nakabayashi , Koichi Kawai
发明人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura , Mikito Nakabayashi , Koichi Kawai
IPC分类号： G11C16/34 , G11C11/34
CPC分类号： G11C16/3463 , G11C16/3454 , G11C16/3459
摘要： A non-volatile semiconductor memory device includes a memory cell array in which electrically erasable and programmable memory cells are arrayed, each of the memory cells storing therein a first logic state with a threshold voltage lower than or equal to a first value or a second logic state with a threshold voltage higher than or equal to a second value that is higher than the first value, a data hold circuit for holding program data and sensing data as read out of the memory cell array, and a controller configured to control a program sequence, wherein the controller has the control functions of: a program control function for applying a program voltage to a selected memory cell of the memory cell array to let the data shift from the first logic state to the second logic state; a program verify control function for verifying that the programmed data of the selected memory cell shifted to the second logic state; an erratic program verify control function for checking that the threshold voltage of a memory cell to be held in the first logic state does not exceed a third value set as an upper limit value of a variation of the first logic state; and an over-program verify control function for checking that the threshold voltage of the selected memory cell shifted to the second logic state does not exceed a fourth value set as an upper limit thereof.
摘要翻译：一种非易失性半导体存储器件包括存储单元阵列，其中电可擦除可编程存储单元被排列，每个存储单元存储第一逻辑状态，阈值电压低于或等于第一值或第二逻辑具有高于或等于高于第一值的第二值的阈值电压的状态，用于保存从存储单元阵列读出的程序数据和感测数据的数据保持电路，以及控制器，其被配置为控制程序序列其中所述控制器具有以下控制功能：用于将程序电压施加到所述存储单元阵列的选定存储单元以使数据从第一逻辑状态移位到第二逻辑状态的程序控制功能; 程序验证控制功能，用于验证所选择的存储单元的编程数据移动到第二逻辑状态; 用于检查要保持在第一逻辑状态的存储单元的阈值电压不超过设置为第一逻辑状态的变化的上限值的第三值的不规则程序验证控制功能; 以及用于检查移动到第二逻辑状态的选择的存储单元的阈值电压不超过设定为其上限的第四值的过程序验证控制功能。

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