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1. 发明申请

US20140144337A1 APPARATUS AND METHOD FOR MANUFACTURING FIELD-POLE MAGNET 有权
标题翻译：用于制造现场磁铁的装置和方法
公开(公告)号：US20140144337A1
公开(公告)日：2014-05-29
申请号：US14234746
申请日：2012-06-20
申请人： Yasuhisa Koike , Kimio Nishimura , Hiroharu Takeuchi , Kunitomo Ishiguro , Kiyoshi Hasegawa , Yoshinori Izawa
发明人： Yasuhisa Koike , Kimio Nishimura , Hiroharu Takeuchi , Kunitomo Ishiguro , Kiyoshi Hasegawa , Yoshinori Izawa
IPC分类号： B30B15/00
CPC分类号： B30B15/0082 , B26F1/38 , B26F3/002 , B28D1/222 , B28D7/02 , B30B13/00 , H01F41/0253 , H02K15/03
摘要： A field-pole magnet manufacturing apparatus manufactures magnet pieces that constitute a field-pole magnet arranged in a rotary electric machine by fracturing the magnet. This manufacturing apparatus includes: a support unit on which the magnet is placed; a fracture unit that is arranged opposite to the support unit across the magnet and is configured to fracture the magnet by pressing the magnet while in contact with the magnet; and a powder removal unit that is configured to remove crush powder produced by fracture of the magnet.
摘要翻译：场磁极制造装置通过压碎磁体来制造构成旋转电机中的场极磁铁的磁体片。该制造装置包括：放置有磁体的支撑单元; 断裂单元，其与所述支撑单元相对地布置在所述磁体上，并且被构造成通过在与所述磁体接触的同时按压所述磁体而使所述磁体断裂; 以及粉碎去除单元，其构造成去除由所述磁体断裂产生的粉碎粉末。

2. 发明授权

US08705698B2 X-ray analyzer and mapping method for an X-ray analysis 有权
标题翻译： X射线分析仪和X线分析的绘图方法
公开(公告)号：US08705698B2
公开(公告)日：2014-04-22
申请号：US13027881
申请日：2011-02-15
申请人： Hiroshi Matsumura , Kiyoshi Hasegawa
发明人： Hiroshi Matsumura , Kiyoshi Hasegawa
IPC分类号： H05G1/62 , G01N23/201 , G06K9/78 , G06K9/82
CPC分类号： G01N23/223 , G01N2223/076 , G06T7/001 , G06T2207/10061 , G06T2207/10121 , G06T2207/30148
摘要： Provided are an X-ray analyzer and a mapping method for an X-ray analysis which, in a inspection for a harmful substance contained in, for example, a material or a composite electronic component, enable determination as to whether a sample is normal or abnormal to be performed visually based on an image obtained by the X-ray mapping analysis. In the X-ray analyzer, an X-ray mapping image of a sample which is confirmed to be normal in advance is obtained as a reference mapping image. A mapping analysis is performed on a inspection sample. A difference from the reference mapping image is obtained for each pixel, to thereby display a difference mapping image. A region in which the amount of specific element is larger than a reference amount is displayed with high brightness, and hence an abnormal portion may be easily found.
摘要翻译：提供了一种X射线分析仪和用于X射线分析的映射方法，其在包含在例如材料或复合电子部件中的有害物质的检查中能够确定样品是正常还是基于通过X射线映射分析获得的图像，可视化地进行异常。在X射线分析装置中，作为基准对照图像，获得确认为正常的样本的X射线映射图像。对检查样品进行映射分析。对于每个像素获得与参考映射图像的差异，从而显示差异映射图像。特定元素的量大于基准量的区域以高亮度显示，因此可能容易发现异常部分。

3. 发明申请

US20120234584A1 SUBSTRATE FOR MOUNTING SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING SAME 有权
标题翻译：用于安装半导体芯片的基板及其制造方法
公开(公告)号：US20120234584A1
公开(公告)日：2012-09-20
申请号：US13394688
申请日：2010-09-06
申请人： Yoshinori Ejiri , Kiyoshi Hasegawa , Takehisa Sakurai , Yoshiaki Tsubomatsu
发明人： Yoshinori Ejiri , Kiyoshi Hasegawa , Takehisa Sakurai , Yoshiaki Tsubomatsu
IPC分类号： H05K1/16 , H05K1/09
CPC分类号： H05K3/244 , H01L21/4857 , H01L2924/00013 , H01L2924/0002 , H05K3/062 , H05K3/108 , H05K3/4644 , H05K3/4652 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： It is an object of the invention to provide a method for producing a substrate for mounting a semiconductor chip, that can reduce bridging and allows excellent wire bondability and solder connection reliability to be obtained, even when forming fine-pitch wirings. The method for producing a substrate for mounting a semiconductor chip according to the invention comprises a resist-forming step in which a resist is formed on the first copper layer of a stack comprising an inner board with an inner layer circuit on the surface and a first copper layer formed on the inner board separated by an insulating layer at the sections other than those that are to constitute a conductor circuit, a conductor circuit-forming step in which a second copper layer is formed by electrolytic copper plating on the first copper layer to obtain a conductor circuit, a nickel layer-forming step in which a nickel layer is formed by electrolytic nickel plating on at least part of the conductor circuit, a resist removal step in which the resist is removed, an etching step in which the first copper layer is removed by etching, and a gold layer-forming step in which a gold layer is formed by electroless gold plating on at least part of the conductor circuit.
摘要翻译：本发明的目的是提供一种用于制造用于安装半导体芯片的基板的方法，即使在形成精细间距布线时也能够减少桥接并且能够获得优异的引线接合性和焊接连接可靠性。根据本发明的用于制造用于安装半导体芯片的基板的方法包括抗蚀剂形成步骤，其中在包括在内表层电路的内板上的第一铜层上形成抗蚀剂，并且第一铜层，其形成在内板上，除了构成导体电路的部分之外的绝缘层分隔开;导体电路形成步骤，其中通过在第一铜层上的电解铜电镀形成第二铜层，获得导体电路，镍层形成步骤，其中在导体电路的至少一部分上通过电解镀镍形成镍层，去除抗蚀剂的抗蚀剂去除步骤，其中第一铜通过蚀刻去除层，以及金层形成步骤，其中在导体电路的至少一部分上通过无电镀金形成金层。

4. 发明授权

US07862889B2 Adhesion assisting agent-bearing metal foil, printed wiring board, and production method of printed wiring board 有权
标题翻译：粘合辅助剂金属箔，印刷线路板和印刷线路板的制造方法
公开(公告)号：US07862889B2
公开(公告)日：2011-01-04
申请号：US12613222
申请日：2009-11-05
申请人： Kenji Takai , Norio Moriike , Kenichi Kamiyama , Takako Watanabe , Shin Takanezawa , Koji Morita , Katsuyuki Masuda , Kiyoshi Hasegawa
发明人： Kenji Takai , Norio Moriike , Kenichi Kamiyama , Takako Watanabe , Shin Takanezawa , Koji Morita , Katsuyuki Masuda , Kiyoshi Hasegawa
IPC分类号： B32B15/04 , H05K1/02
CPC分类号： H05K3/4655 , H05K3/108 , H05K3/28 , H05K3/386 , H05K3/389 , H05K3/4652 , H05K2201/0133 , H05K2201/0154 , H05K2201/0195 , H05K2201/0212 , H05K2201/0358 , H05K2203/0759 , Y10T428/12431 , Y10T428/24917 , Y10T428/2804 , Y10T428/287 , Y10T428/31681
摘要： The invention relates to an adhesion assisting agent-bearing metal foil comprising a layer of an adhesion assisting agent containing an epoxy resin as an indispensable component on a metal, wherein the adhesion assisting agent layer has a thickness of 0.1 to 10 μm. The invention also relates to a printed wiring board being a multilayer wiring board having a plurality of layers, wherein an adhesion assisting agent layer is formed between insulating layers.
摘要翻译：本发明涉及一种粘合促进剂金属箔，其包含含有环氧树脂作为金属上不可或缺的成分的粘合助剂层，其中粘合助剂层的厚度为0.1〜10μm。本发明还涉及作为具有多层的多层布线基板的印刷布线板，其中在绝缘层之间形成粘附辅助剂层。

5. 发明授权

US07794306B2 Surface finishing apparatus and related method 有权
标题翻译：表面处理装置及相关方法
公开(公告)号：US07794306B2
公开(公告)日：2010-09-14
申请号：US10772429
申请日：2004-02-06
申请人： Tomohiro Kondo , Masahiko Iizumi , Masahiro Omata , Kiyoshi Hasegawa , Takashi Ogino , Takafumi Watanabe , Yoshiyuki Chida , Yasushi Matsushita , Kazuo Takeda
发明人： Tomohiro Kondo , Masahiko Iizumi , Masahiro Omata , Kiyoshi Hasegawa , Takashi Ogino , Takafumi Watanabe , Yoshiyuki Chida , Yasushi Matsushita , Kazuo Takeda
IPC分类号： B24B1/30
CPC分类号： B24B49/16 , B24B5/42 , B24B19/12 , B24B21/00
摘要： An apparatus and method for surface finishing a workpiece is disclosed as including a workpiece supporting mechanism supporting a workpiece having a target shaped periphery with a given width to be surface finished and a tool holder holding a surface finish tool in abutting contact with the target shaped periphery of the workpiece. A pressure applying mechanism is operative to apply a pressure force to the surface finish tool through the tool holder to cause the surface finish tool to be held in pressured contact with the target shaped periphery, with the pressure force exhibiting a given distribution pattern depending upon an axial direction of the workpiece. A drive mechanism rotates the workpiece to allow the surface finish tool to surface finish the target shaped periphery into a given geometrical profile, variably contoured along an axis of the workpiece depending on the given pressure distribution pattern.
摘要翻译：公开了一种用于表面处理工件的装置和方法，包括：工件支撑机构，其支撑具有待表面加工的给定宽度的目标形状周边的工件;以及保持表面加工工具以与目标形状周边抵接的工具架的工件。压力施加机构可操作以通过工具保持器向表面加工工具施加压力，以使表面精加工工具与目标形状的周边保持压力接触，其中压力显示给定的分布图案，这取决于工件的轴向。驱动机构使工件旋转以允许表面光洁度工具将目标形状的周边表面光洁成给定的几何轮廓，根据给定的压力分布图案沿着工件的轴线可变地轮廓。

6. 发明申请

US20100044086A1 FORMATION METHOD OF METAL LAYER ON RESIN LAYER, PRINTED WIRING BOARD, AND PRODUCTION METHOD THEREOF 有权
标题翻译：树脂层，印刷线路板上金属层的形成方法及其生产方法
公开(公告)号：US20100044086A1
公开(公告)日：2010-02-25
申请号：US12614267
申请日：2009-11-06
申请人： Kenji Takai , Norio Moriike , Kenichi Kamiyama , Katsuyuki Masuda , Kiyoshi Hasegawa
发明人： Kenji Takai , Norio Moriike , Kenichi Kamiyama , Katsuyuki Masuda , Kiyoshi Hasegawa
IPC分类号： H05K1/09 , H05K1/03 , B05D5/12
CPC分类号： H05K3/386 , C23C18/1608 , C23C18/1653 , C23C18/2093 , C23C18/31 , C25D5/022 , H05K3/108 , H05K3/244 , H05K3/427 , H05K3/4644 , H05K3/4652 , H05K2201/0154 , H05K2201/0355 , H05K2203/072 , Y10S428/901 , Y10T29/49117 , Y10T29/49124 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165 , Y10T428/12472 , Y10T428/12493 , Y10T428/12507 , Y10T428/12514 , Y10T428/12535 , Y10T428/24917
摘要： A printed wiring board having a conductor circuit comprising a copper layer adjacent to an insulating layer and an electroless gold plating, wherein the insulating layer has ten-point mean surface roughness (Rz) of 2.0 μm or less is provided. According to the present invention, there is no such a defect that gold plating is deposited on a resin, and fine wiring formation with accuracy is realized.
摘要翻译：一种具有导体电路的印刷电路板，其特征在于，具有与绝缘层相邻的铜层和无电镀金，其特征在于，所述绝缘层的平均表面粗糙度（Rz）为20μm以下。根据本发明，没有在树脂上沉积镀金的缺陷，并且实现精确的精细布线形成。

7. 发明申请

US20080138505A1 FORMATION METHOD OF METAL LAYER ON RESIN LAYER, PRINTED WIRING BOARD, AND PRODUCTION METHOD THEREOF 审中-公开
标题翻译：树脂层，印刷线路板上金属层的形成方法及其生产方法
公开(公告)号：US20080138505A1
公开(公告)日：2008-06-12
申请号：US12022916
申请日：2008-01-30
申请人： Kenji Takai , Norio Moriike , Kenichi Kamiyama , Katsuyuki Masuda , Kiyoshi Hasegawa
发明人： Kenji Takai , Norio Moriike , Kenichi Kamiyama , Katsuyuki Masuda , Kiyoshi Hasegawa
IPC分类号： H05K3/00
CPC分类号： H05K3/386 , C23C18/1608 , C23C18/1653 , C23C18/2093 , C23C18/31 , C25D5/022 , H05K3/108 , H05K3/244 , H05K3/427 , H05K3/4644 , H05K3/4652 , H05K2201/0154 , H05K2201/0355 , H05K2203/072 , Y10S428/901 , Y10T29/49117 , Y10T29/49124 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165 , Y10T428/12472 , Y10T428/12493 , Y10T428/12507 , Y10T428/12514 , Y10T428/12535 , Y10T428/24917
摘要： A printed wiring board having a conductor circuit comprising a copper layer adjacent to an insulating layer and an electroless gold plating, wherein the insulating layer has ten-point mean surface roughness (Rz) of 2.0 μm or less is provided. According to the present invention, there is no such a defect that gold plating is deposited on a resin, and fine wiring formation with accuracy is realized.
摘要翻译：一种印刷电路板，其具有包括与绝缘层相邻的铜层的导体电路和无电镀金，其中，绝缘层具有2.0μm或更小的十点平均表面粗糙度（Rz）。根据本发明，没有在树脂上沉积镀金的缺陷，并且实现精确的精细布线形成。

8. 发明授权

US07033245B2 Lapping apparatus and lapping method 失效
标题翻译：研磨装置和研磨方法
公开(公告)号：US07033245B2
公开(公告)日：2006-04-25
申请号：US10774528
申请日：2004-02-10
申请人： Kiyoshi Hasegawa , Masahiko Iizumi , Masahiro Omata , Takashi Ogino , Tomohiro Kondo , Kazuo Takeda , Takafumi Watanabe , Yoshiyuki Chida , Yasushi Matsushita
发明人： Kiyoshi Hasegawa , Masahiko Iizumi , Masahiro Omata , Takashi Ogino , Tomohiro Kondo , Kazuo Takeda , Takafumi Watanabe , Yoshiyuki Chida , Yasushi Matsushita
IPC分类号： B24B49/02 , B24B19/12 , B24B21/06
CPC分类号： B24B49/16 , B24B5/42 , B24B19/12 , B24B21/00
摘要： A lapping apparatus lapping a work having a pre-machined surface comprises a lapping film which includes a thin substrate having a surface provided with abrasive grains, a shoe disposed at a back surface side of the lapping film, a shoe driving unit which drives the shoe toward the work in order to press the abrasive-grained surface of the lapping film to the pre-machined surface of the work, a rotational driving unit which drives the work rotationally, a detecting unit which detects the position of the rotating work in the rotating direction, and a controlling unit which controls the pressing force of the shoe driving unit so as to drive the shoe correspondingly to the position of the work in the rotating direction during machining.
摘要翻译：研磨具有预加工表面的工件的研磨装置包括研磨膜，其包括具有设置有磨粒的表面的薄基材，设置在研磨膜的背面侧的鞋，驱动鞋的鞋驱动单元朝向工作以将研磨膜的磨粒表面压到工件的预加工表面上，旋转驱动单元，其旋转地驱动工作;检测单元，其检测旋转工件在旋转中的位置方向和控制单元，其控制鞋驱动单元的按压力，以便在加工期间相应于工件在旋转方向上的位置驱动鞋。

9. 发明授权

US06975039B2 Method of forming a ball grid array package 失效
标题翻译：形成球栅阵列封装的方法
公开(公告)号：US06975039B2
公开(公告)日：2005-12-13
申请号：US10712054
申请日：2003-11-14
申请人： Kiyoshi Hasegawa , Fumihiko Ooka
发明人： Kiyoshi Hasegawa , Fumihiko Ooka
IPC分类号： H01L23/12 , H01L21/56 , H01L21/60 , H01L23/13 , H01L23/24 , H01L23/31 , H01L23/498 , H01L23/495 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/06 , H01L23/13 , H01L23/24 , H01L23/3107 , H01L23/49816 , H01L23/49827 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/94 , H01L24/97 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48465 , H01L2224/48599 , H01L2224/49171 , H01L2224/49175 , H01L2224/73204 , H01L2224/73215 , H01L2224/94 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a semiconductor chip having a major surface and first pads formed on the major surface. The semiconductor package also includes a package substrate having (a) opposite first and second major surfaces, (b) a side surface extending between the first and second major surfaces, (c) a pad forming region adjacent to and along the side surface, (d) second pads formed on the pad forming region, (e) external electrodes formed on the first major surface of the package substrate, wherein the second major surface of the package substrate is fixed to the major surface of the semiconductor chip, and wherein the external electrodes are electrically connected to the second pads. The semiconductor package further includes bonding wires electrically connecting the first pads to the second pads and a sealing material covering the bonding wires and first and second pads.
摘要翻译：半导体封装包括具有主表面的半导体芯片和在主表面上形成的第一焊盘。半导体封装还包括具有（a）相对的第一和第二主表面的封装衬底，（b）在第一和第二主表面之间延伸的侧表面，（c）与侧表面相邻并沿着侧表面的焊盘形成区域（ d）形成在焊盘形成区域上的第二焊盘，（e）形成在封装基板的第一主表面上的外部电极，其中封装基板的第二主表面固定到半导体芯片的主表面，并且其中外部电极电连接到第二焊盘。半导体封装还包括将第一焊盘电连接到第二焊盘的接合线和覆盖接合线以及第一和第二焊盘的密封材料。

10. 发明授权

US06811828B2 Electroless gold plating solution and method for electroless plating 有权
公开(公告)号：US06811828B2
公开(公告)日：2004-11-02
申请号：US10380548
申请日：2003-03-17
申请人： Akio Takahashi , Hiroshi Yamamoto , Sumiko Nakajima , Kiyoshi Hasegawa , Kanji Murakami
发明人： Akio Takahashi , Hiroshi Yamamoto , Sumiko Nakajima , Kiyoshi Hasegawa , Kanji Murakami
IPC分类号： B05D118
CPC分类号： C23C18/44
摘要： The present invention is aimed to provide an electroless gold plating solution which requires less amount of a reducing agent, retains a sufficient deposition rate for a practical use, and has an excellent stability as a plating solution; and a method for carrying out an electroless gold plating. The present invention provides an electroless gold plating solution comprising a gold salt, a phenyl compound based reducing agent and a water-soluble amine and a method for plating using the gold plating solution.

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