专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06551846B1 Semiconductor memory device capable of correctly and surely effecting voltage stress acceleration 失效
标题翻译：半导体存储器能够正确且可靠地实现电压应力加速
公开(公告)号：US06551846B1
公开(公告)日：2003-04-22
申请号：US09642751
申请日：2000-08-18
申请人： Kiyohiro Furutani , Mikio Asakura , Tetsuo Katoh
发明人： Kiyohiro Furutani , Mikio Asakura , Tetsuo Katoh
IPC分类号： G01R3126
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/3011 , Y10S257/905 , Y10S257/906 , Y10S257/907 , Y10S257/908 , H01L2924/00
摘要： A test signal generating circuit generates internal test control signals from a small number of signals supplied via an address terminal in a test mode operation. According to the test control signals, the values of internal row address signal bits from an address buffer are set, while a row-related control circuit with test control function controls operations of a row selection circuit and bit line peripheral circuitry according to the test control signals. A plurality of word lines are driven simultaneously into a selected state and an acceleration test is performed according to a small number of control signals in a short period of time. Voltage stress applied between memory cell capacitors and between word lines can be accelerated with a small number of control signals.
摘要翻译：测试信号发生电路在测试模式操作中从经由地址终端提供的少量信号产生内部测试控制信号。根据测试控制信号，设置来自地址缓冲器的内部行地址信号位的值，而具有测试控制功能的行相关控制电路根据测试控制来控制行选择电路和位线外围电路的操作信号。多个字线被同时驱动到选择状态，并且在短时间段内根据少量的控制信号执行加速度测试。存储单元电容器和字线之间施加的电压应力可以用少量的控制信号加速。

2. 发明授权

US06301163B1 Semiconductor memory device and method of checking same for defect 有权
标题翻译：半导体存储器件及其检查方法为缺陷
公开(公告)号：US06301163B1
公开(公告)日：2001-10-09
申请号：US09385582
申请日：1999-08-27
申请人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
发明人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
IPC分类号： G11C2900
CPC分类号： G11C29/24
摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.
摘要翻译：一种半导体存储器件，包括用于在测试模式下选择正常行中的存储单元的第一测试行解码器（9a），用于选择备用存储单元行的第二测试行解码器（9b），用于选择的第一测试列解码器正常列中的存储单元，以及用于选择备用存储单元列的第二测试列解码器（10b）。控制电路（11）可以通过使用控制信号（SRT）和控制信号（SCT）来执行行和列解码器的四个组合之间的切换。所有备用存储器单元在修补缺陷存储器单元以进行产量增强之前被测试。

3. 发明授权

US6055199A Test circuit for a semiconductor memory device and method for burn-in test 有权
标题翻译：一种用于半导体存储器件的测试电路和用于老化测试的方法
公开(公告)号：US6055199A
公开(公告)日：2000-04-25
申请号：US176880
申请日：1998-10-21
申请人： Kei Hamade , Kiyohiro Furutani , Takashi Kono , Mikio Asakura
发明人： Kei Hamade , Kiyohiro Furutani , Takashi Kono , Mikio Asakura
IPC分类号： G11C29/50 , G11C7/00
CPC分类号： G11C29/50 , G11C11/401
摘要： A circuit for supplying a stress to memory cells of a semiconductor memory device having the plurality of the memory cells respectively connected to a word line and a bit line comprises a circuit for generating precharge voltage for bit line, a bit line precharging and equalizing circuit which is connected between said circuit for generating precharge voltage for bit line and said memory cells, a pad connected to the bit line precharging and equalizing circuit for applying a desirable voltage to said memory cells through the corresponding bit lines, and a circuit connected to the circuit for generating precharge voltage for bit line for generating a signal for stopping the operation of said circuit for generating precharge voltage for bit line, whereby cell checker patterns can easily be realized in order to screen out possible failures not only in gate oxide films but also in capacitor dielectrics, storage node junctions or the like by applying an arbitrary stress voltage from the outside of the device.
摘要翻译：用于向具有分别连接到字线和位线的多个存储单元的半导体存储器件的存储单元提供应力的电路包括用于产生位线的预充电电压的电路，位线预充电和均衡电路，连接在所述用于产生位线的预充电电压的电路和所述存储单元之间，连接到位线预充电和均衡电路的焊盘，用于通过相应的位线向所述存储器单元施加期望的电压，以及连接到电路的电路用于产生用于产生用于产生用于产生用于产生位线的预充电电压的所述电路的操作的信号的位线的预充电电压，从而可以容易地实现电池检查器图案，以便不仅在栅极氧化膜中屏蔽可能的故障，电容器电介质，存储节点结等，从外部施加任意的应力电压设备侧。

4. 发明授权

US5764576A Semiconductor memory device and method of checking same for defect 失效
公开(公告)号：US5764576A
公开(公告)日：1998-06-09
申请号：US752419
申请日：1996-11-19
申请人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
发明人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , G11C29/14 , G11C29/24
CPC分类号： G11C29/24
摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

5. 发明授权

US5740119A Semiconductor memory device having internal address converting function, whose test and layout are conducted easily 失效
公开(公告)号：US5740119A
公开(公告)日：1998-04-14
申请号：US756505
申请日：1996-11-26
申请人： Mikio Asakura , Hideto Hidaka , Kiyohiro Furutani , Kenichi Yasuda
发明人： Mikio Asakura , Hideto Hidaka , Kiyohiro Furutani , Kenichi Yasuda
IPC分类号： G11C8/12 , G11C11/401 , G11C11/406 , G11C29/00 , G11C29/14 , G11C29/28 , G11C29/56 , G11C7/00
CPC分类号： G11C11/406 , G11C29/28 , G11C8/12
摘要： In a semiconductor memory device selectively implementing one of a 4K refresh cycle and a 8K refresh cycle, the positions of externally applied address signal bits are switched internally by address switching circuits such that memory cells at the same positions are selected regardless of whether the 4K refresh cycle or the 8K refresh cycle is specified according to a refresh cycle mode specify signal. As a result, by testing the device in one refresh cycle mode, the device can be checked in both refresh cycle operations, reducing the test time and making the test easier.

6. 发明授权

US5999464A Semiconductor memory device and method of checking same for defect 失效
公开(公告)号：US5999464A
公开(公告)日：1999-12-07
申请号：US58885
申请日：1998-04-13
申请人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
发明人： Hideto Hidaka , Mikio Asakura , Kiyohiro Furutani , Tetsuo Kato
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , G11C29/14 , G11C29/24
CPC分类号： G11C29/24
摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

7. 发明授权

US5970507A Semiconductor memory device having a refresh-cycle program circuit 失效
标题翻译：具有刷新循环程序电路的半导体存储器件
公开(公告)号：US5970507A
公开(公告)日：1999-10-19
申请号：US676963
申请日：1996-07-08
申请人： Tetsuo Kato , Kiyohiro Furutani , Hideto Hidaka , Mikio Asakura
发明人： Tetsuo Kato , Kiyohiro Furutani , Hideto Hidaka , Mikio Asakura
IPC分类号： G11C11/403 , G11C11/406 , G11C11/409 , G06F12/00
CPC分类号： G11C11/406
摘要： In a semiconductor memory device, a self refresh cycle program circuit is provided and a refresh operation is conducted in accordance with one of the refresh cycles programmed in the refresh-cycle program circuit. The refresh cycle of the self-refresh mode is selected from a plurality of refresh-cycle types. A plurality of refresh modes allows a refresh cycle to be selected from a plurality of refresh-cycle types in accordance with a selected refresh mode.
摘要翻译：在半导体存储器件中，提供自刷新周期程序电路，并且根据在刷新周期程序电路中编程的刷新周期之一进行刷新操作。从多个刷新周期类型中选择自刷新模式的刷新周期。多个刷新模式允许根据所选择的刷新模式从多个刷新周期类型中选择刷新周期。

8. 发明授权

US5867439A Semiconductor memory device having internal address converting function, whose test and layout are conducted easily 失效
标题翻译：具有内部地址转换功能的半导体存储器件，其测试和布局容易进行
公开(公告)号：US5867439A
公开(公告)日：1999-02-02
申请号：US22490
申请日：1998-02-12
申请人： Mikio Asakura , Hideto Hidaka , Kiyohiro Furutani , Kenichi Yasuda
发明人： Mikio Asakura , Hideto Hidaka , Kiyohiro Furutani , Kenichi Yasuda
IPC分类号： G11C8/12 , G11C11/401 , G11C11/406 , G11C29/00 , G11C29/14 , G11C29/28 , G11C29/56 , G11C7/00
CPC分类号： G11C11/406 , G11C29/28 , G11C8/12
摘要： In a semiconductor memory device selectively implementing one of a 4K refresh cycle and a 8K refresh cycle, the positions of externally applied address signal bits are switched internally by address switching circuits such that memory cells at the same positions are selected regardless of whether the 4K refresh cycle or the 8K refresh cycle is specified according to a refresh cycle mode specify signal. As a result, by testing the device in one refresh cycle mode, the device can be checked in both refresh cycle operations, reducing the test time and making the test easier.
摘要翻译：在选择性地实现4K刷新周期和8K刷新周期之一的半导体存储器件中，外部施加的地址信号位的位置由地址切换电路在内部切换，使得在相同位置的存储单元被选择，而不管4K刷新循环或8K刷新周期根据刷新周期模式指定信号指定。因此，通过在一个刷新周期模式下测试器件，可以在两个刷新周期操作中检查器件，减少测试时间并使测试更容易。

9. 发明授权

US5793686A Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output 失效
公开(公告)号：US5793686A
公开(公告)日：1998-08-11
申请号：US755930
申请日：1996-11-25
申请人： Kiyohiro Furutani , Tsukasa Ooishi , Mikio Asakura , Hideto Hidaka , Kei Hamade , Yoshito Nakaoka
发明人： Kiyohiro Furutani , Tsukasa Ooishi , Mikio Asakura , Hideto Hidaka , Kei Hamade , Yoshito Nakaoka
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C29/00 , G11C29/14 , G11C29/34 , G11C29/38 , G11C7/00
CPC分类号： G11C29/38 , G11C29/34 , G11C7/1051 , G11C7/1078
摘要： Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.

10. 发明授权

US06477105B2 Semiconductor memory device with a hierarchical word line configuration capable of preventing leakage current in a sub-word line driver 失效
标题翻译：具有能够防止子字线驱动器中的漏电流的分级字线配置的半导体存储器件
公开(公告)号：US06477105B2
公开(公告)日：2002-11-05
申请号：US10103698
申请日：2002-03-25
申请人： Kengo Aritomi , Mikio Asakura , Takashi Ito , Kiyohiro Furutani
发明人： Kengo Aritomi , Mikio Asakura , Takashi Ito , Kiyohiro Furutani
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C8/10 , G11C8/14
摘要： Complementary sub-decode signals to be provided to a sub-word line driver are separately generated through different circuits using individual power-supply voltages. Thus, the generation of a through current in the sub-word line driver is prevented.
摘要翻译：要提供给子字线驱动器的互补子解码信号通过使用各个电源电压的不同电路分别产生。因此，防止了在子字线驱动器中产生直通电流。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式