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1. 发明申请

US20050085028A1 Method and structure to suppress external latch-up 审中-公开
标题翻译：抑制外部闩锁的方法和结构
公开(公告)号：US20050085028A1
公开(公告)日：2005-04-21
申请号：US10605699
申请日：2003-10-21
申请人： Kiran Chatty , Peter Cottrell , Robert Gauthier , Mujahid Muhammad
发明人： Kiran Chatty , Peter Cottrell , Robert Gauthier , Mujahid Muhammad
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0921
摘要： A method and structure for protection against latch-up is provided. Integrated circuits manufactured in accordance with the present disclosure feature well and substrate contacts of varying periodicity. Such a strategy enables maximizing the design of an integrated circuit as to the suppression of latch-up while concurrently optimizing available area on the chip allocable to circuit design. This method and structure is particularly beneficial to protect against cable discharge events and other discharge occurrences prone to injecting large current densities into an integrated circuit.
摘要翻译：提供了一种用于防止闩锁的方法和结构。根据本公开制造的集成电路特征良好，并且具有不同周期性的衬底触点。这样的策略能够最大化集成电路的设计，以抑制闩锁，同时优化可分配给电路设计的芯片上的可用区域。该方法和结构特别有利于防止电缆放电事件和易于将大电流密度注入集成电路的其它放电事件。

2. 发明申请

US20050224882A1 LOW TRIGGER VOLTAGE ESD NMOSFET TRIPLE-WELL CMOS DEVICES 审中-公开
标题翻译：低触发电压ESD NMOSFET三阱CMOS器件
公开(公告)号：US20050224882A1
公开(公告)日：2005-10-13
申请号：US10709041
申请日：2004-04-08
申请人： Kiran Chatty , Robert Gauthier , Mujahid Muhammad , Christopher Putnam
发明人： Kiran Chatty , Robert Gauthier , Mujahid Muhammad , Christopher Putnam
IPC分类号： H01L23/62 , H01L29/06 , H01L29/10 , H01L29/78
CPC分类号： H01L29/78 , H01L29/0653 , H01L29/1083 , H01L2924/0002 , H01L2924/00
摘要： An ESD NMOSFET, and a method for lowering a ESD NMOSFET trigger voltage. An ESD NMOSFET is configured in triple well CMOS architecture where the first well is separated from second and third wells by respective shallow well isolation regions. The first well is also separated from the substrate along the bottom by a conductive band region. A substrate contact is located outside of the first, second and third wells, and provides a current path during an ESD event from the first well. Source and drain regions are formed in the first well, to form an FET with the drain being connected to an I/O pad which is subject to an ESD event. A resistive path extends through an opening in the conductive band region to a substrate contact, providing an increased I/O pad to substrate resistance which decreases the trigger voltage for the ESD NMOSFET.
摘要翻译： ESD NMOSFET，以及降低ESD NMOSFET触发电压的方法。 ESD NMOSFET配置在三阱CMOS结构中，其中第一阱通过相应的浅阱隔离区与第二阱和第三阱分离。第一阱也通过导电带区沿着底部与衬底分离。衬底触点位于第一，第二和第三阱的外部，并且在来自第一阱的ESD事件期间提供电流路径。源极和漏极区域形成在第一阱中，以形成FET，其漏极连接到经受ESD事件的I / O焊盘。电阻路径延伸穿过导电带区域中的开口到衬底接触，从而为衬底电阻提供增加的I / O焊盘，从而降低ESD NMOSFET的触发电压。

3. 发明申请

US20050227418A1 METHOD FOR CREATING A SELF-ALIGNED SOI DIODE BY REMOVING A POLYSILICON GATE DURING PROCESSING 失效
标题翻译：通过在加工过程中移除多晶硅栅极创建自对准SOI二极管的方法
公开(公告)号：US20050227418A1
公开(公告)日：2005-10-13
申请号：US10708912
申请日：2004-03-31
申请人： Kiran Chatty , Robert Gauthier , Mujahid Muhammad , Christopher Putnam
发明人： Kiran Chatty , Robert Gauthier , Mujahid Muhammad , Christopher Putnam
IPC分类号： H01L21/329 , H01L21/84 , H01L27/02 , H01L27/12 , H01L29/861
CPC分类号： H01L27/0255 , H01L21/84 , H01L27/1203 , H01L29/66136 , H01L29/861
摘要： A method of forming a self-aligned SOI diode, the method comprising depositing a protective structure over a substrate; implanting a plurality of diffusion regions of variable dopant types in an area between at least one pair of isolation regions in the substrate, the plurality of diffusion regions separated by a diode junction, wherein the implanting aligns an upper surface of the diode junction with the protective structure; and removing the protective structure. The method further comprises forming a silicide layer over the diffusion regions and aligned with the protective structure. The protective structure comprises a hard mask, wherein the hard mask comprises a silicon nitride layer. Alternatively, the protective structure comprises a polysilicon gate and insulating spacers on opposite sides of the gate. Furthermore, in the removing step, the spacers remain on the substrate.
摘要翻译：一种形成自对准SOI二极管的方法，所述方法包括在衬底上沉积保护结构; 在衬底中的至少一对隔离区域之间的区域中注入多个可变掺杂剂类型的扩散区域，所述多个扩散区域被二极管结点隔开，其中所述注入将所述二极管结的上表面与所述保护层结构体; 并移除保护结构。该方法还包括在扩散区上形成硅化物层并与保护结构对准。保护结构包括硬掩模，其中硬掩模包括氮化硅层。或者，保护结构包括在栅极的相对侧上的多晶硅栅极和绝缘间隔物。此外，在去除步骤中，衬垫保留在衬底上。

4. 发明申请

US20060157799A1 LOW TRIGGER VOLTAGE, LOW LEAKAGE ESD NFET 失效
标题翻译：低触发电压，低漏电ESD NFET
公开(公告)号：US20060157799A1
公开(公告)日：2006-07-20
申请号：US10905682
申请日：2005-01-17
申请人： Kiran Chatty , Robert Gauthier , Terence Hook , Christopher Putnam , Mujahid Muhammad
发明人： Kiran Chatty , Robert Gauthier , Terence Hook , Christopher Putnam , Mujahid Muhammad
IPC分类号： H01L29/76
CPC分类号： H01L29/78 , H01L27/027
摘要： A field effect transistor with associated parasitic lateral npn bipolar junction transistor includes a source region in a substrate, a channel region in the substrate laterally adjacent to the source region, a drain region in the substrate laterally adjacent to the channel region, and a gate above the channel region of the substrate. In addition, a reduced trigger voltage region of the substrate is positioned below the drain region. The reduced trigger voltage region has a threshold voltage of about zero and comprises an undoped region of the pure wafer substrate. Thus, the reduced trigger voltage region is free of implanted N-type and P-type doping.
摘要翻译：具有相关联的寄生横向npn双极结型晶体管的场效应晶体管包括衬底中的源极区域，与源极区域横向相邻的衬底中的沟道区域，衬底中的与沟道区域横向相邻的漏极区域，以及位于衬底的沟道区域。此外，衬底的降低的触发电压区域位于漏极区域的下方。降低的触发电压区域具有约零的阈值电压，并且包括纯晶片衬底的未掺杂区域。因此，降低的触发电压区域没有注入的N型和P型掺杂。

5. 发明申请

US20050045952A1 PFET-BASED ESD PROTECTION STRATEGY FOR IMPROVED EXTERNAL LATCH-UP ROBUSTNESS 审中-公开
标题翻译：基于PFET的ESD保护策略，用于改进外部锁定稳定性
公开(公告)号：US20050045952A1
公开(公告)日：2005-03-03
申请号：US10604922
申请日：2003-08-27
申请人： Kiran Chatty , Robert Gauthier , Mujahid Muhammad , Christopher Putnam
发明人： Kiran Chatty , Robert Gauthier , Mujahid Muhammad , Christopher Putnam
IPC分类号： H01L21/336 , H01L27/02
CPC分类号： H01L27/0266
摘要： A method and apparatus for protection against electrostatic discharge (ESD) with improved latch-up robustness featuring a silicide blocked p-type field effect transistor is disclosed. The transistor has a snapback voltage that is less than the breakdown voltage of its gate oxide. The transistor is part of an integrated circuit and coupled to an I/O pad having no n-diffusions connected directly to it. A given integrated circuit may employ one or more the transistors configured in accordance with the invention that are associated with one or more I/O pads within the integrated circuit.
摘要翻译：公开了一种具有改进的闩锁鲁棒性的防静电放电（ESD）的方法和装置，其具有硅化物阻挡的p型场效应晶体管。晶体管具有小于其栅极氧化物的击穿电压的快速恢复电压。晶体管是集成电路的一部分，并且耦合到没有直接连接到其的n扩散的I / O焊盘。给定的集成电路可以采用根据本发明配置的一个或多个与集成电路内的一个或多个I / O焊盘相关联的晶体管。

6. 发明申请

US20060072267A1 HIGH VOLTAGE ESD POWER CLAMP 失效
标题翻译：高电压ESD功率钳位
公开(公告)号：US20060072267A1
公开(公告)日：2006-04-06
申请号：US10711748
申请日：2004-10-01
申请人： Kiran Chatty , Robert Gauthier , Mahmoud Mousa , Mujahid Muhammad , Christopher Putnam
发明人： Kiran Chatty , Robert Gauthier , Mahmoud Mousa , Mujahid Muhammad , Christopher Putnam
IPC分类号： H03K19/0175
CPC分类号： H01L27/0266 , H03K17/08142
摘要： A structure and apparatus is provided for an electrostatic discharge power clamp, for use with high voltage power supplies. The power clamp includes a network of transistor devices, for example, nFETs arranged in series between a power rail and a ground rail. The first transistor device is biased into a partially on-state, and thus, neither device sees the full voltage potential between the power rail and the ground rail. Accordingly, the power clamp can function in voltage environments higher than the native voltage of the transistor devices. Additionally, the second transistor device is controlled by an RC network functioning as a trigger which allows the second transistor device to turn on during a voltage spike such as occurs during an ESD event. The capacitor of the RC network may be small thereby requiring small real estate on the integrated circuit. The clamp may have fast turn-on times as well as conducting current for long periods of time after turning on.
摘要翻译：为静电放电电源钳提供一种用于高压电源的结构和装置。功率钳包括晶体管器件网络，例如串联布置在电源轨和接地轨之间的nFET。第一晶体管器件被偏置成部分导通状态，因此，两个器件都不会看到电源轨和接地轨之间的全电压电位。因此，功率钳可以在高于晶体管器件的天然电压的电压环境中工作。此外，第二晶体管器件由用作触发器的RC网络来控制，该RC网络允许第二晶体管器件在诸如在ESD事件期间发生的电压尖峰期间导通。 RC网络的电容器可能很小，从而在集成电路上需要小的空间。打开后，夹具可能会导通快速导通时间，并长时间传导电流。

7. 发明授权

US08597993B2 Electrostatic discharge (ESD) device and method of fabricating 有权
标题翻译：静电放电（ESD）器件及其制造方法
公开(公告)号：US08597993B2
公开(公告)日：2013-12-03
申请号：US12048461
申请日：2008-03-14
申请人： Shunhua Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Mujahid Muhammad
发明人： Shunhua Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Mujahid Muhammad
IPC分类号： H01L21/8238
CPC分类号： H01L27/0259 , H01L27/0277 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.
摘要翻译：通过将三极管内的pFET与NMOSFET或n-p-n之间的PMOS双极集成在一起来制造集成电路芯片中的静电放电（EDS）电路的结构和方法。横向双极性优选地包括在电路的I / O和/或VDD处的二极管。

8. 发明授权

US08513738B2 ESD field-effect transistor and integrated diffusion resistor 有权
标题翻译： ESD场效应晶体管和集成扩散电阻
公开(公告)号：US08513738B2
公开(公告)日：2013-08-20
申请号：US13188094
申请日：2011-07-21
申请人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L23/60
CPC分类号： H01L29/41775 , H01L27/0266 , H01L29/1087 , H01L29/66659 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor.
摘要翻译：静电放电保护装置，静电放电保护装置的制造方法以及静电放电保护装置的设计结构。第一场效应晶体管的漏极和较高电阻的扩散电阻可以形成为掺杂区域的不同部分。可以使用布置在掺杂区域中的介电材料的隔离区域和选择性硅化物形成来限定与第一场效应晶体管的漏极直接耦合的扩散电阻器。静电放电保护器件还可以包括第二场效应晶体管，其具有作为与扩散电阻器直接耦合并且由扩散电阻器与第一场效应晶体管的漏极间接耦合的掺杂区域的一部分的漏极。

9. 发明授权

US08299533B2 Vertical NPNP structure in a triple well CMOS process 有权
标题翻译：三阱CMOS工艺中的垂直NPNP结构
公开(公告)号：US08299533B2
公开(公告)日：2012-10-30
申请号：US12954155
申请日：2010-11-24
申请人： John B. Campi, Jr. , Shunhua Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, Jr. , Shunhua Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L23/62
CPC分类号： H01L29/74 , H01L21/823892 , H01L27/0262 , H01L27/0928 , H01L2924/0002 , H01L2924/00
摘要： A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.
摘要翻译：使用三阱CMOS工艺制造的垂直NPNP结构，以及制造垂直NPNP结构的方法，提供静电放电（ESD）保护的方法和BiCMOS集成电路的设计结构。垂直NPNP结构可用于从负电压ESD事件向输入/输出（I / O）焊盘提供片上保护。也可以使用垂直PNPN结构来保护相同的I / O焊盘免受正电压ESD事件的影响。

10. 发明申请

US20120126285A1 Vertical NPNP Structure In a Triple Well CMOS Process 有权
标题翻译：三井CMOS工艺中的垂直NPNP结构
公开(公告)号：US20120126285A1
公开(公告)日：2012-05-24
申请号：US12954155
申请日：2010-11-24
申请人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L29/74 , G06F17/50 , H01L21/332
CPC分类号： H01L29/74 , H01L21/823892 , H01L27/0262 , H01L27/0928 , H01L2924/0002 , H01L2924/00
摘要： A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.
摘要翻译：使用三阱CMOS工艺制造的垂直NPNP结构，以及制造垂直NPNP结构的方法，提供静电放电（ESD）保护的方法和BiCMOS集成电路的设计结构。垂直NPNP结构可用于从负电压ESD事件向输入/输出（I / O）焊盘提供片上保护。也可以使用垂直PNPN结构来保护相同的I / O焊盘免受正电压ESD事件的影响。

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