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1. 发明授权

US4841353A Transistor devices for microwave oscillator elements 失效
标题翻译：用于微波振荡器元件的晶体管器件
公开(公告)号：US4841353A
公开(公告)日：1989-06-20
申请号：US129390
申请日：1987-11-24
申请人： Kenzo Wada , Eiji Nagata
发明人： Kenzo Wada , Eiji Nagata
IPC分类号： H01L23/12 , H01L23/66 , H01P5/02 , H03B5/18
CPC分类号： H01L24/49 , H01L23/66 , H01L2223/6644 , H01L2224/48091 , H01L2224/4813 , H01L2224/48247 , H01L2224/49175 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01014 , H01L2924/01015 , H01L2924/01031 , H01L2924/01033 , H01L2924/01055 , H01L2924/01082 , H01L2924/10329 , H01L2924/12032 , H01L2924/1306 , H01L2924/15153 , H01L2924/1517 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011
摘要： A transistor device for a microwave oscillating element having an FET transistor chip and a package encapsulating the chip therein. In order to avoid any affection of the external circuit to the input impedance of the transistor device and to make the phase rotation low at a frequency band higher than the X band, a conductor element is provided within the package to connect the drain electrode of the chip and a corresponding terminal of the package. The conductor element has an inductance to provide a sufficient high impedance at the intended frequency band. The conductor element is supported on an insulator plate fixedly mounted within the package.
摘要翻译：一种用于微波振荡元件的晶体管器件，具有FET晶体管芯片和封装芯片的封装。为了避免外部电路对晶体管器件的输入阻抗的任何影响，并使相位旋转低于高于X频带的频带，导体元件设置在封装内以连接芯片和相应的封装端子。导体元件具有电感以在期望的频带提供足够的高阻抗。导体元件被支撑在固定地安装在封装内的绝缘板上。

2. 发明授权

US06882175B2 Inter-block interface circuit and system LSI 有权
标题翻译：块间接口电路和系统LSI
公开(公告)号：US06882175B2
公开(公告)日：2005-04-19
申请号：US10460175
申请日：2003-06-13
申请人： Isao Motegi , Eiji Nagata
发明人： Isao Motegi , Eiji Nagata
IPC分类号： H01L21/822 , H01L27/04 , H03K19/00 , H03K17/16 , H03K19/003
CPC分类号： H03K19/0016
摘要： An inter-block interface circuit which effectively prevents occurrences of inconveniences (for example, such that a shoot-through current flows due to unsteady potential in wiring) caused by switching off a power supply of a block, using simple circuitry, in LSI such that signals are communicated between the blocks and the power supplies of the blocks are interrupted independently. In the circuit, gate circuits 112 and 114 are respectively provided in blocks 102 and 104 that communicate signals with one another, and interface control circuit 202 dynamically controls respective input levels of gate circuits 112 and 114. In other words, the circuit 202 fixes an input level of gate circuit 112 or 114 in a block whose power supply is ON to “L”, and thereby compulsively fixes an output level of the gate circuit to “L”.
摘要翻译：一种块间接口电路，其有效地防止了在LSI中使用简单的电路关闭块的电源而引起的不方便（例如，由于布线中的不稳定电位而导致直通电流流动）信号在块之间通信，块的电源被独立中断。在电路中，门电路112和114分别设置在彼此传送信号的块102和104中，并且接口控制电路202动态地控制门电路112和114的相应输入电平。换句话说，电路202将电源接通的块中的门电路112或114的输入电平固定为“L”，从而强制将门电路的输出电平固定为“L”。

3. 发明申请

US20090311519A1 Metal composite film and process for producing the same 失效
标题翻译：金属复合膜及其制造方法
公开(公告)号：US20090311519A1
公开(公告)日：2009-12-17
申请号：US12227330
申请日：2006-05-17
申请人： Eiji Nagata , Hiroyuki Ishii
发明人： Eiji Nagata , Hiroyuki Ishii
IPC分类号： B32B15/08 , B32B27/08 , C23C28/02
CPC分类号： H05K1/036 , B32B15/08 , B32B27/28 , B32B27/34 , B32B2274/00 , B32B2457/08 , C23C18/1653 , C23C18/2066 , C23C18/31 , C23C28/00 , C25D7/00 , H05K1/0346 , H05K1/0393 , H05K3/181 , H05K2201/0129 , H05K2201/0154 , Y10T428/264 , Y10T428/265 , Y10T428/269 , Y10T428/31681
摘要： A metal composite film having an excellent heat resistance and adhesion, suited for flexible printed circuit boards capable of forming fine wirings, as well as a production process thereof, is disclosed. The metal composite film comprises an insulating film; a thermoplastic polyimide layer(s) formed on at least one surface of the insulating film; and metal layers formed on the surface of each of the thermoplastic polyimide layer(s), which metal layers are formed by electroless plating and then by electrolytic plating, respectively. Since this metal composite film has an excellent heat resistance and adhesion, and maintains the excellent adhesion after forming fine wirings, it is suitably used as a high density flexible printed circuit board having fine circuits.
摘要翻译：公开了一种具有优异的耐热性和粘合性的金属复合膜，适用于能够形成细线的柔性印刷电路板及其制造方法。金属复合膜包括绝缘膜; 形成在所述绝缘膜的至少一个表面上的热塑性聚酰亚胺层; 以及形成在每个热塑性聚酰亚胺层的表面上的金属层，该金属层分别通过无电镀形成，然后通过电解电镀形成。由于该金属复合膜具有优异的耐热性和粘附性，并且在形成细线之后保持优异的粘附性，因此适合用作具有精细电路的高密度柔性印刷电路板。

4. 发明申请

US20070172674A1 Resin composite copper foil, printed wiring board, and production processes thereof 有权
标题翻译：树脂复合铜箔，印刷线路板及其制造方法
公开(公告)号：US20070172674A1
公开(公告)日：2007-07-26
申请号：US11657529
申请日：2007-01-25
申请人： Mitsuru Nozaki , Morio Gaku , Yasuo Tanaka , Eiji Nagata , Yasuo Kikuchi , Masashi Yano
发明人： Mitsuru Nozaki , Morio Gaku , Yasuo Tanaka , Eiji Nagata , Yasuo Kikuchi , Masashi Yano
IPC分类号： B32B15/08
CPC分类号： B32B27/281 , B32B7/06 , B32B15/14 , B32B15/20 , B32B27/38 , C08G73/1042 , C08G73/12 , H05K3/181 , H05K3/386 , H05K2201/0154 , H05K2201/0358 , H05K2203/1152 , Y10S428/901 , Y10T428/31681 , Y10T428/31721
摘要： A resin composite copper foil comprising a copper foil and a resin layer containing a block copolymer polyimide and a maleimide compound, the resin layer being formed on one surface of the copper foil, a production process thereof, a copper-clad laminate using the resin composite copper foil, a production process of a printed wiring board using the copper-clad laminate, and a printed wiring board obtained by the above process.
摘要翻译：一种树脂复合铜箔，其包含铜箔和含有嵌段共聚物聚酰亚胺和马来酰亚胺化合物的树脂层，所述树脂层形成在所述铜箔的一个表面上，其制造方法，使用所述树脂复合材料的覆铜层压板铜箔，使用覆铜层压板的印刷电路板的制造方法，以及通过上述方法得到的印刷电路板。

5. 发明授权

US08771496B2 Process for producing metal composite film 失效
标题翻译：金属复合膜生产工艺
公开(公告)号：US08771496B2
公开(公告)日：2014-07-08
申请号：US12227330
申请日：2006-05-17
申请人： Eiji Nagata , Hiroyuki Ishii
发明人： Eiji Nagata , Hiroyuki Ishii
IPC分类号： C23C28/02 , C23C18/31 , C25D7/00 , B32B15/08 , B32B15/20 , B32B27/06
CPC分类号： H05K1/036 , B32B15/08 , B32B27/28 , B32B27/34 , B32B2274/00 , B32B2457/08 , C23C18/1653 , C23C18/2066 , C23C18/31 , C23C28/00 , C25D7/00 , H05K1/0346 , H05K1/0393 , H05K3/181 , H05K2201/0129 , H05K2201/0154 , Y10T428/264 , Y10T428/265 , Y10T428/269 , Y10T428/31681
摘要： A metal composite film having an excellent heat resistance and adhesion, suited for flexible printed circuit boards capable of forming fine wirings, as well as a production process thereof, is disclosed. The metal composite film comprises an insulating film; a thermoplastic polyimide layer(s) formed on at least one surface of the insulating film; and metal layers formed on the surface of each of the thermoplastic polyimide layer(s), which metal layers are formed by electroless plating and then by electrolytic plating, respectively. Since this metal composite film has an excellent heat resistance and adhesion, and maintains the excellent adhesion after forming fine wirings, it is suitably used as a high density flexible printed circuit board having fine circuits.
摘要翻译：公开了一种具有优异的耐热性和粘合性的金属复合膜，适用于能够形成细线的柔性印刷电路板及其制造方法。金属复合膜包括绝缘膜; 形成在所述绝缘膜的至少一个表面上的热塑性聚酰亚胺层; 以及形成在每个热塑性聚酰亚胺层的表面上的金属层，该金属层分别通过无电镀形成，然后通过电解电镀形成。由于该金属复合膜具有优异的耐热性和粘附性，并且在形成细线之后保持优异的粘附性，因此适合用作具有精细电路的高密度柔性印刷电路板。

6. 发明授权

US07146550B2 Isolation testing circuit and testing circuit optimization method 有权
标题翻译：隔离测试电路和测试电路优化方法
公开(公告)号：US07146550B2
公开(公告)日：2006-12-05
申请号：US10792809
申请日：2004-03-05
申请人： Eiji Nagata
发明人： Eiji Nagata
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G01R31/31704 , H01L2924/0002 , H01L2924/00
摘要： In order to avoid generation of a routing complexity of LSI and a signal rounding due to insertion of the isolation testing circuit, if a plurality of IPs are incorporated into LSI, the present invention provides an isolation testing circuits having test switching selectors 731 to 736 for selecting any one of a test input signal (or a test input transit signal) and a normal input signal, and test signal transit buffers 721 to 726 for relaying the test input signal (or the test input transit signal) are formed in respective IP blocks 701 to 706 incorporated into an LSI. Adjacent isolation testing circuits are connected mutually based on a floor plan or layout placement information such that a wiring length of a test input signal 709 and test input transit signals 710 to 714, which are connected in a single stroke of a pen, can be reduced shortest.
摘要翻译：为了避免由于隔离测试电路的插入而导致LSI的布线复杂度的产生和舍入的信号，如果多个IP被并入到LSI中，本发明提供一种具有测试切换选择器731至736的隔离测试电路，用于选择测试输入信号（或测试输入转接信号）和正常输入信号中的任何一个，并且在相应的IP块中形成用于中继测试输入信号（或测试输入转接信号）的测试信号中继缓冲器721至726 701至706并入LSI。相邻的隔离测试电路基于平面图或布局布置信息相互连接，使得可以减少连接在笔的单个行程中的测试输入信号709和测试输入转接信号710至714的布线长度最短

7. 发明申请

US20120189859A1 RESIN COMPOSITE ELECTROLYTIC COPPER FOIL, COPPER CLAD LAMINATE AND PRINTED WIRING BOARD 审中-公开
标题翻译：树脂复合电解铜箔，铜箔层压板和印刷线
公开(公告)号：US20120189859A1
公开(公告)日：2012-07-26
申请号：US13386751
申请日：2010-06-25
申请人： Mitsuru Nozaki , Akihiro Nomoto , Norikatsu Akiyama , Eiji Nagata , Masashi Yano
发明人： Mitsuru Nozaki , Akihiro Nomoto , Norikatsu Akiyama , Eiji Nagata , Masashi Yano
IPC分类号： B32B15/08
CPC分类号： H05K1/09 , B32B15/08 , C25D1/04 , C25D5/022 , C25D7/0614 , C25D7/0678 , H05K1/0346 , H05K1/0373 , H05K3/384 , H05K3/4652 , H05K2201/0154 , H05K2201/0355 , H05K2201/0358 , H05K2203/0307 , Y10T428/31681
摘要： The problem of the invention is to provide a resin composite electrolytic copper foil having further improved heat resistance and improved plate adhesion strength when plated after desmear treatment in the work process of an additive method. The solution is to form a roughened surface having a plurality of minute projections, a surface roughness (Rz) within a range of 1.0 μm to 3.0 μm and a lightness value of not more than 30 on one surface of an electrolytic copper foil, and form a layer of a resin composition containing a block copolymerized polyimide resin having a structure that imide oligomers of a first structural unit and a second structural unit are bonded alternately and repeatedly on the roughened surface.
摘要翻译：本发明的问题是提供一种在添加剂方法的工作过程中在去污处理后进行电镀时耐热性进一步提高和板粘附强度提高的树脂复合电解铜箔。该溶液是形成具有多个微小突起的粗糙表面，在电解铜箔的一个表面上的表面粗糙度（Rz）在1.0μm至3.0μm范围内且亮度值不大于30，并且形成含有嵌段共聚聚酰亚胺树脂的树脂组合物层，其具有在第一结构单元和第二结构单元上的酰亚胺低聚物的结构在粗糙化表面上交替重复地结合。

8. 发明申请

US20110219219A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND REGISTER ADDRESS CONTROLLER 审中-公开
标题翻译：半导体集成电路和寄存器地址控制器
公开(公告)号：US20110219219A1
公开(公告)日：2011-09-08
申请号：US13110664
申请日：2011-05-18
申请人： Yuusuke ADACHI , Eiji Nagata
发明人： Yuusuke ADACHI , Eiji Nagata
IPC分类号： G06F9/30
CPC分类号： G06F9/384
摘要： This invention provides with a semiconductor integrated circuit, comprising a register map that makes correspondence between a register to which a CPU accesses and an address which specifies the register, wherein the register map includes a plurality of register maps in which assignments of address bits are rearranged in correspondence with each of a plurality of modes, and wherein any of the register maps is selected from the plurality of register maps according to the respective modes.
摘要翻译：本发明提供了一种半导体集成电路，包括使CPU访问的寄存器和指定寄存器的地址之间的对应关系的寄存器映射，其中寄存器映射包括多个寄存器映射，其中地址位的分配被重新排列与多个模式中的每一个相对应，并且其中根据各个模式从多个寄存器映射中选择任何寄存器映射。

9. 发明授权

US07346871B2 Method of estimating wiring complexity degree in semiconductor integrated circuit 有权
标题翻译：估算半导体集成电路布线复杂程度的方法
公开(公告)号：US07346871B2
公开(公告)日：2008-03-18
申请号：US11299757
申请日：2005-12-13
申请人： Fumihito Watanuki , Eiji Nagata
发明人： Fumihito Watanuki , Eiji Nagata
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , H01L27/0207
摘要： A method of estimating a wiring complexity degree in a semiconductor integrated circuit with a multi-layered wiring, which has a wiring structure including at least two layers or more, in laying signal wirings, includes a step of predicting a power-supply wiring space used in the semiconductor integrated circuit, a step of dividing the predicted power-supply wiring space onto respective wiring layers, and a step of estimating a complexity degree at a time of laying signal wirings, based on the predicted power-supply wiring space and a wiring specification in respective wiring layers every wiring layer.
摘要翻译：在敷设信号配线的情况下，具有包括至少两层以上的布线结构的多层布线的半导体集成电路中的布线复杂度的估计方法包括以下步骤：使用的电源布线空间在半导体集成电路中，将预测电力配线空间分割到各布线层上的步骤，以及基于预测的电源布线空间和布线来估计铺设信号布线时的复杂度的步骤规格各布线层每一布线层。

10. 发明授权

US4736168A Dielectric resonator controlled oscillator having a raised frequency multiplying efficiency 失效
标题翻译：具有升高的倍频效率的介质谐振器控制振荡器
公开(公告)号：US4736168A
公开(公告)日：1988-04-05
申请号：US43286
申请日：1987-03-18
申请人： Eiji Nagata
发明人： Eiji Nagata
IPC分类号： H03B19/00 , H03B5/18 , H03B19/14
CPC分类号： H03B5/1876 , H03B19/14 , H03B2200/007 , H03B5/1852
摘要： In a dielectric resonator controlled oscillator with frequency multiplication, a line (12) has an open end and another end connected to a gate electrode of an FET (11) with a dielectric resonator (13) electromagnetically coupled to the line at a location along a total length of the line. The total length is selected to make a combination of the line and the dielectric resonator have a substantially zero impedance for a higher harmonic frequency when seen from the gate electrode. More specifically, the total length is selected so as to be equal to about three quarters of a wavelength which a frequency multiplied oscillation, such as a frequency doubled oscillation, has in the line. The location is selected so as to optimize the oscillator for a fundamental oscillation of a fundamental frequency determined by the dielectric resonator.
摘要翻译： PCT No.PCT / JP86 / 00390 Sec。 371日期1987年3月18日 102（e）1987年3月18日PCT PCT 1986年7月23日PCT公布。公开号WO87 / 00707 日本1987年1月29日。在具有倍频的介质谐振器控制振荡器中，线（12）具有开口端，另一端连接到具有电介质谐振器（13）的FET（11）的栅电极，电介质谐振器沿着线的总长度的一个位置的线。总长度被选择为使得当从栅电极观察时，线和介质谐振器的组合对于较高谐波频率具有基本零阻抗。更具体地，总长度被选择为等于频率倍增振荡（例如倍频振荡）的波长的大约四分之三。选择该位置以优化用于由介质谐振器确定的基频的基本振荡的振荡器。

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