专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06480423B2 High-speed cycle clock-synchronous memory device 失效
标题翻译：高速循环时钟同步存储器件
公开(公告)号：US06480423B2
公开(公告)日：2002-11-12
申请号：US09873313
申请日：2001-06-05
申请人： Haruki Toda , Kenji Tsuchida , Hitoshi Kuyama
发明人： Haruki Toda , Kenji Tsuchida , Hitoshi Kuyama
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C7/1072 , G11C11/4087
摘要： A high-speed clock-synchronous memory device is provided with a sense amplifier S/A shared by and between cell arrays, and a cell array controller unit CNTRLi, wherein input and output of data/command synchronous with the clock, access command supplies all address data bits (row and column) simultaneously. By acknowledging a change in bits observed between tow successive commands, regarding some of the address bits configuring an access address, the device judges whether the current access is made within the same cell array as the preceding access, between the neighboring cell arrays, or between remote cell arrays. According to the judgment, suitable command cycle is applied. At this time, the command cycle satisfies the relationship: S≧N≧F.
摘要翻译：高速时钟同步存储装置设置有由单元阵列之间和单元阵列之间共享的读出放大器S / A和单元阵列控制器单元CNTRLi，其中与时钟同步的数据/命令的输入和输出访问命令提供所有同时地址数据位（行和列）。通过确认在两个连续命令之间观察到的位的改变，关于配置访问地址的一些地址位，设备判断当前访问是在与先前的访问相同的单元阵列之间，相邻单元阵列之间，还是在远程单元阵列。根据判断，应用适当的命令循环。此时，命令循环满足关系：S> = N> = F。

2. 发明授权

US06442088B1 Semiconductor memory system, and access control method for semiconductor memory and semiconductor memory 失效
标题翻译：半导体存储器系统以及半导体存储器和半导体存储器的访问控制方法
公开(公告)号：US06442088B1
公开(公告)日：2002-08-27
申请号：US09986658
申请日：2001-11-09
申请人： Kenji Tsuchida , Haruki Toda
发明人： Kenji Tsuchida , Haruki Toda
IPC分类号： G11C700
CPC分类号： G11C11/4094 , G11C7/1072 , G11C7/12 , G11C7/22 , G11C2207/002
摘要： In a semiconductor memory system, an SDRAM comprises a memory cell array 101 which is divided into a plurality of cell array blocks, a column decoder, a row decoder, and a sense amplifier circuit. In the SDRAM, a first operation mode with a first cycle time is set when successive access within a cell array block is conducted, a second operation mode with a second cycle time shorter than the first cycle time is set when successive access covering the cell array blocks being apart from each other is conducted, and a third operation mode with a medium cycle time is set when successive access covering the cell array blocks adjacent to each other is conducted. With the above constitution, high speed access can be realized without provision of a specific accessory circuit while suppressing overhead for the semiconductor chip size.
摘要翻译：在半导体存储器系统中，SDRAM包括被分成多个单元阵列块的存储单元阵列101，列解码器，行解码器和读出放大器电路。在SDRAM中，当进行单元阵列块中的连续访问时，设置具有第一周期时间的第一操作模式，当覆盖单元阵列的连续访问时，设置具有比第一周期时间短的第二周期时间的第二操作模式进行彼此分离的块，并且进行覆盖彼此相邻的单元阵列块的连续访问时，设定具有中等周期时间的第三操作模式。利用上述结构，可以在不设置特定的附件电路的同时抑制半导体芯片尺寸的开销来实现高速访问。

3. 发明授权

US06295231B1 High-speed cycle clock-synchronous memory device 失效
标题翻译：高速循环时钟同步存储器件
公开(公告)号：US06295231B1
公开(公告)日：2001-09-25
申请号：US09354102
申请日：1999-07-15
申请人： Haruki Toda , Kenji Tsuchida , Hitoshi Kuyama
发明人： Haruki Toda , Kenji Tsuchida , Hitoshi Kuyama
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C7/1072 , G11C11/4087
摘要： A high-speed clock-synchronous memory device is provided with a sense amplifier S/A shared by and between cell arrays, and a cell array controller unit CNTRLi, wherein input and output of data/command synchronous with the clock, access command supplies all address data bits (row and column) simultaneously. By acknowledging a change in bits observed between two successive commands, regarding some of address bits configuring access address, the device judges whether the current access is made within the same cell array as the preceding access, between the neighboring cell arrays, or between remote cell arrays. According to the judgement, suitable command cycle is applied. At this time, the command cycle satisfies relationship: S≧N≧F.
摘要翻译：高速时钟同步存储装置设置有由单元阵列之间和单元阵列之间共享的读出放大器S / A和单元阵列控制器单元CNTRLi，其中与时钟同步的数据/命令的输入和输出访问命令提供所有同时地址数据位（行和列）。通过确认在两个连续命令之间观察到的位的变化，关于配置访问地址的一些地址位，设备判断当前访问是在与先前访问相同的单元阵列之间，相邻单元阵列之间还是在远程单元之间阵列根据判断，应用适当的命令循环。此时，命令循环满足关系：S> = N> = F。

4. 发明授权

US06256258B1 Semiconductor memory system, and access control method for semiconductor memory and semiconductor memory 失效
标题翻译：半导体存储器系统以及半导体存储器和半导体存储器的访问控制方法
公开(公告)号：US06256258B1
公开(公告)日：2001-07-03
申请号：US09411373
申请日：1999-10-04
申请人： Kenji Tsuchida , Haruki Toda
发明人： Kenji Tsuchida , Haruki Toda
IPC分类号： G11C800
CPC分类号： G11C11/4094 , G11C7/1072 , G11C7/12 , G11C7/22 , G11C2207/002
摘要： In a semiconductor memory system, an SDRAM comprises a memory cell array 101 which is divided into a plurality of cell array blocks, a column decoder, a row decoder, and a sense amplifier circuit. In the SDRAM, a first operation mode with a first cycle time is set when successive access within a cell array block is conducted, a second operation mode with a second cycle time shorter than the first cycle time is set when successive access covering the cell array blocks being apart from each other is conducted, and third operation mode with a medium cycle time is set when successive access covering the cell array blocks adjacent to each other is conducted. With the above constitution, a high speed access can be realized without provision of a specific accessory circuit while suppressing overhead for the semiconductor chip size.
摘要翻译：在半导体存储器系统中，SDRAM包括被分成多个单元阵列块的存储单元阵列101，列解码器，行解码器和读出放大器电路。在SDRAM中，当进行单元阵列块中的连续访问时，设置具有第一周期时间的第一操作模式，当覆盖单元阵列的连续访问时，设置具有比第一周期时间短的第二周期时间的第二操作模式进行彼此分离的块，并且进行覆盖彼此相邻的单元阵列块的连续访问时，设定具有中等周期时间的第三操作模式。利用上述结构，可以在不设置特定附件电路的同时抑制半导体芯片尺寸的开销来实现高速访问。

5. 发明授权

US06647478B2 Semiconductor memory device 失效
公开(公告)号：US06647478B2
公开(公告)日：2003-11-11
申请号：US10175085
申请日：2002-06-20
申请人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
发明人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
IPC分类号： G06F1202
CPC分类号： G11C7/22 , G11C7/1072 , G11C2207/2281 , G11C2207/229
摘要： A semiconductor memory device. The device includes a bit line, a memory cell coupled to the bit line and a word line coupled to the memory cell. A first time between the receiving of a read command for a read operation in order to read data from the memory cell and the beginning of the read operation is different from a second time between the receiving of a write command for a write operation in order to write data to the memory cell and the beginning of the write operation.

6. 发明授权

US07085881B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07085881B2
公开(公告)日：2006-08-01
申请号：US10681184
申请日：2003-10-09
申请人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
发明人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
IPC分类号： G06F12/02
CPC分类号： G11C7/22 , G11C7/1072 , G11C2207/2281 , G11C2207/229
摘要： A semiconductor memory device includes a bit line, a memory cell coupled to the bit line and a word line coupled to the memory cell. A first time between receiving a write command for a write operation in order to write data to the memory cell and the beginning of the write operation is different from a second time between receiving a refresh command for a refresh operation in order to refresh data stored in the memory cell and beginning the write operation.
摘要翻译：半导体存储器件包括位线，耦合到位线的存储单元和耦合到存储器单元的字线。为了向存储器单元写入数据和写入操作的开始，接收写入操作的写入命令之间的第一次不同于接收刷新操作的刷新命令之间的第二次，以刷新存储在存储器单元中的数据存储单元并开始写操作。

7. 发明授权

US06335904B1 Semiconductor memory system, and access control method for semiconductor memory and semiconductor memory 失效
标题翻译：半导体存储器系统以及半导体存储器和半导体存储器的访问控制方法
公开(公告)号：US06335904B1
公开(公告)日：2002-01-01
申请号：US09852037
申请日：2001-05-10
申请人： Kenji Tsuchida , Haruki Toda
发明人： Kenji Tsuchida , Haruki Toda
IPC分类号： G11C800
CPC分类号： G11C11/4094 , G11C7/1072 , G11C7/12 , G11C7/22 , G11C2207/002
摘要： In a semiconductor memory system, an SDRAM comprises a memory cell array 101 which is divided into a plurality of cell array blocks, a column decoder, a row decoder, and a sense amplifier circuit. In the SDRAM, a first operation mode with a first cycle time is set when successive access within a cell array block is conducted, a second operation mode with a second cycle time shorter than the first cycle time is set when successive access covering the cell array blocks being apart from each other is conducted and a third operation mode with a medium cycle time is set when successive access covering the cell array blocks adjacent to each other is conducted. With the above constitution, a high speed access can be realized without provision of a specific accessory circuit while suppressing overhead for a semiconductor chip size.
摘要翻译：在半导体存储器系统中，SDRAM包括被分成多个单元阵列块的存储单元阵列101，列解码器，行解码器和读出放大器电路。在SDRAM中，当进行单元阵列块中的连续访问时，设置具有第一周期时间的第一操作模式，当覆盖单元阵列的连续访问时，设置具有比第一周期时间短的第二周期时间的第二操作模式进行彼此分开的块，并且进行覆盖彼此相邻的单元阵列块的连续访问时，设定具有中等周期时间的第三操作模式。利用上述结构，可以在不设置特定附件电路的同时抑制半导体芯片尺寸的开销，实现高速访问。

8. 发明授权

US06753695B2 Semiconductor integrated circuit device and pulse width changing circuit 失效
标题翻译：半导体集成电路器件和脉冲宽度变化电路
公开(公告)号：US06753695B2
公开(公告)日：2004-06-22
申请号：US10104069
申请日：2002-03-25
申请人： Haruki Toda , Kenji Tsuchida , Satoshi Eto , Kuninori Kawabata
发明人： Haruki Toda , Kenji Tsuchida , Satoshi Eto , Kuninori Kawabata
IPC分类号： H03K3017
CPC分类号： H03K5/13 , H03K5/06 , H03K5/08
摘要： A semiconductor integrated circuit device comprises a plurality of MIS transistors, and an integrated circuit unit including logic gate circuits configured by a combination of the plurality of MIS transistors. Each of the MIS transistors has a gate including a circuit element represented by an equivalent circuit in which a capacitance and resistance are parallel-connected.
摘要翻译：半导体集成电路器件包括多个MIS晶体管，以及集成电路单元，其包括由多个MIS晶体管的组合构成的逻辑门电路。每个MIS晶体管具有包括由电容和电阻并联连接的等效电路表示的电路元件的栅极。

9. 发明授权

US06615309B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06615309B2
公开(公告)日：2003-09-02
申请号：US10337977
申请日：2003-01-08
申请人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
发明人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
IPC分类号： G06F1202
CPC分类号： G11C7/22 , G11C7/1072 , G11C2207/2281 , G11C2207/229
摘要： A semiconductor memory device. The device includes a bit line, a memory cell coupled to the bit line a word line coupled to the memory cell. A first time between the receiving of a read command for a read operation in order to read data from the memory cell and the beginning of read operation is different from a second time between the receiving of a write command for a write operation in order to write data to the memory cell and the beginning of the write operation.
摘要翻译：半导体存储器件。该设备包括位线，耦合到位线的存储单元，耦合到存储单元的字线。为了从存储单元读取数据和读取操作的开始，读取操作的读取命令的第一次与在写入操作的写入命令的接收之间的第二时间不同，以便写入数据到存储单元和写入操作的开始。

10. 发明授权

US06608514B1 Clock signal generator circuit and semiconductor integrated circuit with the same circuit 失效
标题翻译：时钟信号发生器电路和半导体集成电路具有相同的电路
公开(公告)号：US06608514B1
公开(公告)日：2003-08-19
申请号：US09511352
申请日：2000-02-23
申请人： Hironobu Akita , Katsuaki Isobe , Masaharu Wada , Kenji Tsuchida , Haruki Toda
发明人： Hironobu Akita , Katsuaki Isobe , Masaharu Wada , Kenji Tsuchida , Haruki Toda
IPC分类号： H03K300
CPC分类号： G11C7/222 , G11C7/22 , H03K5/00006 , H03K5/135
摘要： A clock signal generator circuit comprises an off-chip driver, a first clock control circuit for outputting a first internal clock signal Tu synchronizing with an external clock signal CK, a second clock control circuit for outputting a second internal clock signal Td 180° out-of-phase with the external clock signal CK, a third clock control circuit for outputting a third internal clock signal aTx1 synchronizing with the first clock signal Tu and advanced in phase by at least the signal delay time in the off-chip driver, a fourth clock control circuit for outputting a fourth internal clock signal aTx2 synchronizing with the second clock signal Td and advanced in phase by at least the signal delay time in the off-chip driver, an OR circuit to which the third and fourth internal clock signals aTx1, aTx2 are inputted and which outputs a fifth internal clock signal aTx, and a fifth clock control circuit for outputting a sixth internal clock signal Tx which is in synchronization with the fifth internal clock signal aTx outputted from the OR circuit, has twice the frequency of the external clock signal CK, and is advanced in phase by the signal delay time in the off-chip driver.
摘要翻译：时钟信号发生器电路包括片外驱动器，用于输出与外部时钟信号CK同步的第一内部时钟信号Tu的第一时钟控制电路，用于将第二内部时钟信号Td 180°输出的第二时钟控制电路，与外部时钟信号CK的同相;第三时钟控制电路，用于输出与第一时钟信号Tu同步的第三内部时钟信号aTx1并至少在芯片外驱动器中的信号延迟时间相位前进;第四时钟控制电路，时钟控制电路，用于输出与第二时钟信号Td同步的第四内部时钟信号aTx2并至少在片外驱动器中的信号延迟时间相位前进;第三和第四内部时钟信号aTx1，输入aTx2并输出第五内部时钟信号aTx，以及第五时钟控制电路，用于输出与f同步的第六内部时钟信号Tx 从OR电路输出的第四内部时钟信号aTx具有外部时钟信号CK的两倍频率，并且在片外驱动器中相位提前信号延迟时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式