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1. 发明授权

US07565477B2 Semiconductor device and method of controlling the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US07565477B2
公开(公告)日：2009-07-21
申请号：US11644031
申请日：2006-12-22
申请人： Kenji Shibata , Masahiko Okura , Kenta Kato , Mitsuhiro Nagao , Stewart Wang , Katherine Butler , Cheung Nga Tik
发明人： Kenji Shibata , Masahiko Okura , Kenta Kato , Mitsuhiro Nagao , Stewart Wang , Katherine Butler , Cheung Nga Tik
IPC分类号： G06F12/00
CPC分类号： G06F12/1433 , G06F2212/2022
摘要： A semiconductor device includes: memory regions that include non-volatile memory cells; disabling information memory units that correspond to the memory regions, each of the disabling information memory units storing first program disabling information indicating whether programming is to be disabled or enabled in each corresponding memory region; a program disabling information selection circuit that outputs second program disabling information for disabling programming in a corresponding memory region, regardless of the first program disabling information, when programming is disabled collectively in the memory regions in accordance with collective program disabling information indicating whether programming is to be disabled collectively in the memory regions, the program disabling information selection circuit outputting the first program disabling information as the second program disabling information when programming is not collectively disabled; and a program control circuit that disables or enables programming in the corresponding memory region in accordance with the second program disabling information.
摘要翻译：半导体器件包括：包括非易失性存储单元的存储器区域; 禁用与存储器区域相对应的信息存储单元，每个禁用信息存储单元存储指示是否在每个对应的存储器区域中禁用或启用编程的第一程序禁用信息; 程序禁用信息选择电路，当根据集合程序禁止信息指示是否编程是否被编程时，输出第二程序禁用信息以禁止在对应的存储器区域中的编程，而不管第一程序禁用信息在存储区域中集中禁止，程序禁止信息选择电路输出第一程序禁用信息作为编程时的第二程序禁用信息不被集中禁用; 以及程序控制电路，其根据第二程序禁止信息禁止或使得能够在对应的存储器区域中进行编程。

2. 发明申请

US20080155180A1 Semiconductor device and method of controlling the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US20080155180A1
公开(公告)日：2008-06-26
申请号：US11644031
申请日：2006-12-22
申请人： Kenji Shibata , Masahiko Okura , Kenta Kato , Mitsuhiro Nagao , Stewart Wang , Katherine Butler , Cheung Nga Tik
发明人： Kenji Shibata , Masahiko Okura , Kenta Kato , Mitsuhiro Nagao , Stewart Wang , Katherine Butler , Cheung Nga Tik
IPC分类号： G06F12/02
CPC分类号： G06F12/1433 , G06F2212/2022
摘要： A semiconductor device includes: memory regions that include non-volatile memory cells; disabling information memory units that correspond to the memory regions, each of the disabling information memory units storing first program disabling information indicating whether programming is to be disabled or enabled in each corresponding memory region; a program disabling information selection circuit that outputs second program disabling information for disabling programming in a corresponding memory region, regardless of the first program disabling information, when programming is disabled collectively in the memory regions in accordance with collective program disabling information indicating whether programming is to be disabled collectively in the memory regions, the program disabling information selection circuit outputting the first program disabling information as the second program disabling information when programming is not collectively disabled; and a program control circuit that disables or enables programming in the corresponding memory region in accordance with the second program disabling information.
摘要翻译：半导体器件包括：包括非易失性存储单元的存储器区域; 禁用与存储器区域相对应的信息存储单元，每个禁用信息存储单元存储指示是否在每个对应的存储器区域中禁用或启用编程的第一程序禁用信息; 程序禁用信息选择电路，当根据集合程序禁止信息指示是否编程是否被编程时，输出第二程序禁用信息以禁止在对应的存储器区域中的编程，而不管第一程序禁用信息在存储区域中集中禁止，程序禁止信息选择电路输出第一程序禁用信息作为编程时的第二程序禁用信息不被集中禁用; 以及程序控制电路，其根据第二程序禁止信息禁止或使得能够在对应的存储器区域中进行编程。

3. 发明申请

US20080155217A1 Semiconductor device and method of controlling the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US20080155217A1
公开(公告)日：2008-06-26
申请号：US11644161
申请日：2006-12-22
申请人： Kenta Kato , Masahiko Okura , Kenji Shibata , Mitsuhiro Nagao , Stewart Wang
发明人： Kenta Kato , Masahiko Okura , Kenji Shibata , Mitsuhiro Nagao , Stewart Wang
IPC分类号： G06F12/14
CPC分类号： G06F12/1425 , G06F2212/2022
摘要： A semiconductor device includes: a memory cell array that includes non-volatile memory cells; a first memory region and a second memory region that are located in the memory cell array, the first memory region being protected during a protecting period, the second memory region being not protected; an address change circuit that changes an address in an address space of the first memory region and the second memory region in the memory cell array, to an address in an address space of the second memory region, during the protecting period; and a control circuit that prohibits access to the first memory region, and allows access to the second region, during the protecting period.
摘要翻译：半导体器件包括：包括非易失性存储器单元的存储单元阵列; 位于所述存储单元阵列中的第一存储器区域和第二存储器区域，所述第一存储器区域在保护期间被保护，所述第二存储器区域不被保护; 在保护期间，将存储单元阵列中的第一存储器区域和第二存储器区域的地址空间中的地址改变为第二存储器区域的地址空间中的地址的地址改变电路; 以及控制电路，其在保护期间禁止对第一存储区域的访问，并允许访问第二区域。

4. 发明授权

US07574576B2 Semiconductor device and method of controlling the same 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US07574576B2
公开(公告)日：2009-08-11
申请号：US11644161
申请日：2006-12-22
申请人： Kenta Kato , Masahiko Okura , Kenji Shibata , Mitsuhiro Nagao , Stewart Wang
发明人： Kenta Kato , Masahiko Okura , Kenji Shibata , Mitsuhiro Nagao , Stewart Wang
IPC分类号： G06F12/00
CPC分类号： G06F12/1425 , G06F2212/2022
摘要： A semiconductor device includes: a memory cell array that includes non-volatile memory cells; a first memory region and a second memory region that are located in the memory cell array, the first memory region being protected during a protecting period, the second memory region being not protected; an address change circuit that changes an address in an address space of the first memory region and the second memory region in the memory cell array, to an address in an address space of the second memory region, during the protecting period; and a control circuit that prohibits access to the first memory region, and allows access to the second region, during the protecting period.
摘要翻译：半导体器件包括：包括非易失性存储器单元的存储单元阵列; 位于所述存储单元阵列中的第一存储器区域和第二存储器区域，所述第一存储器区域在保护期间被保护，所述第二存储器区域不被保护; 在保护期间，将存储单元阵列中的第一存储器区域和第二存储器区域的地址空间中的地址改变为第二存储器区域的地址空间中的地址的地址改变电路; 以及控制电路，其在保护期间禁止对第一存储区域的访问，并允许访问第二区域。

5. 发明申请

US20070033333A1 Non-volatile memory device, and control method of non-volatile memory device 有权
标题翻译：非易失性存储器件，以及非易失性存储器件的控制方法
公开(公告)号：US20070033333A1
公开(公告)日：2007-02-08
申请号：US11479387
申请日：2006-06-30
申请人： Kenta Kato , Mitsuhiro Nagao
发明人： Kenta Kato , Mitsuhiro Nagao
IPC分类号： G06F12/00
CPC分类号： G11C16/0416 , G11C16/22
摘要： In a memory cell array, aside from a normal-data storing region, a control-information storing region is also allocated, and the control-information storing region is composed of a predetermined number of control-information storing memory cells in each bit of control information, and same bit data is stored in the predetermined number of control-information storing memory cells, and the data is read out simultaneously at the time of reading out. When being read-out the control information, since data is read out simultaneously from the predetermined number of memory cells, the driving capacity of reading route when reading out is reinforced. Reading time of control information being read out at the time of turning on the power or initializing after resetting can be shortened, and the operation can be quickly transferred to normal access action.
摘要翻译：在存储单元阵列中，除了正常数据存储区域之外，还分配控制信息存储区域，并且控制信息存储区域由预定数量的控制信息组成，每个控制位存储存储单元信息和相同位数据被存储在预定数量的控制信息存储单元中，并且在读出时同时读出数据。当读出控制信息时，由于从预定数量的存储单元同时读出数据，所以读出时读取路径的驱动能力得到加强。可以缩短在开启电源或复位后的初始化时读取的控制信息的读取时间，并且可以快速地将操作转移到正常的访问动作。

6. 发明申请

US20060101301A1 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US20060101301A1
公开(公告)日：2006-05-11
申请号：US11259874
申请日：2005-10-26
申请人： Mitsuhiro Nagao , Kenta Kato
发明人： Mitsuhiro Nagao , Kenta Kato
IPC分类号： G06F1/04
CPC分类号： G11C7/20 , G11C7/24 , G11C8/08 , G11C11/417 , G11C16/20 , G11C16/225 , G11C29/028 , G11C2029/4402
摘要： The operational information read out by the read-out sense amplifier (19) is transferred via the data line DB to a volatile memory section. The volatile memory section is configured with the volatile memory section (21) having a SRAM configuration and the second volatile memory section (23) configured with latch circuits, which are respectively connected in parallel with the data line DB. The operational information, which may be provided depending on an operation state of the write-protect information and other information stored in the non-volatile memory cell MC selected by the word line WLWP, is written and read out with respect to the first volatile memory section (21) in response to the identification information linked with the operational information. The operational information which must be constantly accessible, is written into the second volatile memory section (23) in response to the identification information. Thus, the operational information is available in a memory mode depending on the attributes of the operational information.
摘要翻译：由读出放大器（19）读出的运算信息经由数据线DB传送到易失性存储器部分。易失性存储器部分配置有具有SRAM配置的易失性存储器部分（21）和配置有分别与数据线DB并联连接的锁存电路的第二易失性存储器部分（23）。可以根据写保护信息的操作状态和由字线WLWP选择的存储在非易失性存储单元MC中的其他信息提供的操作信息相对于第一易失性存储器被写入和读出部分（21）响应于与操作信息相关联的识别信息。响应于识别信息，必须始终可访问的操作信息被写入第二易失性存储器部分（23）。因此，根据操作信息的属性，操作信息以存储模式可用。

7. 发明授权

US07436715B2 Non-volatile memory device, and control method of non-volatile memory device 有权
标题翻译：非易失性存储器件，以及非易失性存储器件的控制方法
公开(公告)号：US07436715B2
公开(公告)日：2008-10-14
申请号：US11479387
申请日：2006-06-30
申请人： Kenta Kato , Mitsuhiro Nagao
发明人： Kenta Kato , Mitsuhiro Nagao
IPC分类号： G11C7/00
CPC分类号： G11C16/0416 , G11C16/22
摘要： In a memory cell array, aside from a normal-data storing region, a control-information storing region is also allocated, and the control-information storing region is composed of a predetermined number of control-information storing memory cells in each bit of control information, and same bit data is stored in the predetermined number of control-information storing memory cells, and the data is read out simultaneously at the time of reading out. When being read-out the control information, since data is read out simultaneously from the predetermined number of memory cells, the driving capacity of reading route when reading out is reinforced. Reading time of control information being read out at the time of turning on the power or initializing after resetting can be shortened, and the operation can be quickly transferred to normal access action.
摘要翻译：在存储单元阵列中，除了正常数据存储区域之外，还分配控制信息存储区域，并且控制信息存储区域由预定数量的控制信息组成，每个控制位存储存储单元信息和相同位数据被存储在预定数量的控制信息存储单元中，并且在读出时同时读出数据。当读出控制信息时，由于从预定数量的存储单元同时读出数据，所以读出时读取路径的驱动能力得到加强。可以缩短在开启电源或复位后的初始化时读取的控制信息的读取时间，并且可以快速地将操作转移到正常的访问动作。

8. 发明申请

US20060098496A1 Method and apparatus for setting operational information of a non-volatile memory 有权
标题翻译：用于设置非易失性存储器的操作信息的方法和装置
公开(公告)号：US20060098496A1
公开(公告)日：2006-05-11
申请号：US11259873
申请日：2005-10-26
申请人： Shozo Kawabata , Mitsuhiro Nagao , Kenta Kato
发明人： Shozo Kawabata , Mitsuhiro Nagao , Kenta Kato
IPC分类号： G11C7/10
CPC分类号： G11C29/02 , G11C16/102 , G11C16/20 , G11C16/3436 , G11C29/021 , G11C29/023 , G11C29/028 , G11C2029/4402
摘要： A verify sense amplifier (19) reads data from a non-volatile memory cell to be rewritten. The readout data is compared to expected data in a comparator circuit (21). Upon completion of rewriting, the comparator circuit (21) outputs a match signal MCH. A selector (23) outputs a decode signal STR(i) or SWP(i) indicative of a volatile data retaining unit (25), in correspondence with the non-volatile memory cell MC to be rewritten. According to a verify instruction signal PGV/ERV, the readout data read by the verify sense amplifier (19) is stored in the volatile data retaining unit (25). Control is performed with a match signal MCH instead of the verify instruction signal PGV/ERV, thereby storing the data in the volatile data retaining unit (25) upon completion of rewriting. Therefore, there is no need to re-read operational information from the non-volatile storage.
摘要翻译：验证读出放大器（19）从要被重写的非易失性存储器单元读取数据。读出数据与比较器电路（21）中的期望数据进行比较。在完成重写时，比较器电路（21）输出匹配信号MCH。选择器（23）对应于要重写的非易失性存储器单元MC输出指示易失性数据保持单元（25）的解码信号STR（i）或SWP（i）。根据验证指示信号PGV / ERV，将由验证读出放大器（19）读出的读出数据存储在易失性数据保持单元（25）中。通过匹配信号MCH而不是验证指令信号PGV / ERV进行控制，从而在完成重写时将数据存储在易失性数据保持单元（25）中。因此，不需要从非易失性存储器重新读取操作信息。

9. 发明授权

US08443131B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US08443131B2
公开(公告)日：2013-05-14
申请号：US11259874
申请日：2005-10-26
申请人： Mitsuhiro Nagao , Kenta Kato
发明人： Mitsuhiro Nagao , Kenta Kato
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G11C11/34 , G11C16/04 , G11C7/10
CPC分类号： G11C7/20 , G11C7/24 , G11C8/08 , G11C11/417 , G11C16/20 , G11C16/225 , G11C29/028 , G11C2029/4402
摘要： Operational information read out by a read-out sense amplifier (19) is transferred via the data line DB to a volatile memory section. The volatile memory section is configured with the volatile memory section (21) having a SRAM configuration and the second volatile memory section (23) configured with latch circuits, both sections respectively connected in parallel with the data line DB. The operational information, which may be provided depending on an operation state of the write-protect information and other information stored in the non-volatile memory cell MC selected by the word line WLWP, is written and read out with respect to the first volatile memory section (21) in response to the identification information linked with the operational information. The operational information which must be constantly accessible, is written into the second volatile memory section (23). Thus, the operational information is available in response to attributes of the operational information.
摘要翻译：由读出放大器（19）读出的操作信息经由数据线DB传送到易失性存储器部分。易失性存储器部分配置有具有SRAM配置的易失性存储器部分（21）和配置有锁存电路的第二易失性存储器部分（23），两个部分分别与数据线DB并联连接。可以根据写保护信息的操作状态和由字线WLWP选择的存储在非易失性存储单元MC中的其他信息提供的操作信息相对于第一易失性存储器被写入和读出部分（21）响应于与操作信息相关联的识别信息。必须经常访问的操作信息被写入第二易失性存储器部分（23）。因此，响应于操作信息的属性，操作信息可用。

10. 发明授权

US07120050B2 Method and apparatus for setting operational information of a non-volatile memory 有权
公开(公告)号：US07120050B2
公开(公告)日：2006-10-10
申请号：US11259873
申请日：2005-10-26
申请人： Shozo Kawabata , Mitsuhiro Nagao , Kenta Kato
发明人： Shozo Kawabata , Mitsuhiro Nagao , Kenta Kato
IPC分类号： G11C16/04
CPC分类号： G11C29/02 , G11C16/102 , G11C16/20 , G11C16/3436 , G11C29/021 , G11C29/023 , G11C29/028 , G11C2029/4402
摘要： A verify sense amplifier (19) reads data from a non-volatile memory cell to be rewritten. The readout data is compared to expected data in a comparator circuit (21). Upon completion of rewriting, the comparator circuit (21) outputs a match signal MCH. A selector (23) outputs a decode signal STR(i) or SWP(i) indicative of a volatile data retaining unit (25), in correspondence with the non-volatile memory cell MC to be rewritten. According to a verify instruction signal PGV/ERV, the readout data read by the verify sense amplifier (19) is stored in the volatile data retaining unit (25). Control is performed with a match signal MCH instead of the verify instruction signal PGV/ERV, thereby storing the data in the volatile data retaining unit (25) upon completion of rewriting. Therefore, there is no need to re-read operational information from the non-volatile storage.

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