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1. 发明授权

US07563670B2 Method for etching single-crystal semiconductor selective to amorphous/polycrystalline semiconductor and structure formed by same 有权
标题翻译：用于蚀刻对非晶/多晶半导体有选择性的单晶半导体及其结构的方法
公开(公告)号：US07563670B2
公开(公告)日：2009-07-21
申请号：US11558974
申请日：2006-11-13
申请人： Kangguo Cheng , Richard O. Henry , Kenneth T. Settlemyer, Jr.
发明人： Kangguo Cheng , Richard O. Henry , Kenneth T. Settlemyer, Jr.
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/20
CPC分类号： H01L21/32134 , H01L21/30608 , H01L27/10841 , H01L27/10864
摘要： A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor. The method then includes etching the single-crystal semiconductor sidewalls to widen the upper trench portion beyond the exposed upper surface of the semiconductor fill of the capacitor to form exposed regions of single-crystal semiconductor on a bottom portion of the upper trench adjacent to the exposed upper surface of the semiconductor fill. A trench top insulating layer is deposited on the bottom portion of the upper trench, over the upper surface of the semiconductor fill and over the adjacent regions of single-crystal semiconductor. The method then includes forming a vertical gate dielectric layer, wherein the trench top insulating layer extends below the vertical gate insulating layer.
摘要翻译：一种形成垂直DRAM装置的方法。下沟槽填充有用于电容器的多晶或非晶半导体。上沟槽部分具有暴露的单晶半导体的侧壁。该方法然后包括蚀刻单晶半导体侧壁以将上部沟槽部分加宽超过电容器的半导体填充物的暴露的上表面，以在邻近暴露的上部沟槽的上部沟槽的底部上形成单晶半导体的暴露区域半导体填料的上表面。沟槽顶部绝缘层沉积在上沟槽的底部上方，半导体填充物的上表面和相邻的单晶半导体区域之上。该方法然后包括形成垂直栅极电介质层，其中沟槽顶部绝缘层延伸到垂直栅极绝缘层下方。

2. 发明申请

US20080111175A1 METHOD FOR ETCHING SINGLE-CRYSTAL SEMICONDUCTOR SELECTIVE TO AMORPHOUS/POLYCRYSTALLINE SEMICONDUCTOR AND STRUCTURE FORMED BY SAME 有权
标题翻译：用于蚀刻单晶半导体选择性到非晶态/多晶半导体的方法和由其形成的结构
公开(公告)号：US20080111175A1
公开(公告)日：2008-05-15
申请号：US11558974
申请日：2006-11-13
申请人： Kangguo Cheng , Richard O. Henry , Kenneth T. Settlemyer
发明人： Kangguo Cheng , Richard O. Henry , Kenneth T. Settlemyer
IPC分类号： H01L27/108 , H01L21/8242 , H01L21/306
CPC分类号： H01L21/32134 , H01L21/30608 , H01L27/10841 , H01L27/10864
摘要： A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor. The method then includes etching the single-crystal semiconductor sidewalls to widen the of the upper trench portion beyond the exposed upper surface of the semiconductor fill of the capacitor to form exposed regions of single-crystal semiconductor on a bottom portion of the upper trench adjacent to the exposed upper surface of the semiconductor fill. A trench top insulating layer is deposited on the bottom portion of the upper trench, over the upper surface of the semiconductor fill and over the adjacent regions of single-crystal semiconductor. The method then includes forming a vertical gate dielectric layer, wherein the trench top insulating layer extends below the vertical gate insulating layer.
摘要翻译：一种形成垂直DRAM装置的方法。下沟槽填充有用于电容器的多晶或非晶半导体。上沟槽部分具有暴露的单晶半导体的侧壁。该方法然后包括蚀刻单晶半导体侧壁以将上部沟槽部分加宽超过电容器的半导体填充物的暴露的上表面，以在邻近上部沟槽的上部沟槽的底部上形成单晶半导体的暴露区域半导体填充物的暴露的上表面。沟槽顶部绝缘层沉积在上沟槽的底部上方，半导体填充物的上表面和相邻的单晶半导体区域上方。该方法然后包括形成垂直栅极电介质层，其中沟槽顶部绝缘层延伸到垂直栅极绝缘层下方。

3. 发明申请

US20080261128A1 Methods and structures for protecting one area while processing another area on a chip 有权
标题翻译：在处理芯片上的另一个区域时保护一个区域的方法和结构
公开(公告)号：US20080261128A1
公开(公告)日：2008-10-23
申请号：US12106586
申请日：2008-04-21
申请人： Deok-kee Kim , Kenneth T. Settlemyer , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Thimothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
发明人： Deok-kee Kim , Kenneth T. Settlemyer , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Thimothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
IPC分类号： G03F7/004 , G03F7/20
CPC分类号： H01L21/0337 , G03F7/11 , H01L21/027 , H01L21/0332 , H01L21/0334 , H01L21/0338 , H01L21/31144
摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
摘要翻译：增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。

4. 发明授权

US07497959B2 Methods and structures for protecting one area while processing another area on a chip 失效
标题翻译：在处理芯片上的另一个区域时保护一个区域的方法和结构
公开(公告)号：US07497959B2
公开(公告)日：2009-03-03
申请号：US10709514
申请日：2004-05-11
申请人： Deok-kee Kim , Kenneth T. Settlemyer, Jr. , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
发明人： Deok-kee Kim , Kenneth T. Settlemyer, Jr. , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
IPC分类号： H01B3/00 , H01L21/31 , H01L49/00
CPC分类号： H01L21/0337 , G03F7/11 , H01L21/027 , H01L21/0332 , H01L21/0334 , H01L21/0338 , H01L21/31144
摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
摘要翻译：增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。

5. 发明授权

US09059000B2 Methods and structures for protecting one area while processing another area on a chip 有权
公开(公告)号：US09059000B2
公开(公告)日：2015-06-16
申请号：US12106586
申请日：2008-04-21
申请人： Deok-kee Kim , Kenneth T. Settlemyer, Jr. , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
发明人： Deok-kee Kim , Kenneth T. Settlemyer, Jr. , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
IPC分类号： H01L21/027 , H01L21/033 , H01L21/311 , G03F7/11
CPC分类号： H01L21/0337 , G03F7/11 , H01L21/027 , H01L21/0332 , H01L21/0334 , H01L21/0338 , H01L21/31144
摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

6. 发明授权

US07138308B2 Replacement gate with TERA cap 失效
标题翻译：替换门与TERA帽
公开(公告)号：US07138308B2
公开(公告)日：2006-11-21
申请号：US10905070
申请日：2004-12-14
申请人： Kangguo Cheng , Ramachandra Divakaruni , Kenneth T. Settlemyer, Jr.
发明人： Kangguo Cheng , Ramachandra Divakaruni , Kenneth T. Settlemyer, Jr.
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/3205 , H01L21/4763 , H01L21/302
CPC分类号： H01L29/6656 , H01L29/495 , H01L29/4966 , H01L29/51 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A field effect transistor formed by a sacrificial gate process has a simplified process and improved yield by using a tunable resistant anti-reflective coating (TERA) as the cap layer over the sacrificial gate layer. The TERA layer serves as a tunable anti-reflection layer for photolithography patterning, a hardmask for etching the sacrificial gate, a polish stopping layer for planarization, and a blocking layer for preventing silicide formation over the sacrificial gate. The TERA is stripped by a two-step process that is highly selective to the nitride spacers, so that the spacers are not damaged in the process of stripping the sacrificial gate.
摘要翻译：通过牺牲栅极工艺形成的场效应晶体管通过使用可调阻抗抗反射涂层（TERA）作为牺牲栅极层上的覆盖层，具有简化的工艺和提高的产量。 TERA层用作光刻图案的可调谐抗反射层，用于蚀刻牺牲栅极的硬掩模，用于平坦化的抛光停止层，以及用于防止在牺牲栅极上形成硅化物的阻挡层。通过对氮化物间隔物具有高度选择性的两步法来剥离TERA，使得在剥离牺牲栅极的过程中间隔体不被损坏。

7. 发明授权

US08021945B2 Bottle-shaped trench capacitor with enhanced capacitance 有权
标题翻译：具有增强电容的瓶形沟槽电容器
公开(公告)号：US08021945B2
公开(公告)日：2011-09-20
申请号：US12423242
申请日：2009-04-14
申请人： Xi Li , Russell H. Arndt , Kangguo Cheng , Richard O. Henry , Jinghong H. Li
发明人： Xi Li , Russell H. Arndt , Kangguo Cheng , Richard O. Henry , Jinghong H. Li
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/1087 , H01L28/82 , Y10S438/964
摘要： In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized. At least some of the oxidized portion is removed to expose a wall of an enlarged trench, along which wall a dielectric layer and conductive material are formed in order to form a trench capacitor.
摘要翻译：根据本发明的一个方面，提供一种用于制造包括沟槽电容器的半导体芯片的方法。在这种方法中，可以通过电介质层中的开口在垂直方向上蚀刻单晶半导体区域，以形成露出单晶半导体材料的粗糙表面的沟槽。沟槽在垂直于垂直方向的第一方向上具有初始侧向尺寸。然后在晶体表面上暴露的半导体材料以结晶方向依赖的方式进行蚀刻，以在沟槽表面暴露半导体材料的多个晶面。然后可以沉积含掺杂剂的衬里以对沟槽的表面进行排列，然后升高衬底的温度以将掺杂剂从含掺杂剂的衬里驱动到与表面相邻的半导体区域中。在这样的步骤中，通常暴露在壁处的半导体材料的一部分被氧化。去除至少一些氧化部分以露出扩大的沟槽的壁，沿着该壁形成介电层和导电材料以形成沟槽电容器。

8. 发明申请

US20100258904A1 BOTTLE-SHAPED TRENCH CAPACITOR WITH ENHANCED CAPACITANCE 有权
标题翻译：具有增强电容的瓶形TRENCH电容器
公开(公告)号：US20100258904A1
公开(公告)日：2010-10-14
申请号：US12423242
申请日：2009-04-14
申请人： Xi Li , Russell H. Arndt , Kangguo Cheng , Richard O. Henry , Jinghong H. Li
发明人： Xi Li , Russell H. Arndt , Kangguo Cheng , Richard O. Henry , Jinghong H. Li
IPC分类号： H01L27/07 , H01L21/02
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/1087 , H01L28/82 , Y10S438/964
摘要： In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized. At least some of the oxidized portion is removed to expose a wall of an enlarged trench, along which wall a dielectric layer and conductive material are formed in order to form a trench capacitor.
摘要翻译：根据本发明的一个方面，提供一种用于制造包括沟槽电容器的半导体芯片的方法。在这种方法中，可以通过电介质层中的开口在垂直方向上蚀刻单晶半导体区域，以形成露出单晶半导体材料的粗糙表面的沟槽。沟槽在垂直于垂直方向的第一方向上具有初始侧向尺寸。然后在晶体表面上暴露的半导体材料以结晶方向依赖的方式进行蚀刻，以在沟槽表面暴露半导体材料的多个晶面。然后可以沉积含掺杂剂的衬里以对沟槽的表面进行排列，然后升高衬底的温度以将掺杂剂从含掺杂剂的衬里驱动到与表面相邻的半导体区域中。在这样的步骤中，通常暴露在壁处的半导体材料的一部分被氧化。去除至少一些氧化部分以露出扩大的沟槽的壁，沿着该壁形成介电层和导电材料以形成沟槽电容器。

9. 发明授权

US09080239B2 Method and apparatus for angular high density plasma chemical vapor deposition 有权
标题翻译：用于角高密度等离子体化学气相沉积的方法和装置
公开(公告)号：US09080239B2
公开(公告)日：2015-07-14
申请号：US13434934
申请日：2012-03-30
申请人： Daewon Yang , Kangguo Cheng , Pavel Smetana , Richard S. Wise , Keith Kwong Hon Wong
发明人： Daewon Yang , Kangguo Cheng , Pavel Smetana , Richard S. Wise , Keith Kwong Hon Wong
IPC分类号： C23C16/507 , C23C16/34 , C23C16/40 , C23C16/455 , C23C16/458 , C23C16/56 , H01J37/20 , H01J37/32 , H01L27/108 , H01L21/316 , H01L21/318
CPC分类号： C23C16/507 , C23C16/345 , C23C16/402 , C23C16/45578 , C23C16/4586 , C23C16/56 , H01J37/20 , H01J37/321 , H01J2237/20207 , H01J2237/3323 , H01L21/31608 , H01L21/3185 , H01L27/10867
摘要： Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.
摘要翻译：通过形成多个STI沟槽与FET结合形成浅沟槽电容器; 对于FET，在第一和第二STI沟槽之间注入具有第一极性的第一单元阱; 对于电容器，在第三个STI沟槽的区域中注入具有第二极性的第二单元阱; 从第三STI沟槽去除电介质材料; 形成具有位于所述STI沟槽的所述第一和第二STI沟槽之间的第一部分和位于所述第三沟槽中并延伸到所述第三沟槽中的第二部分的栅极堆叠; 并且执行与第二单元阱相同极性的源极/漏极注入，从而在第一单元阱中形成FET，以及在第二单元阱中形成电容器。第二极性可以与第一极性相反。额外的植入物可以减少第二细胞中的ESR。

10. 发明授权

US09059321B2 Buried channel field-effect transistors 有权
标题翻译：埋地通道场效应晶体管
公开(公告)号：US09059321B2
公开(公告)日：2015-06-16
申请号：US13470620
申请日：2012-05-14
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
IPC分类号： H01L21/338 , H01L21/84 , H01L27/12 , H01L29/66 , H01L29/10 , H01L29/786 , H01L29/78 , H01L21/8238 , H01L29/51
CPC分类号： H01L29/0642 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0692 , H01L29/1054 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/78 , H01L29/78687 , H01L29/78696
摘要： Methods for forming a buried-channel field-effect transistor include doping source and drain regions on a substrate with a dopant having a first type; forming a doped shielding layer on the substrate in a channel region having a second doping type opposite the first type to displace a conducting channel away from a gate-interface region; forming a gate dielectric over the doped shielding layer; and forming a gate on the gate dielectric.
摘要翻译：用于形成掩埋沟道场效应晶体管的方法包括在具有第一类型的掺杂剂的衬底上掺杂源区和漏区; 在具有与第一类型相反的第二掺杂类型的沟道区域中的衬底上形成掺杂的屏蔽层，以使导电沟道偏离栅极 - 界面区域; 在所述掺杂屏蔽层上形成栅极电介质; 并在栅极电介质上形成栅极。

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