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1. 发明授权

US06326270B1 Methods of forming integrated circuit memory devices using masking layers to inhibit overetching of impurity regions and conductive lines 有权
标题翻译：使用掩模层形成集成电路存储器件以抑制杂质区和导电线的过蚀刻的方法
公开(公告)号：US06326270B1
公开(公告)日：2001-12-04
申请号：US09419836
申请日：1999-10-15
申请人： Kang-Yoon Lee , Woo-Tag Kang , Jeong-Seok Kim , Yoo-Cheol Shin
发明人： Kang-Yoon Lee , Woo-Tag Kang , Jeong-Seok Kim , Yoo-Cheol Shin
IPC分类号： H01L21336
CPC分类号： H01L21/76816 , H01L21/76805 , H01L21/76897 , H01L27/10888 , H01L27/10894 , H01L27/10897
摘要： Methods of forming integrated circuit memory devices may include steps to form memory cell access transistors therein. These steps may include steps to form a gate line on a semiconductor substrate and then implant dopants of first conductivity type into the semiconductor substrate to define a self-aligned impurity region therein. A spacer layer of a first material is then formed on a sidewall and upper surface of the gate line. An interlayer insulating layer of a second material is then formed on the spacer layer. A series of selective etching steps are then performed using different etchants. For example, a step is performed to selectively etch the interlayer insulating layer to define a contact hole therein, using the spacer layer as an etching mask to protect the gate line from etching damage. A selective etching step is then performed to convert the spacer layer into a sidewall spacer on the sidewall of the gate line. This etching step is performed using the interlayer insulating layer as an etching mask. A conductive plug (e.g., bit line plug) is then formed in the contact hole. This conductive plug forms an ohmic contact with the impurity region.
摘要翻译：形成集成电路存储器件的方法可以包括在其中形成存储单元存取晶体管的步骤。这些步骤可以包括在半导体衬底上形成栅极线，然后将第一导电类型的掺杂剂注入到半导体衬底中以限定其中的自对准杂质区的步骤。然后在栅极线的侧壁和上表面上形成第一材料的间隔层。然后在间隔层上形成第二材料的层间绝缘层。然后使用不同的蚀刻剂执行一系列选择性蚀刻步骤。例如，使用间隔层作为蚀刻掩模来执行步骤以选择性地蚀刻层间绝缘层以限定其中的接触孔，以保护栅极线免受蚀刻损伤。然后执行选择性蚀刻步骤以将间隔层转换成栅极线的侧壁上的侧壁间隔物。该蚀刻步骤使用层间绝缘层作为蚀刻掩模进行。然后在接触孔中形成导电插塞（例如，位线插头）。该导电插塞与杂质区形成欧姆接触。

2. 发明授权

US5622883A Method for manufacturing semiconductor memory device having landing pad 失效
标题翻译：具有着陆垫的半导体存储器件的制造方法
公开(公告)号：US5622883A
公开(公告)日：1997-04-22
申请号：US550481
申请日：1995-10-30
申请人： Jeong-Seok Kim
发明人： Jeong-Seok Kim
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L21/76804
摘要： In manufacturing a high-integrated semiconductor memory device, there is disclosed a method for forming a trophy-shaped landing pad to a contact hole with a high aspect ratio by using a multiple-step etching process. According to the present invention, a storage node landing pad is formed by the multiple-step etching process and in different profiles via different etching processes from a bit line landing pad, thereby preventing a stringer or a bridge phenomenon occurring between the landing pads. Moreover, the trophy-shaped landing pad is formed by the multiple-step etching process, thereby securing an enough alignment margin and facilitating the manufacturing of 1 Gbit-grade DRAM by lowering the aspect ratio.
摘要翻译：在制造高集成度半导体存储器件时，公开了一种通过使用多步骤蚀刻工艺将具有高纵横比的接合孔形成奖杯状的着陆焊盘的方法。根据本发明，通过多步蚀刻工艺形成存储节点着陆焊盘，并且通过来自位线着陆焊盘的不同蚀刻工艺，在不同的轮廓中形成存储节点着陆焊盘，从而防止在着陆焊盘之间发生桁条或桥接现象。此外，通过多步骤蚀刻工艺形成奖杯形着陆板，从而确保足够的对准边缘，并通过降低纵横比来促进制造1Gbit级DRAM。

3. 发明授权

US06600187B2 Semiconductor memory device and method for manufacturing the same 失效
公开(公告)号：US06600187B2
公开(公告)日：2003-07-29
申请号：US09916736
申请日：2001-07-26
申请人： Jeong-Seok Kim
发明人： Jeong-Seok Kim
IPC分类号： H01L27108
CPC分类号： H01L27/10873 , H01L27/105 , H01L27/1052 , H01L27/10894
摘要： A technology of preventing the threshold voltage of the transistor of a cell region from increasing and the refresh characteristic of the transistor of the cell region from deteriorating, while maintaining the characteristic of the transistor of core circuit/peripheral circuit regions of a semiconductor memory device, is provided. A semiconductor memory device comprises a first transistor comprised of a first gate, a first gate insulating film, a first source region, and a first drain region formed in core circuit/peripheral circuit regions of a semiconductor memory device having a cell region and core circuit/peripheral circuit regions, a planarized interlayer dielectric film which covers the first transistor, and a second transistor formed in the cell region, including a second source region, a second drain region, a second gate having a height corresponding to the height of the interlayer dielectric film, and a second gate insulating film. The first transistor is formed using conventional manufacturing processes, the second transistor is formed by a damascene method, using the interlayer dielectric film as the basis of a reverse gate pattern.

4. 发明授权

US06314528B1 Computer for terminating power without the loss of data and a method thereof 有权
标题翻译：用于在不丢失数据的情况下终止电力的计算机及其方法
公开(公告)号：US06314528B1
公开(公告)日：2001-11-06
申请号：US09198405
申请日：1998-11-24
申请人： Jeong-Seok Kim
发明人： Jeong-Seok Kim
IPC分类号： G06F1100
CPC分类号： G06F1/26
摘要： The present invention comprises a power switch, a central processing unit, a memory, a control unit and a power supply unit. The control unit determines whether a booting operation is successfully preformed, when a power switch is turned to the off position, and then, if a booting operation has been successfully performed, outputs a control signal in order to save data and close all active programs and then turn off power. If a booting operation has not been successfully performed, the control unit outputs a control signal in order to instantly turn off power. The power supply unit turns on or off power according to a control signal from the control unit. The present invention pertains to a computer for terminating power without the loss of data and a method thereof which terminates power only after closing all active programs when the computer's power switch is moved to the off position.
摘要翻译：本发明包括电源开关，中央处理单元，存储器，控制单元和电源单元。控制单元确定是否成功执行启动操作，当电源开关转到关闭位置时，如果启动操作成功执行，则输出控制信号以保存数据并关闭所有活动程序，然后关闭电源。如果启动操作未成功执行，则控制单元输出控制信号以便立即关闭电源。电源单元根据控制单元的控制信号接通或关闭电源。本发明涉及一种用于在不丢失数据的情况下终止电力的计算机及其方法，其在计算机的电源开关移动到关闭位置之后在关闭所有活动程序之后终止电力。

5. 发明授权

US06583004B2 Semiconductor memory device and method for manufacturing the same 失效
公开(公告)号：US06583004B2
公开(公告)日：2003-06-24
申请号：US10104363
申请日：2002-03-21
申请人： Jeong-Seok Kim
发明人： Jeong-Seok Kim
IPC分类号： H01L218242
CPC分类号： H01L27/10873 , H01L27/105 , H01L27/1052 , H01L27/10894
摘要： A technology of preventing the threshold voltage of the transistor of a cell region from increasing and the refresh characteristic of the transistor of the cell region from deteriorating, while maintaining the characteristic of the transistor of core circuit/peripheral circuit regions of a semiconductor memory device, is provided. A semiconductor memory device comprises a first transistor comprised of a first gate, a first gate insulating film, a first source region, and a first drain region formed in core circuit/peripheral circuit regions of a semiconductor memory device having a cell region and core circuit/peripheral circuit regions, a planarized interlayer dielectric film which covers the first transistor, and a second transistor formed in the cell region, including a second source region, a second drain region, a second gate having a height corresponding to the height of the interlayer dielectric film, and a second gate insulating film. The first transistor is formed using conventional manufacturing processes, the second transistor is formed by a damascene method, using the interlayer dielectric film as the basis of a reverse gate pattern.

6. 发明授权

US6140223A Methods of forming contacts for integrated circuits using chemical vapor deposition and physical vapor deposition 失效
标题翻译：使用化学气相沉积和物理气相沉积形成集成电路触点的方法
公开(公告)号：US6140223A
公开(公告)日：2000-10-31
申请号：US175698
申请日：1998-10-20
申请人： Jeong-Seok Kim , Joo-Wook Park
发明人： Jeong-Seok Kim , Joo-Wook Park
IPC分类号： H01L21/28 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76846 , H01L21/76843
摘要： A thin conductive layer is formed on a contact hole bottom and on a contact hole sidewall in an insulating layer on an integrated circuit substrate, and then both chemical vapor deposition and physical vapor deposition are performed, to form a glue layer on the thin conductive layer. By performing both chemical vapor deposition and physical vapor deposition, the desirable characteristics of both processes may be obtained and the drawbacks in each of these processes may be compensated. Preferably, chemical vapor deposition of a material is performed, and physical vapor deposition of the same material is performed, to form the glue layer on the thin conductive layer. More particularly, chemical vapor deposition of titanium nitride, and physical vapor deposition of titanium nitride may be performed to form the glue layer on the thin conductive layer. As an alternative to titanium nitride, tungsten nitride may be used. After forming the glue layer, the contact hole may be filled with conductive material such as tungsten.
摘要翻译：在集成电路基板上的绝缘层的接触孔底部和接触孔侧壁上形成薄导电层，然后进行化学气相沉积和物理气相沉积，以在薄导电层上形成胶层。通过进行化学气相沉积和物理气相沉积，可以获得两种方法的期望特性，并且可以补偿这些方法中的每一种的缺陷。优选地，进行材料的化学气相沉积，并且进行相同材料的物理气相沉积，以在薄导电层上形成胶层。更具体地，可以进行氮化钛的化学气相沉积和氮化钛的物理气相沉积，以在薄导电层上形成胶层。作为氮化钛的替代方案，可以使用氮化钨。在形成胶层之后，接触孔可以用诸如钨的导电材料填充。

7. 发明授权

US5709097A Multiroom airconditioner 失效
标题翻译：多房间空调
公开(公告)号：US5709097A
公开(公告)日：1998-01-20
申请号：US773867
申请日：1996-12-27
申请人： Tae-Geun Kim , Kew-Wan Kim , Jeong-Seok Kim
发明人： Tae-Geun Kim , Kew-Wan Kim , Jeong-Seok Kim
IPC分类号： F24F11/02 , F24F3/06 , F25B1/00 , F25B5/02 , F25B6/02 , F25B41/00
CPC分类号： F24F3/065 , F25B41/00 , F25B5/02 , F25B6/02
摘要： A multiroom airconditioner includes a plurality of indoor units, each of them having an indoor heat exchanger, an outdoor unit having an outdoor heat exchanger and a device for equalizing the pressure of the refrigerant flowing from the indoor units to the outdoor unit, wherein the outdoor heat exchanger is divided into an identical number of sections as that of the indoor heat exchanger, each of the sections being connected to each of the indoor units in one to one basis.
摘要翻译：多室空调包括多个室内单元，每个室内单元具有室内热交换器，具有室外热交换器的室外单元和用于均衡从室内单元流向室外单元的制冷剂的压力的装置，其中室外热交换器被分成与室内热交换器相同数量的部分，每个部分以一对一的方式连接到每个室内单元。

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