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    • 1. 发明授权
    • Silicon-based optical modulator with improved efficiency and chirp control
    • 硅基光学调制器,提高效率和啁啾控制
    • US08520984B2
    • 2013-08-27
    • US12781471
    • 2010-05-17
    • Mark WebsterRussell RomanoKalpendu Shastri
    • Mark WebsterRussell RomanoKalpendu Shastri
    • G02F1/035
    • G02F1/2257G02F2203/20G02F2203/25
    • A silicon-based optical modulator exhibiting improved modulation efficiency and control of “chirp” (i.e., time-varying optical phase) is provided by separately biasing a selected, first region of the modulating device (e.g., the polysilicon region, defined as the common node). In particular, the common node is biased to shift the voltage swing of the silicon-based optical modulator into its accumulation region, which exhibits a larger change in phase as a function of applied voltage (larger OMA) and improved extinction ratio. The response in the accumulation region is also relatively linear, allowing for the chirp to be more easily controlled. The electrical modulation input signal (and its inverse) are applied as separate inputs to the second region (e.g., the SOI region) of each arm of the modulator.
    • 通过分别偏置调制装置的选定的第一区域(例如,定义为共同的多晶硅区域)来提供显示出改善的调制效率和“啁啾”(即,时变光学相位)的控制的硅基光学调制器 节点)。 特别地,公共节点被偏置以将硅基光调制器的电压摆幅移动到其累积区域中,其随着施加电压(较大的OMA)和改善的消光比而呈现较大的相位变化。 积聚区域中的响应也是相对线性的,从而可以更容易地控制啁啾声。 电调制输入信号(及其反相)作为分离的输入施加到调制器的每个臂的第二区域(例如,SOI区域)。
    • 6. 发明申请
    • Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits
    • 用于单片硅基光电路的设计,仿真和验证的综合方法
    • US20050289490A1
    • 2005-12-29
    • US11159283
    • 2005-06-22
    • Kalpendu ShastriSoham PathakPrakash GothoskarPaulius MosinskisBipin Dama
    • Kalpendu ShastriSoham PathakPrakash GothoskarPaulius MosinskisBipin Dama
    • G06F17/50G06G7/62
    • G06F17/5036G06F17/5068
    • Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design. The results of the co-simulation are compared to the results of the co-verification, with alterations made in the logic design and/or the physical layout until the desired operating parameters are obtained. Once the desired results are generated, conventional wafer-level fabrication operations are then considered to provide a final product (“tape out”).
    • 计算机辅助设计(CAD)工具用于在单片硅基电光芯片中执行电气和光学部件的集成设计,验证和布局。 为最终的硅基单片结构中包含的三种不同类型的元件准备了独立的顶级行为逻辑设计:(1)数字电子集成电路元件; (2)模拟/混合信号电子集成电路元件; 和(3)光电元件(包括无源和有源光学元件)。 一旦行为逻辑设计完成,结果将被合并并共同模拟。 为电路中的每种不同类型的元件开发和验证物理布局设计。 然后将单独的物理布局共同验证,以评估整体物理设计的属性。 将共模拟的结果与协同验证的结果进行比较,在逻辑设计和/或物理布局中进行改变,直到获得所需的操作参数。 一旦产生期望的结果,则常规晶圆级制造操作被认为是提供最终产品(“磁带输出”)。