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1. 发明授权

US07768106B2 Multi-chip stack structure and fabrication method thereof 有权
标题翻译：多芯片堆叠结构及其制造方法
公开(公告)号：US07768106B2
公开(公告)日：2010-08-03
申请号：US12077003
申请日：2008-03-13
申请人： Jung-Ping Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
发明人： Jung-Ping Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/50 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48496 , H01L2224/49175 , H01L2224/78 , H01L2224/85001 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00
摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
摘要翻译：提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块，以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本在制造过程中。此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

2. 发明申请

US20100255635A1 FABRICATION METHOD OF MULTI-CHIP STACK STRUCTURE 有权
标题翻译：多芯片堆叠结构的制作方法
公开(公告)号：US20100255635A1
公开(公告)日：2010-10-07
申请号：US12818701
申请日：2010-06-18
申请人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
发明人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
IPC分类号： H01L21/60
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/50 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48496 , H01L2224/49175 , H01L2224/78 , H01L2224/85001 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00
摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
摘要翻译：提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块，以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本在制造过程中。此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

3. 发明申请

US20080224289A1 Multi-chip stack structure and fabrication method thereof 有权
标题翻译：多芯片堆叠结构及其制造方法
公开(公告)号：US20080224289A1
公开(公告)日：2008-09-18
申请号：US12077003
申请日：2008-03-13
申请人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
发明人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/50 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48496 , H01L2224/49175 , H01L2224/78 , H01L2224/85001 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00
摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
摘要翻译：提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块，以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本在制造过程中。此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

4. 发明授权

US07981729B2 Fabrication method of multi-chip stack structure 有权
标题翻译：多芯片堆叠结构的制作方法
公开(公告)号：US07981729B2
公开(公告)日：2011-07-19
申请号：US12818701
申请日：2010-06-18
申请人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
发明人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
IPC分类号： H01L21/60
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/50 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48496 , H01L2224/49175 , H01L2224/78 , H01L2224/85001 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00
摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
摘要翻译：提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块，以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本在制造过程中。此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

5. 发明申请

US20090014860A1 Multi-chip stack structure and fabricating method thereof 审中-公开
标题翻译：多芯片堆叠结构及其制造方法
公开(公告)号：US20090014860A1
公开(公告)日：2009-01-15
申请号：US12011832
申请日：2008-01-29
申请人： Chung-Lun Liu , Jung-Pin Huang , Chin-Huang Chang , Chih-Ming Huang , Cheng-Hsu Hsiao
发明人： Chung-Lun Liu , Jung-Pin Huang , Chin-Huang Chang , Chih-Ming Huang , Cheng-Hsu Hsiao
IPC分类号： H01L21/00 , H01L23/02
CPC分类号： H01L25/0652 , H01L25/18 , H01L2224/32145 , H01L2224/48227 , H01L2224/73215 , H01L2224/73265 , H01L2224/92247 , H01L2225/06562 , H01L2924/00012
摘要： A multi-chip stack structure and a manufacturing method thereof are provided. The fabrication method includes the steps of: providing a chip carrier having a first surface and a second surface opposing thereto and at least a first chip and a second chip mounted on the first surface; electrically connecting the chips to the chip carrier by a plurality of bonding wires; and stacking at least a third chip on the first and second chips by a film deposed therebetween, wherein the third chip is stepwise stacked on the first chip and at least a part of the bonding wire connected to the second chip is covered by the film, and electrically connecting the third chip and the chip carrier by a bonding wire, thereby enabling a plurality of chips to be stacked on the chip carrier to enhance the electrical performance of electronic products.
摘要翻译：提供了一种多芯片堆叠结构及其制造方法。该制造方法包括以下步骤：提供具有与其相对的第一表面和第二表面的芯片载体和至少安装在第一表面上的第一芯片和第二芯片; 通过多个接合线将芯片电连接到芯片载体上; 并且通过其间放置的膜将第一和第二芯片上的至少第三芯片堆叠起来，其中第三芯片逐步堆叠在第一芯片上，并且连接到第二芯片的键合线的至少一部分被膜覆盖，并通过接合线电连接第三芯片和芯片载体，从而能够将多个芯片堆叠在芯片载体上，以增强电子产品的电气性能。

6. 发明申请

US20090057799A1 Sensor semiconductor device and method for fabricating the same 审中-公开
标题翻译：传感器半导体器件及其制造方法
公开(公告)号：US20090057799A1
公开(公告)日：2009-03-05
申请号：US12229651
申请日：2008-08-26
申请人： Chang-Yueh Chan , Chih-Ming Huang , Chien-Ping Huang , Chin-Huang Chang , Cheng-Hsu Hsiao
发明人： Chang-Yueh Chan , Chih-Ming Huang , Chien-Ping Huang , Chin-Huang Chang , Cheng-Hsu Hsiao
IPC分类号： H01L31/00 , H01L21/00
CPC分类号： H01L31/0203 , H01L31/02164 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/1815 , H01L2924/00014 , H01L2924/00
摘要： A sensor semiconductor device and a method for fabricating the same are provided. At least one sensor chip is mounted and electrically connected to a lead frame. A first and a second encapsulation molding processes are sequentially performed to form a transparent encapsulant for encapsulating the sensor chip and a part of the lead frame and to form a light-impervious encapsulant for encapsulating the transparent encapsulant. The transparent encapsulant has a light-pervious portion formed at a position corresponding to and above a sensor zone of the sensor chip. The light-pervious portion is exposed from the light-impervious encapsulant. Light may penetrate the light-pervious portion, without using an additional cover board, thereby reducing manufacturing steps and costs. The above arrangement avoids prior-art problems of poor reliability caused by a porous encapsulant and poor signal reception caused by interference of ambient light entering into a conventional chip only encapsulated by a transparent encapsulant.
摘要翻译：提供一种传感器半导体器件及其制造方法。至少一个传感器芯片被安装并电连接到引线框架。依次执行第一和第二封装成型工艺以形成用于封装传感器芯片和引线框架的一部分的透明密封剂，并形成用于封装透明密封剂的不透光密封剂。透明密封剂具有形成在对应于传感器芯片的传感器区域上方的位置处的透光部分。透光部分从不透光的密封剂暴露出来。光可以穿透透光部分，而不使用附加的盖板，从而减少制造步骤和成本。上述布置避免了由多孔密封剂引起的可靠性差的现有技术问题，以及由仅通过透明密封剂封装的传统芯片的环境光的干扰引起的差信号接收。

7. 发明申请

US20080258306A1 Semiconductor Device and Method for Fabricating the Same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080258306A1
公开(公告)日：2008-10-23
申请号：US12105538
申请日：2008-04-18
申请人： Chin-Huang Chang , Chien-Ping Huang , Chih-Ming Huang , Cheng-Hsu Hsiao , Cheng-Chia Chiang
发明人： Chin-Huang Chang , Chien-Ping Huang , Chih-Ming Huang , Cheng-Hsu Hsiao , Cheng-Chia Chiang
IPC分类号： H01L23/538 , H01L21/56
CPC分类号： H01L23/3114 , H01L21/6835 , H01L23/3135 , H01L23/3185 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/02371 , H01L2224/04105 , H01L2224/05001 , H01L2224/05008 , H01L2224/05023 , H01L2224/05026 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05184 , H01L2224/05548 , H01L2224/05569 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05684 , H01L2224/12105 , H01L2224/16145 , H01L2224/48091 , H01L2224/82001 , H01L2224/97 , H01L2225/06562 , H01L2225/1058 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2224/82 , H01L2924/01028 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a chip having an active surface and an opposing non-active surface, wherein a plurality of bond pads are formed on the active surface, and first metal layers are formed on the bond pads and to edges of the non-active surface; conductive traces disposed on the non-active surface of the chip; a dielectric layer covering sides of the chip and formed with a plurality of openings therein to expose a portion of the conductive traces; and a plurality of second metal layers formed in the openings of the dielectric layer and on the first metal layers, such that the bond pads are electrically connected to the conductive traces via the first and second metal layers.
摘要翻译：本发明提供一种半导体器件及其制造方法。半导体器件包括具有活性表面和相对的非活性表面的芯片，其中在有源表面上形成多个接合焊盘，并且第一金属层形成在接合焊盘和非活性表面的边缘上 ; 布置在芯片的非有源表面上的导电迹线; 介电层，其覆盖所述芯片的侧面并在其中形成有多个开口以暴露所述导电迹线的一部分; 以及多个第二金属层，形成在电介质层的开口中和第一金属层上，使得接合焊盘经由第一和第二金属层电连接到导电迹线。

8. 发明申请

US20080251937A1 Stackable semiconductor device and manufacturing method thereof 审中-公开
标题翻译：可堆叠半导体器件及其制造方法
公开(公告)号：US20080251937A1
公开(公告)日：2008-10-16
申请号：US12082724
申请日：2008-04-11
申请人： Chin-Huang Chang , Chien-Ping Huang , Chih-Ming Huang , Cheng-Hsu Hsiao
发明人： Chin-Huang Chang , Chien-Ping Huang , Chih-Ming Huang , Cheng-Hsu Hsiao
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L21/76898 , H01L25/0657 , H01L2224/48091 , H01L2225/06513 , H01L2225/06551 , H01L2225/06562 , H01L2924/00014
摘要： A stackable semiconductor device and a manufacturing method thereof are disclosed. The method includes providing a wafer comprised of a plurality of chips, wherein a plurality of solder pads are formed on the active surface of each chip, and a plurality of grooves are formed between the solder pads of any two adjacent ones of the chips; forming a dielectric layer on regions between the solder pads of any two adjacent ones of the chips ; forming a metal layer on the dielectric layer electrically connected to the solder pads and forming a connective layer on the metal layer, wherein the width of the connective layer is smaller than that of the metal layer; cutting along the grooves to break off the electrical connection between adjacent chips; thinning the non-active surface of the wafer to the extent that the metal layer is exposed from the wafer; and separating the chips to form a plurality of stackable semiconductor devices. Accordingly, a multi-chip stack structure can be obtained by stacking and electrically connecting a plurality of semiconductor devices through the electrical connection between the connective layer of a semiconductor device and the metal layer of another semiconductor device, thereby effectively integrating more chips without having to increase the stacking area, and further the problems of poor electrical connection, complicated manufacturing processes and high costs known in the prior art can be avoided.
摘要翻译：公开了一种可堆叠半导体器件及其制造方法。该方法包括提供由多个芯片组成的晶片，其中在每个芯片的有源表面上形成多个焊盘，并且在任何两个相邻芯片的焊盘之间形成多个沟槽; 在任何两个相邻芯片的焊盘之间的区域上形成电介质层; 在与所述焊料焊盘电连接的所述电介质层上形成金属层，并在所述金属层上形成连接层，其中所述连接层的宽度小于所述金属层的宽度; 沿着凹槽切割以破坏相邻芯片之间的电连接; 使晶片的非活性表面变薄至金属层从晶片露出的程度; 并分离所述芯片以形成多个可堆叠半导体器件。因此，通过半导体器件的连接层与另一半导体器件的金属层之间的电连接层叠并电连接多个半导体器件，可以获得多芯片堆叠结构，从而有效地集成更多的芯片，而不必增加堆积面积，进一步避免了现有技术中已知的电连接不良，制造工艺复杂，成本高的问题。

9. 发明申请

US20080283994A1 Stacked package structure and fabrication method thereof 审中-公开
标题翻译：堆叠封装结构及其制造方法
公开(公告)号：US20080283994A1
公开(公告)日：2008-11-20
申请号：US12152687
申请日：2008-05-16
申请人： Ho-Yi Tsai , Chien-Ping Huang , Jung-Pin Huang , Chin-Huang Chang , Cheng-Hsu Hsiao
发明人： Ho-Yi Tsai , Chien-Ping Huang , Jung-Pin Huang , Chin-Huang Chang , Cheng-Hsu Hsiao
IPC分类号： H01L23/49 , H01L21/56
CPC分类号： H01L23/49816 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/1134 , H01L2224/1308 , H01L2224/1411 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/15174 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H05K3/3436 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stacked package structure and fabrication method thereof are disclosed, including providing a substrate having a plurality of stackable solder pads formed on surface thereof for allowing at least one semiconductor chip to be electrically connected to the substrate; forming an encapsulant for encapsulating the semiconductor chip and further exposing the stackable solder pads from the encapsulant, thus forming a lower-layer semiconductor package; forming conductive bumps on at least one stackable solder pad by means of wire bonding such that at least one upper-layer semiconductor package can be mounted via solder balls on the conductive bumps and the stackable solder pads of the lower-layer semiconductor package to form a stacked package structure, wherein, stacking height of the solder balls and the conductive bumps is greater than height of the encapsulant of the lower-layer semiconductor package, thus, when stacking fine pitch semiconductor packages or when warps occur to the upper-layer semiconductor package or the lower-layer semiconductor package, the conductive bumps can compensate for inadequate height caused by solder ball collapse or fill up gaps between the solder balls and the stackable solder pads caused by warps, thereby allowing the solder balls to be able to effectively contact and wet on the substrate of the lower-layer semiconductor package.
摘要翻译：公开了一种堆叠封装结构及其制造方法，包括提供一种具有形成在其表面上的多个可叠置焊料焊盘的衬底，用于允许至少一个半导体芯片电连接到衬底; 形成用于封装半导体芯片的密封剂，并进一步从可密封剂暴露可堆叠的焊盘，从而形成下层半导体封装; 通过引线接合在至少一个可堆叠的焊盘上形成导电凸块，使得至少一个上层半导体封装可以经由焊球安装在导电凸块和下层半导体封装的可堆叠焊盘上，以形成堆叠的封装结构，其中，焊球和导电凸块的堆叠高度大于下层半导体封装的密封剂的高度，因此，当堆叠精细间距半导体封装时或当上行半导体封装发生翘曲时或下层半导体封装，导电凸块可以补偿由焊球塌陷引起的不适当的高度，或填充由经线引起的焊球和可堆叠焊盘之间的间隙，从而允许焊球能够有效地接触和在下层半导体封装的衬底上湿润。

10. 发明申请

US20090261476A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090261476A1
公开(公告)日：2009-10-22
申请号：US12148319
申请日：2008-04-18
申请人： Chien-Ping Huang , Chin-Huang Chang , Chih-Ming Huang , Cheng-Hsu Hsiao , Chun-Chi Ke
发明人： Chien-Ping Huang , Chin-Huang Chang , Chih-Ming Huang , Cheng-Hsu Hsiao , Chun-Chi Ke
IPC分类号： H01L23/482 , H01L21/60
CPC分类号： H01L24/19 , H01L21/6835 , H01L23/3114 , H01L24/24 , H01L24/82 , H01L25/105 , H01L2221/68345 , H01L2224/24226 , H01L2224/82001 , H01L2225/1035 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311
摘要： A semiconductor device and a manufacturing method thereof are disclosed. The method includes the steps of providing a carrier board having conductive circuits disposed thereon and a plurality of chips with active surfaces having solder pads disposed thereon, wherein conductive bumps are disposed on the solder pads; mounting chips on the carrier board; filling the spacing between the chips with a dielectric layer and forming openings in the dielectric layer at periphery of each chip to expose the conductive circuits; forming a metal layer in the openings of the dielectric layer and at periphery of the active surface of the chips for electrically connecting the conductive bumps and the conductive circuits; and cutting along the dielectric layer between the chips and removing the carrier board to separate each chip and exposing the conductive circuits from the non-active surface.
摘要翻译：公开了一种半导体器件及其制造方法。该方法包括以下步骤：提供具有布置在其上的导电电路的载体板和具有设置在其上的焊料焊盘的有源表面的多个芯片，其中导电凸块设置在焊盘上; 将芯片安装在载板上; 用电介质层填充芯片之间的间隔，并在每个芯片周边的电介质层中形成开口以露出导电电路; 在所述电介质层的开口部和所述芯片的有源面的外围形成金属层，用于电连接所述导电凸块和所述导电电路; 并沿着芯片之间的电介质层切割并去除载体板以分离每个芯片并使导电电路与非活性表面相接触。

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