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1. 发明申请

US20070284654A1 METAL ALLOY LAYER OVER CONDUCTIVE REGION OF TRANSISTOR DEVICE OF DIFFERENT CONDUCTIVE MATERIAL THAN CONDUCTIVE REGION 审中-公开
标题翻译：不同导电材料与导电区域的晶体管器件导电区域的金属合金层
公开(公告)号：US20070284654A1
公开(公告)日：2007-12-13
申请号：US11422965
申请日：2006-06-08
申请人： Judith M. Rubino , James Pan , Dinkar Singh , Jonathan Smith , Anna Topol
发明人： Judith M. Rubino , James Pan , Dinkar Singh , Jonathan Smith , Anna Topol
IPC分类号： H01L29/76
CPC分类号： H01L29/78 , H01L29/7845
摘要： A transistor device and method are disclosed for reducing parasitic resistance and enhancing channel mobility using a metal alloy layer over a conductive region. A transistor device may include a conductive region such as a source, drain and/or gate including at least one first conductive material, and a metal alloy layer disposed on substantially all of a surface of the conductive region, the metal alloy layer including a second conductive material different than the at least one first conductive materials. In one embodiment, the second conductive material includes a cobalt and/or nickel alloy. The metal alloy layer provides a non-epitaxial raised source/drain (and gate) to reduce the parasitic series resistance in, for example, nFETs fabricated on UTSOI. In addition, the metal alloy layer may include a stress to enhance mobility in a channel of the transistor device. The metal alloy layer may be formed using a selective electrochemical metal deposition process such as electroless or electrolytic plating.
摘要翻译：公开了一种晶体管器件和方法，用于在导电区域上使用金属合金层降低寄生电阻并增强沟道迁移率。晶体管器件可以包括导电区域，例如包括至少一个第一导电材料的源极，漏极和/或栅极以及设置在导电区域的基本上所有表面上的金属合金层，金属合金层包括第二导电区域导电材料不同于至少一种第一导电材料。在一个实施例中，第二导电材料包括钴和/或镍合金。金属合金层提供非外延凸起的源极/漏极（和栅极），以减少例如在UTSOI上制造的nFET的寄生串联电阻。此外，金属合金层可以包括提高晶体管器件的沟道中的迁移率的应力。可以使用诸如无电镀或电解电镀的选择性电化学金属沉积工艺来形成金属合金层。

2. 发明授权

US07407605B2 Manufacturable CoWP metal cap process for copper interconnects 有权
标题翻译：用于铜互连的可制造的CoWP金属帽工艺
公开(公告)号：US07407605B2
公开(公告)日：2008-08-05
申请号：US11751788
申请日：2007-05-22
申请人： Darryl D. Restaino , Donald F. Canaperi , Judith M. Rubino , Sean P. E. Smith , Richard O. Henry , James E. Fluegel , Mahadevaiyer Krishnan
发明人： Darryl D. Restaino , Donald F. Canaperi , Judith M. Rubino , Sean P. E. Smith , Richard O. Henry , James E. Fluegel , Mahadevaiyer Krishnan
IPC分类号： H01B1/00
CPC分类号： H01L21/288 , C23C18/1241 , C23C18/1607 , C23C18/1608 , C23C18/1844 , C23C18/50 , H01L21/76849 , H01L21/76874 , H05K3/244 , H05K2203/0716 , H05K2203/072
摘要： An aqueous seeding solution of palladium acetate, acetic acid and chloride.
摘要翻译：乙酸钯，乙酸和氯化钠的水溶液接种溶液。

3. 发明授权

US07064064B2 Copper recess process with application to selective capping and electroless plating 有权
标题翻译：铜凹槽工艺，适用于选择性封盖和无电镀
公开(公告)号：US07064064B2
公开(公告)日：2006-06-20
申请号：US11058783
申请日：2005-02-16
申请人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
发明人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76847 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.
摘要翻译：公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

4. 发明授权

US06457234B1 Process for manufacturing self-aligned corrosion stop for copper C4 and wirebond 有权
标题翻译：用于制造铜C4和引线键的自对准防腐蚀工艺
公开(公告)号：US06457234B1
公开(公告)日：2002-10-01
申请号：US09311973
申请日：1999-05-14
申请人： Daniel C. Edelstein , Judith M. Rubino , Carlos J. Sambucetti , Anthony K. Stamper
发明人： Daniel C. Edelstein , Judith M. Rubino , Carlos J. Sambucetti , Anthony K. Stamper
IPC分类号： H01R900
CPC分类号： H01L24/48 , H01L21/288 , H01L21/32134 , H01L21/4846 , H01L21/76886 , H01L23/498 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/45 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05016 , H01L2224/05073 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05184 , H01L2224/05556 , H01L2224/05558 , H01L2224/05572 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48453 , H01L2224/48463 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/48755 , H01L2224/48764 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01049 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H05K3/244 , Y10T29/49117 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917 , H01L2924/00014 , H01L2924/00 , H01L2224/48744 , H01L2224/05552
摘要： A self-aligned (i.e., spatially selective) process for fabricating a corrosion-resistant conductive pad on a substrate, and an associated structure that includes an interconnect to allow a terminal connection to the conductive pad (e.g., a chip-to-package connection). The conductive pad may include a metal such as copper, aluminum, or tungsten. The self-aligned process generates a metallic layer on an initially exposed metal layer, wherein the metallic layer is electrically conductive and corrosion resistant. The process may be accomplished by providing a substrate having a metal layer with an exposed surface, depositing a second metal layer on the exposed surface, annealing the substrate to alloy a portion of the metal layer that includes the exposed surface and a portion of the second metal layer, and removing the unalloyed portion of the second metal layer.
摘要翻译：用于在衬底上制造耐腐蚀导电焊盘的自对准（即，空间选择性）工艺以及包括允许端子连接到导电焊盘的互连的相关结构（例如，芯片到封装的连接）。导电焊盘可以包括诸如铜，铝或钨的金属。自对准工艺在初始暴露的金属层上产生金属层，其中金属层是导电的和耐腐蚀的。该方法可以通过提供具有暴露表面的金属层的基底，在暴露的表面上沉积第二金属层，退火基底以使包含暴露表面的金属层的一部分和第二金属层的一部分金属层，并且去除第二金属层的非合金部分。

5. 发明授权

US07468320B2 Reduced electromigration and stressed induced migration of copper wires by surface coating 有权
标题翻译：通过表面涂层减少电迁移和应力诱导的铜线迁移
公开(公告)号：US07468320B2
公开(公告)日：2008-12-23
申请号：US11183773
申请日：2005-07-19
申请人： Chao-Kun Hu , Robert Rosenberg , Judith M. Rubino , Carlos J. Sambucetti , Anthony K. Stamper
发明人： Chao-Kun Hu , Robert Rosenberg , Judith M. Rubino , Carlos J. Sambucetti , Anthony K. Stamper
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76849 , H01L21/76864 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing. We have used electroless metal coatings, such as CoWP, CoSnP and Pd, to illustrate significant reliability benefits, although chemical vapor deposition (CVD) of metals or metal forming compounds can be employed.
摘要翻译：本发明的想法是在沉积层间电介质之前，通过1-20nm厚的金属层将芯片上互连（BEOL）布线中的图案化Cu导线的自由表面涂覆。该涂层足够薄，以便消除对通过抛光进行附加平面化的需要，同时提供了防止氧化和表面或Cu的扩散的保护，这已经被本发明人鉴定为导致金属线路故障的主要贡献者通过电迁移和热压力消除。此外，金属层增加了Cu和电介质之间的粘合强度，从而进一步增加寿命并且有助于工艺产量。自由表面是在镶嵌工艺中的CMP（化学机械抛光）或通过图形化Cu布线的干蚀刻工艺的直接结果。提出通过选择性方法将金属覆盖层沉积到Cu上以最小化进一步的加工。尽管可以使用金属或金属形成化合物的化学气相沉积（CVD），但我们已经使用了无电金属涂层，例如CoWP，CoSnP和Pd来说明显着的可靠性优点。

6. 发明授权

US07259025B2 Ferromagnetic liner for conductive lines of magnetic memory cells 有权
标题翻译：磁记忆体导电线的铁磁衬垫
公开(公告)号：US07259025B2
公开(公告)日：2007-08-21
申请号：US11644792
申请日：2006-12-22
申请人： Rainer Leuschner , Michael C. Gaidis , Judith M. Rubino , Lubomyr Taras Romankiw
发明人： Rainer Leuschner , Michael C. Gaidis , Judith M. Rubino , Lubomyr Taras Romankiw
IPC分类号： H01L21/00
CPC分类号： H01L21/76852 , H01L21/76873 , H01L21/76874 , H01L21/76885 , H01L27/228 , H01L43/12
摘要： A method of forming a ferromagnetic liner on conductive lines of magnetic memory devices and a structure thereof. The ferromagnetic liner increases the flux concentration of current run through the conductive lines, reducing the amount of write current needed to switch magnetic memory cells. The conductive lines are formed in a plate-up method, and the ferromagnetic liner is selectively formed on the plated conductive lines. The ferromagnetic liner may also be formed over conductive lines and a top portion of vias in a peripheral region of the workpiece.
摘要翻译：一种在磁存储器件的导线上形成铁磁衬垫的方法及其结构。铁磁衬垫增加了通过导线延伸的电流的通量浓度，从而减少了切换磁存储单元所需的写入电流。导电线以平板化方式形成，并且铁电衬里选择性地形成在镀覆的导电线上。铁磁衬垫也可以形成在工件的外围区域中的导电线和通孔的顶部上。

7. 发明授权

US07253106B2 Manufacturable CoWP metal cap process for copper interconnects 有权
标题翻译：用于铜互连的可制造的CoWP金属帽工艺
公开(公告)号：US07253106B2
公开(公告)日：2007-08-07
申请号：US10905230
申请日：2004-12-22
申请人： Darryl D. Restaino , Donald F. Canaperi , Judith M. Rubino , Sean P. E. Smith , Richard O. Henry , James E. Fluegel , Mahadevaiyer Krishnan
发明人： Darryl D. Restaino , Donald F. Canaperi , Judith M. Rubino , Sean P. E. Smith , Richard O. Henry , James E. Fluegel , Mahadevaiyer Krishnan
IPC分类号： H01L21/44
CPC分类号： H01L21/288 , C23C18/1241 , C23C18/1607 , C23C18/1608 , C23C18/1844 , C23C18/50 , H01L21/76849 , H01L21/76874 , H05K3/244 , H05K2203/0716 , H05K2203/072
摘要： A method to electrolessly plate a CoWP alloy on copper in a reproducible manner that is effective for a manufacturable process. In the method, a seed layer of palladium (Pd) is deposited on the copper by an aqueous seeding solution of palladium acetate, acetic acid and chloride. Thereafter, a complexing solution is applied to remove any Pd ions which are adsorbed on surfaces other than the copper. Finally, a plating solution of cobalt (Co), tungsten (W) and phosphorous (P) is applied to the copper so as to deposit a layer of CoWP on the Pd seed and copper.
摘要翻译：一种以可再生的方式对铜上的CoWP合金进行无电镀的方法，该方法对于可制造的工艺是有效的。在该方法中，通过乙酸钯，乙酸和氯化物的水性接种溶液将铜（Pd）种子层沉积在铜上。此后，应用络合溶液以除去吸附在除铜之外的表面上的任何Pd离子。最后，将铜（Co），钨（W）和磷（P）的电镀溶液施加到铜上，以便在Pd种子和铜上沉积CoWP层。

8. 发明授权

US07193323B2 Electroplated CoWP composite structures as copper barrier layers 有权
标题翻译：电镀CoWP复合结构作为铜阻挡层
公开(公告)号：US07193323B2
公开(公告)日：2007-03-20
申请号：US10714966
申请日：2003-11-18
申请人： Cyril Cabral, Jr. , Stefanie R. Chiras , Emanuel Cooper , Hariklia Deligianni , Andrew J. Kellock , Judith M. Rubino , Roger Y. Tsai
发明人： Cyril Cabral, Jr. , Stefanie R. Chiras , Emanuel Cooper , Hariklia Deligianni , Andrew J. Kellock , Judith M. Rubino , Roger Y. Tsai
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/2885 , C25D9/08 , H01L21/76838 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/76877 , H01L23/53238 , H01L2224/05007
摘要： A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a method of making an interconnect structure comprising: providing a trench or via within a dielectric material, and a conducting metal containing copper within the trench or the via; and forming a CoWP film by electrodeposition on the copper layer. The CoWP film contains from 10 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a interconnect structure comprising a dielectric layer in contact with a metal layer; an electrodeposited CoWP film on the metal layer, and a copper layer on the CoWP film.
摘要翻译：一种复合材料，其包含含有铜的层和在铜层上的电沉积CoWP膜。 CoWP膜含有11原子％至25原子％的磷并具有5nm至200nm的厚度。本发明还涉及一种制造互连结构的方法，包括：在介电材料内提供沟槽或通孔，以及在沟槽或通孔内容纳铜的导电金属; 并通过电沉积在铜层上形成CoWP膜。 CoWP膜含有10原子％至25原子％的磷，并且具有5nm至200nm的厚度。本发明还涉及包括与金属层接触的电介质层的互连结构; 金属层上的电沉积CoWP膜，CoWP膜上的铜层。

9. 发明授权

US07081680B2 Self-aligned corrosion stop for copper C4 and wirebond 有权
标题翻译：用于铜C4和引线键的自对准腐蚀停止
公开(公告)号：US07081680B2
公开(公告)日：2006-07-25
申请号：US10849459
申请日：2004-05-19
申请人： Daniel C. Edelstein , Anthony K. Stamper , Judith M. Rubino , Carlos J. Sambucetti
发明人： Daniel C. Edelstein , Anthony K. Stamper , Judith M. Rubino , Carlos J. Sambucetti
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/48 , H01L21/288 , H01L21/32134 , H01L21/4846 , H01L21/76886 , H01L23/498 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/45 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05016 , H01L2224/05073 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05184 , H01L2224/05556 , H01L2224/05558 , H01L2224/05572 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48453 , H01L2224/48463 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/48755 , H01L2224/48764 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01049 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H05K3/244 , Y10T29/49117 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917 , H01L2924/00014 , H01L2924/00 , H01L2224/48744 , H01L2224/05552
摘要： An electrical structure including a substrate and an interconnect. The substrate includes an electrically conductive and corrosion resistant metallic layer on a metal layer. The interconnect is electrically coupled to the metallic layer. A top surface of the metallic layer is above a top surface of the substrate and a bottom surface of the metallic layer is in direct mechanical contact with a first portion of a top surface of the metal layer. The metal layer is unalloyed and includes a metal.
摘要翻译：包括衬底和互连的电结构。衬底包括在金属层上的导电且耐腐蚀的金属层。互连电耦合到金属层。金属层的顶表面位于衬底的顶表面之上，并且金属层的底表面与金属层的顶表面的第一部分直接机械接触。金属层是非合金的并且包括金属。

10. 发明授权

US06975032B2 Copper recess process with application to selective capping and electroless plating 有权
公开(公告)号：US06975032B2
公开(公告)日：2005-12-13
申请号：US10319967
申请日：2002-12-16
申请人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
发明人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
IPC分类号： H01L21/768 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76847 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

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