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1. 发明申请

US20070284654A1 METAL ALLOY LAYER OVER CONDUCTIVE REGION OF TRANSISTOR DEVICE OF DIFFERENT CONDUCTIVE MATERIAL THAN CONDUCTIVE REGION 审中-公开
标题翻译：不同导电材料与导电区域的晶体管器件导电区域的金属合金层
公开(公告)号：US20070284654A1
公开(公告)日：2007-12-13
申请号：US11422965
申请日：2006-06-08
申请人： Judith M. Rubino , James Pan , Dinkar Singh , Jonathan Smith , Anna Topol
发明人： Judith M. Rubino , James Pan , Dinkar Singh , Jonathan Smith , Anna Topol
IPC分类号： H01L29/76
CPC分类号： H01L29/78 , H01L29/7845
摘要： A transistor device and method are disclosed for reducing parasitic resistance and enhancing channel mobility using a metal alloy layer over a conductive region. A transistor device may include a conductive region such as a source, drain and/or gate including at least one first conductive material, and a metal alloy layer disposed on substantially all of a surface of the conductive region, the metal alloy layer including a second conductive material different than the at least one first conductive materials. In one embodiment, the second conductive material includes a cobalt and/or nickel alloy. The metal alloy layer provides a non-epitaxial raised source/drain (and gate) to reduce the parasitic series resistance in, for example, nFETs fabricated on UTSOI. In addition, the metal alloy layer may include a stress to enhance mobility in a channel of the transistor device. The metal alloy layer may be formed using a selective electrochemical metal deposition process such as electroless or electrolytic plating.
摘要翻译：公开了一种晶体管器件和方法，用于在导电区域上使用金属合金层降低寄生电阻并增强沟道迁移率。晶体管器件可以包括导电区域，例如包括至少一个第一导电材料的源极，漏极和/或栅极以及设置在导电区域的基本上所有表面上的金属合金层，金属合金层包括第二导电区域导电材料不同于至少一种第一导电材料。在一个实施例中，第二导电材料包括钴和/或镍合金。金属合金层提供非外延凸起的源极/漏极（和栅极），以减少例如在UTSOI上制造的nFET的寄生串联电阻。此外，金属合金层可以包括提高晶体管器件的沟道中的迁移率的应力。可以使用诸如无电镀或电解电镀的选择性电化学金属沉积工艺来形成金属合金层。

2. 发明授权

US08003473B2 Bipolar transistor with silicided sub-collector 有权
标题翻译：双极晶体管，带硅化子集电极
公开(公告)号：US08003473B2
公开(公告)日：2011-08-23
申请号：US12557557
申请日：2009-09-11
申请人： Francois Pagette , Christian Lavoie , Anna Topol
发明人： Francois Pagette , Christian Lavoie , Anna Topol
IPC分类号： H01L21/331
CPC分类号： H01L29/737 , H01L29/0821 , H01L29/66242
摘要： Embodiments of the invention provide a method of fabricating a semiconductor device. The method includes defining a sub-collector region in a layer of doped semiconductor material; forming an active region, a dielectric region, and a reach-through region on top of the layer of doped semiconductor material with the dielectric region separating the active region from the reach-through region; and siliciding the reach-through region and a portion of the sub-collector region to form a partially silicided conductive pathway. A semiconductor device made thereby is also provided.
摘要翻译：本发明的实施例提供一种制造半导体器件的方法。该方法包括在掺杂半导体材料层中限定子集电极区; 在所述掺杂半导体材料层的顶部上形成有源区，电介质区和到达区，所述电介质区将所述有源区与所述覆盖区分离; 并且将通过区域和子集电极区域的一部分硅化以形成部分硅化的导电路径。还提供了由此制成的半导体器件。

3. 发明申请

US20110084393A1 METHOD OF FORMING ELECTRODEPOSITED CONTACTS 有权
标题翻译：形成电沉积联系人的方法
公开(公告)号：US20110084393A1
公开(公告)日：2011-04-14
申请号：US12967633
申请日：2010-12-14
申请人： Cyril Cabral, JR. , Hariklia Deligianni , Randolph F. Knarr , Sandra G. Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe M. Vereecken
发明人： Cyril Cabral, JR. , Hariklia Deligianni , Randolph F. Knarr , Sandra G. Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe M. Vereecken
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L21/2885 , H01L21/76843 , H01L21/76846 , H01L21/76877 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A contact metallurgy structure comprising a patterned dielectric layer having vias on a substrate; a silicide layer of cobalt and/or nickel located at the bottom of vias; a contact layer comprising Ti located in vias on top of the silicide layer; a diffusion layer located in vias and on top of the contact layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer comprises at least one member selected from the group consisting of copper, ruthenium, rhodium platinum, palladium, iridium, rhenium, tungsten, gold, silver and osmium and alloys thereof. When the metal fill layer comprises rhodium, the diffusion layer is not required. Optionally a seed layer for the metal fill layer can be employed.
摘要翻译：一种接触式冶金结构，包括在衬底上具有通孔的图案化介电层; 位于通孔底部的钴和/或镍的硅化物层; 包含位于硅化物层顶部的通孔中的Ti的接触层; 位于所述接触层的通孔和顶部的扩散层; 提供通孔中的金属填充层以及制造方法。金属填充层包括选自铜，钌，铑铂，钯，铱，铼，钨，金，银和锇中的至少一种以及它们的合金。当金属填充层包含铑时，不需要扩散层。任选地，可以使用用于金属填充层的种子层。

4. 发明授权

US07851357B2 Method of forming electrodeposited contacts 有权
标题翻译：形成电沉积触点的方法
公开(公告)号：US07851357B2
公开(公告)日：2010-12-14
申请号：US12130381
申请日：2008-05-30
申请人： Cyril Cabral, Jr. , Lili Deligianni , Randolph F. Knarr , Sandra G. Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe M. Vereecken
发明人： Cyril Cabral, Jr. , Lili Deligianni , Randolph F. Knarr , Sandra G. Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe M. Vereecken
IPC分类号： H01L21/4763
CPC分类号： H01L23/485 , H01L21/2885 , H01L21/76843 , H01L21/76846 , H01L21/76877 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.
摘要翻译：一种接触式冶金结构，包括在基底上具有空腔的图案化电介质层; 位于空腔底部的硅化物或锗化物层，例如钴和/或镍; 接触层，其包含位于介电层顶部并且在空腔内并且与底部上的硅化物或锗化物层接触的Ti或Ti / TiN; 位于所述接触层顶部和所述空腔内的扩散阻挡层; 可选地，位于阻挡层顶部的用于电镀的种子层; 提供通孔中的金属填充层以及制造方法。金属填充层用选自铜，铑，钌，铱，钼，金，银，镍，钴，银，金，镉和锌中的至少一种电池和其合金电沉积。当金属填充层是铑，钌或铱时，在填充金属和电介质之间不需要有效的扩散阻挡层。当阻挡层是可镀的，例如钌，铑，铂或铱时，不需要种子层。

5. 发明申请

US20090212388A1 HIGH-Z STRUCTURE AND METHOD FOR CO-ALIGNMENT OF MIXED OPTICAL AND ELECTRON BEAM LITHOGRAPHIC FABRICATION LEVELS 有权
标题翻译：混合光电子束光刻制备水平的高Z结构与方法
公开(公告)号：US20090212388A1
公开(公告)日：2009-08-27
申请号：US12436189
申请日：2009-05-06
申请人： David Michael Fried , John Michael Hergenrother , Sharee Jane McNab , Michael J. Rooks , Anna Topol
发明人： David Michael Fried , John Michael Hergenrother , Sharee Jane McNab , Michael J. Rooks , Anna Topol
IPC分类号： H01L29/06
CPC分类号： G03F9/708 , B82Y10/00 , B82Y40/00 , G03F7/7045 , G03F9/7076 , G03F9/7088 , H01J37/3174 , H01L21/76283 , H01L21/823481 , H01L21/84 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A structure for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target. The structure including a first trench in a semiconductor substrate, the first trench extending from a top surface of the substrate into the substrate a first distance; an electron back-scattering layer in a bottom of the first trench; a dielectric capping layer in the trench over the back-scattering layer; and a second trench in the substrate, the second trench extending from the top surface of the substrate into the substrate a second distance, the second distance less than the first distance.
摘要翻译：用于将集成电路芯片的制造级别的第一组特征对准到电子束对准目标的结构。所述结构包括半导体衬底中的第一沟槽，所述第一沟槽从所述衬底的顶表面延伸到所述衬底中第一距离; 在第一沟槽的底部的电子背散射层; 背面散射层上的沟槽中的介电覆盖层; 以及所述衬底中的第二沟槽，所述第二沟槽从所述衬底的顶表面延伸到所述衬底中第二距离，所述第二距离小于所述第一距离。

6. 发明申请

US20090140297A1 SELF-ALIGNMENT SCHEME FOR A HETEROJUNCTION BIPOLAR TRANSISTOR 审中-公开
标题翻译：自对准双极晶体管的自对准方案
公开(公告)号：US20090140297A1
公开(公告)日：2009-06-04
申请号：US12114036
申请日：2008-05-02
申请人： Francois Pagette , Anna Topol
发明人： Francois Pagette , Anna Topol
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/7378 , H01L29/66242
摘要： Embodiments herein present a structure, method, etc. for a self-alignment scheme for a heterojunction bipolar transistor (HBT). An HBT is provided, comprising an extrinsic base, a first self-aligned silicide layer over the extrinsic base, and a nitride etch stop layer above the first self-aligned silicide layer. A continuous layer is also included between the first self-aligned silicide layer and the nitride etch stop layer, wherein the continuous layer can comprise oxide. The HBT further includes spacers adjacent the continuous layer, wherein the spacers and the continuous layer separate the extrinsic base from an emitter contact. In addition, an emitter is provided, wherein the height of the emitter is less than or equal to the height of the extrinsic base. Moreover, a second self-aligned silicide layer is over the emitter, wherein the height of the second silicide layer is less than or equal to the height of the first silicide layer.
摘要翻译：本文的实施方案提供了用于异质结双极晶体管（HBT）的自对准方案的结构，方法等。提供了一种HBT，其包括非本征基极，在外部基极上的第一自对准硅化物层，以及位于第一自对准硅化物层上方的氮化物蚀刻停止层。第一自对准硅化物层和氮化物蚀刻停止层之间还包括连续层，其中连续层可以包括氧化物。 HBT还包括邻近连续层的间隔物，其中间隔物和连续层将外部碱基与发射体接触分开。此外，提供了发射器，其中发射器的高度小于或等于外部基极的高度。此外，第二自对准硅化物层在发射极之上，其中第二硅化物层的高度小于或等于第一硅化物层的高度。

7. 发明授权

US07498256B2 Copper contact via structure using hybrid barrier layer 有权
标题翻译：铜接触通孔结构使用混合阻挡层
公开(公告)号：US07498256B2
公开(公告)日：2009-03-03
申请号：US11465865
申请日：2006-08-21
申请人： Randolph F. Knarr , Christopher D. Sheraw , Andrew H. Simon , Anna Topol , Yun-Yu Wang , Keith Kwong Hon Wong
发明人： Randolph F. Knarr , Christopher D. Sheraw , Andrew H. Simon , Anna Topol , Yun-Yu Wang , Keith Kwong Hon Wong
IPC分类号： H01L21/00
CPC分类号： H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Contact via structures using a hybrid barrier layer, are disclosed. One contact via structure includes: an opening through a dielectric to a silicide region; a first layer in the opening in direct contact with the silicide region, wherein the first layer is selected from the group consisting of: titanium (Ti) and tungsten nitride (WN); at least one second layer over the first layer, the at least one second layer selected from the group consisting of: tantalum nitride (TaN), titanium nitride (TiN), tantalum (Ta), ruthenium (Ru), rhodium (Rh), platinum (Pt) and cobalt (Co); a seed layer for copper (Cu); and copper (Cu) filling a remaining portion of the opening.
摘要翻译：公开了通过使用混合阻挡层的结构的接触。一个接触通孔结构包括：通过电介质到硅化物区的开口; 与所述硅化物区直接接触的所述开口中的第一层，其中所述第一层选自：钛（Ti）和氮化钨（WN）; 在第一层上的至少一个第二层，选自氮化钽（TaN），氮化钛（TiN），钽（Ta），钌（Ru），铑（Rh），铑铂（Pt）和钴（Co）; 铜（Cu）种子层; 和填充开口的剩余部分的铜（Cu）。

8. 发明授权

US07405154B2 Structure and method of forming electrodeposited contacts 有权
标题翻译：形成电沉积触点的结构和方法
公开(公告)号：US07405154B2
公开(公告)日：2008-07-29
申请号：US11308433
申请日：2006-03-24
申请人： Cyril Cabral, Jr. , Hariklia Deligianni , Randolph F. Knarr , Sandra G. Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe M. Vereecken
发明人： Cyril Cabral, Jr. , Hariklia Deligianni , Randolph F. Knarr , Sandra G. Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe M. Vereecken
IPC分类号： H01L21/4763
CPC分类号： H01L23/485 , H01L21/2885 , H01L21/76843 , H01L21/76846 , H01L21/76877 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.
摘要翻译：一种接触式冶金结构，包括在基底上具有空腔的图案化电介质层; 位于空腔底部的硅化物或锗化物层，例如钴和/或镍; 接触层，其包含位于介电层顶部并且在空腔内并与底部的硅化物或锗化物层接触的Ti或Ti / TiN; 位于所述接触层顶部和所述空腔内的扩散阻挡层; 可选地，位于阻挡层顶部的用于电镀的种子层; 提供通孔中的金属填充层以及制造方法。金属填充层用选自铜，铑，钌，铱，钼，金，银，镍，钴，银，金，镉和锌中的至少一种电池和其合金电沉积。当金属填充层是铑，钌或铱时，在填充金属和电介质之间不需要有效的扩散阻挡层。当阻挡层是可镀的，例如钌，铑，铂或铱时，不需要种子层。

9. 发明申请

US20080121936A1 SELF-ALIGNMENT SCHEME FOR A HETEROJUNCTION BIPOLAR TRANSISTOR 有权
标题翻译：自对准双极晶体管的自对准方案
公开(公告)号：US20080121936A1
公开(公告)日：2008-05-29
申请号：US11460013
申请日：2006-07-26
申请人： Francois Pagette , Anna Topol
发明人： Francois Pagette , Anna Topol
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/7378 , H01L29/66242
摘要： Embodiments herein present a structure, method, etc. for a self-alignment scheme for a heterojunction bipolar transistor (HBT). An HBT is provided, comprising an extrinsic base, a first self-aligned silicide layer over the extrinsic base, and a nitride etch stop layer above the first self-aligned silicide layer. A continuous layer is also included between the first self-aligned silicide layer and the nitride etch stop layer, wherein the continuous layer can comprise oxide. The HBT further includes spacers adjacent the continuous layer, wherein the spacers and the continuous layer separate the extrinsic base from an emitter contact. In addition, an emitter is provided, wherein the height of the emitter is less than or equal to the height of the extrinsic base. Moreover, a second self-aligned silicide layer is over the emitter, wherein the height of the second silicide layer is less than or equal to the height of the first silicide layer.
摘要翻译：本文的实施方案提供了用于异质结双极晶体管（HBT）的自对准方案的结构，方法等。提供了一种HBT，其包括非本征基极，在外部基极上的第一自对准硅化物层，以及位于第一自对准硅化物层上方的氮化物蚀刻停止层。第一自对准硅化物层和氮化物蚀刻停止层之间还包括连续层，其中连续层可以包括氧化物。 HBT还包括邻近连续层的间隔物，其中间隔物和连续层将外部碱基与发射体接触分开。此外，提供了发射器，其中发射器的高度小于或等于外部基极的高度。此外，第二自对准硅化物层在发射极之上，其中第二硅化物层的高度小于或等于第一硅化物层的高度。

10. 发明授权

US08089157B2 Contact metallurgy structure 有权
标题翻译：接触冶金结构
公开(公告)号：US08089157B2
公开(公告)日：2012-01-03
申请号：US12967633
申请日：2010-12-14
申请人： Cyril Cabral, Jr. , Hariklia Deligianni , Randolph F. Knarr , Sandra G. Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe M. Vereecken
发明人： Cyril Cabral, Jr. , Hariklia Deligianni , Randolph F. Knarr , Sandra G. Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe M. Vereecken
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/485 , H01L21/2885 , H01L21/76843 , H01L21/76846 , H01L21/76877 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A contact metallurgy structure comprising a patterned dielectric layer having vias on a substrate; a silicide layer of cobalt and/or nickel located at the bottom of vias; a contact layer comprising Ti located in vias on top of the silicide layer; a diffusion layer located in vias and on top of the contact layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer comprises at least one member selected from the group consisting of copper, ruthenium, rhodium platinum, palladium, iridium, rhenium, tungsten, gold, silver and osmium and alloys thereof. When the metal fill layer comprises rhodium, the diffusion layer is not required. Optionally a seed layer for the metal fill layer can be employed.
摘要翻译：一种接触式冶金结构，包括在衬底上具有通孔的图案化介电层; 位于通孔底部的钴和/或镍的硅化物层; 包含位于硅化物层顶部的通孔中的Ti的接触层; 位于接触层的通孔和顶部的扩散层; 提供通孔中的金属填充层以及制造方法。金属填充层包括选自铜，钌，铑铂，钯，铱，铼，钨，金，银和锇中的至少一种及其合金。当金属填充层包含铑时，不需要扩散层。任选地，可以使用用于金属填充层的种子层。

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