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1. 发明申请

US20100296035A1 DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND DISPLAY DEVICE HAVING THE SAME 审中-公开
标题翻译：显示基板，其制造方法和具有该基板的显示装置
公开(公告)号：US20100296035A1
公开(公告)日：2010-11-25
申请号：US12848416
申请日：2010-08-02
申请人： Jong-Seong Kim , Sung-Hwan Cho , Ho-Nam Yum , Jae-Hyun Kim , Jung-Woo Park , Bong-Sun Seo , Seong-Chul Hong , Seong-Ho Kim
发明人： Jong-Seong Kim , Sung-Hwan Cho , Ho-Nam Yum , Jae-Hyun Kim , Jung-Woo Park , Bong-Sun Seo , Seong-Chul Hong , Seong-Ho Kim
IPC分类号： G02F1/1335 , B05D5/12
CPC分类号： G02F1/133555 , G02F1/13439
摘要： A display substrate includes a transparent substrate, a pixel layer, an organic insulating layer, a transparent electrode and a reflective electrode. The pixel layer is formed on the transparent substrate, and includes a plurality of pixel parts. Each of the pixel parts includes a transmission region and a reflection region. The organic insulating layer is formed on the pixel layer. The transparent electrode is formed on the organic insulating layer corresponding to each of the pixel parts. The reflective electrode is formed on the transparent electrode corresponding to the reflection region. The reflective electrode includes a silver alloy that includes silver (Ag) and impurities having a low solubility in the silver.
摘要翻译：显示基板包括透明基板，像素层，有机绝缘层，透明电极和反射电极。像素层形成在透明基板上，并且包括多个像素部。每个像素部分包括透射区域和反射区域。有机绝缘层形成在像素层上。透明电极形成在对应于每个像素部分的有机绝缘层上。反射电极形成在对应于反射区域的透明电极上。反射电极包括银合金，其包含银（Ag）和在银中具有低溶解度的杂质。

2. 发明申请

US20070195236A1 Display substrate, method of manufacturing the same and display device having the same 审中-公开
标题翻译：显示基板及其制造方法以及具有该基板的显示装置
公开(公告)号：US20070195236A1
公开(公告)日：2007-08-23
申请号：US11506531
申请日：2006-08-18
申请人： Jong-Seong Kim , Sung-Hwan Cho , Ho-nam Yum , Jae-Hyun Kim , Jung-Woo Park , Bong-Sun Seo , Seong-Chul Hong , Seong-Ho Kim
发明人： Jong-Seong Kim , Sung-Hwan Cho , Ho-nam Yum , Jae-Hyun Kim , Jung-Woo Park , Bong-Sun Seo , Seong-Chul Hong , Seong-Ho Kim
IPC分类号： G02F1/1335
CPC分类号： G02F1/133555 , G02F1/13439
摘要： A display substrate includes a transparent substrate, a pixel layer, an organic insulating layer, a transparent electrode and a reflective electrode. The pixel layer is formed on the transparent substrate, and includes a plurality of pixel parts. Each of the pixel parts includes a transmission region and a reflection region. The organic insulating layer is formed on the pixel layer. The transparent electrode is formed on the organic insulating layer corresponding to each of the pixel parts. The reflective electrode is formed on the transparent electrode corresponding to the reflection region. The reflective electrode includes a silver alloy that includes silver (Ag) and impurities having a low solubility in the silver.
摘要翻译：显示基板包括透明基板，像素层，有机绝缘层，透明电极和反射电极。像素层形成在透明基板上，并且包括多个像素部。每个像素部分包括透射区域和反射区域。有机绝缘层形成在像素层上。透明电极形成在对应于每个像素部分的有机绝缘层上。反射电极形成在对应于反射区域的透明电极上。反射电极包括银合金，其包含银（Ag）和在银中具有低溶解度的杂质。

3. 发明申请

US20080081479A1 Method for fabricating fine pattern in semiconductor device 失效
标题翻译：在半导体器件中制造精细图案的方法
公开(公告)号：US20080081479A1
公开(公告)日：2008-04-03
申请号：US11824362
申请日：2007-06-29
申请人： Jung-Woo Park
发明人： Jung-Woo Park
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/32139
摘要： A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist pattern over an etch target layer, forming a first hard mask layer over a substrate structure, planarizing the first hard mask layer to form a first hard mask pattern and expose the first photoresist pattern, removing the first photoresist pattern, forming a second photoresist pattern enclosing the first hard mask pattern, forming a second hard mask layer over the substrate structure, planarizing the second hard mask layer to form a second hard mask pattern and expose the first hard mask pattern, removing the second photoresist pattern, and etching the etch target layer using the first hard mask pattern and the second hard mask pattern.
摘要翻译：在半导体器件中制造精细图案的方法包括在蚀刻目标层上形成第一光致抗蚀剂图案，在衬底结构上形成第一硬掩模层，平面化第一硬掩模层以形成第一硬掩模图案，并将第一光致抗蚀剂图案，去除第一光致抗蚀剂图案，形成包围第一硬掩模图案的第二光致抗蚀剂图案，在衬底结构上方形成第二硬掩模层，平坦化第二硬掩模层以形成第二硬掩模图案，硬掩模图案，去除第二光致抗蚀剂图案，以及使用第一硬掩模图案和第二硬掩模图案蚀刻蚀刻目标层。

4. 发明授权

US07326587B2 Semiconductor memory device having capacitor and method of forming the same 失效
标题翻译：具有电容器的半导体存储器件及其形成方法
公开(公告)号：US07326587B2
公开(公告)日：2008-02-05
申请号：US11153746
申请日：2005-06-14
申请人： Jung-Woo Park , Jung-Min Ha
发明人： Jung-Woo Park , Jung-Min Ha
IPC分类号： H01L21/00
CPC分类号： H01L27/1087 , H01L28/84 , H01L31/0236 , H01L31/02363 , H01L31/0745 , Y02E10/50
摘要： A semiconductor memory device having a capacitor is disclosed. The capacitor includes a bottom capacitor surface formed of a silicon-germanium crystalline layer or a dual layer in which a silicon-germanium crystalline layer covers a silicon crystalline layer. The bottom capacitor surface is uneven and is conventionally formed by an epitaxial method. The silicon germanium crystalline layer is approximately 5 to 50 percent germanium content by weight. The method of fabricating the semiconductor memory device comprises: selectively exposing the surface of a crystalline silicon substrate at the region where the capacitor bottom electrode is formed; supplying a source gas to grow a silicon germanium crystalline layer at the surface of the selectively exposed silicon substrate; stacking a dielectric layer over the silicon germanium crystalline layer; and stacking a conductive layer over the dielectric layer to form a capacitor top electrode. After forming the silicon germanium crystalline layer to a predefined thickness, a silicon crystalline layer can be further grown at the silicon germanium crystalline layer. After forming the silicon germanium crystalline layer and before forming the dielectric layer, annealing can be performed for a predefined time.
摘要翻译：公开了一种具有电容器的半导体存储器件。电容器包括由硅 - 锗晶体层形成的底部电容器表面或其中硅 - 锗晶体层覆盖硅晶体层的双层。底部电容器表面是不均匀的，并且通常通过外延法形成。硅锗晶体层的锗含量约为5-50％。制造半导体存储器件的方法包括：在形成电容器底部电极的区域选择性地暴露晶体硅衬底的表面; 供应源气体以在选择性暴露的硅衬底的表面上生长硅锗晶体层; 在硅锗晶体层上堆叠介电层; 并在该电介质层上层叠导电层以形成电容器顶部电极。在将硅锗晶层形成预定厚度之后，可以在硅锗晶层进一步生长硅晶层。在形成硅锗晶层之后，在形成电介质层之前，可以进行预定时间的退火。

5. 发明申请

US20070182383A1 Electric power converting device and power converting method for controlling doubly-fed induction generator 有权
标题翻译：用于控制双馈感应发电机的电力转换装置和电力转换方法
公开(公告)号：US20070182383A1
公开(公告)日：2007-08-09
申请号：US11647124
申请日：2006-12-28
申请人： Jung-Woo Park , Ki-Wook Lee , Dong-Wook Kim
发明人： Jung-Woo Park , Ki-Wook Lee , Dong-Wook Kim
IPC分类号： H02P9/00
CPC分类号： H02P9/46 , H02J3/386 , H02P9/007 , Y02E10/763
摘要： Disclosed herein is an electric power converting device and power converting method for controlling doubly-fed induction generators, which provides a synchronous generator for generating auxiliary electric power independently of a doubly-fed induction generator so as to generate electricity even in a system power-free environment, a grid-side converter is composed of a three-phase four-wire converter so as to generate a balanced voltage even in an unbalanced load condition and automatically synchronize a stator voltage of a doubly-fed induction generator and a system voltage with each other.
摘要翻译：本发明公开了一种用于控制双馈感应发电机的电力转换装置和电力转换方法，其提供了一种用于独立于双馈感应发电机产生辅助电力的同步发电机，以便即使在无系统的系统中也能发电电网侧转换器由三相四线转换器构成，即使在不平衡负载条件下也能产生平衡电压，并且自动同步双馈感应发电机的定子电压和系统电压其他。

6. 发明申请

US20050230732A1 Semiconductor memory device having capacitor and method of forming the same 失效
标题翻译：具有电容器的半导体存储器件及其形成方法
公开(公告)号：US20050230732A1
公开(公告)日：2005-10-20
申请号：US11153746
申请日：2005-06-14
申请人： Jung-Woo Park , Jung-Min Ha
发明人： Jung-Woo Park , Jung-Min Ha
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242 , H01L31/0236 , H01L31/0745 , H01L27/14
CPC分类号： H01L27/1087 , H01L28/84 , H01L31/0236 , H01L31/02363 , H01L31/0745 , Y02E10/50
摘要： A semiconductor memory device having a capacitor is disclosed. The capacitor includes a bottom capacitor surface formed of a silicon-germanium crystalline layer or a dual layer in which a silicon-germanium crystalline layer covers a silicon crystalline layer. The bottom capacitor surface is uneven and is conventionally formed by an epitaxial method. The silicon germanium crystalline layer is approximately 5 to 50 percent germanium content by weight. The method of fabricating the semiconductor memory device comprises: selectively exposing the surface of a crystalline silicon substrate at the region where the capacitor bottom electrode is formed; supplying a source gas to grow a silicon germanium crystalline layer at the surface of the selectively exposed silicon substrate; stacking a dielectric layer over the silicon germanium crystalline layer; and stacking a conductive layer over the dielectric layer to form a capacitor top electrode. After forming the silicon germanium crystalline layer to a predefined thickness, a silicon crystalline layer can be further grown at the silicon germanium crystalline layer. After forming the silicon germanium crystalline layer and before forming the dielectric layer, annealing can be performed for a predefined time.
摘要翻译：公开了一种具有电容器的半导体存储器件。电容器包括由硅 - 锗晶体层形成的底部电容器表面或其中硅 - 锗晶体层覆盖硅晶体层的双层。底部电容器表面是不均匀的，并且通常通过外延法形成。硅锗晶体层的锗含量约为5-50％。制造半导体存储器件的方法包括：在形成电容器底部电极的区域选择性地暴露晶体硅衬底的表面; 供应源气体以在选择性暴露的硅衬底的表面上生长硅锗晶体层; 在硅锗晶体层上堆叠介电层; 并在该电介质层上层叠导电层以形成电容器顶部电极。在将硅锗晶层形成预定厚度之后，可以在硅锗晶层进一步生长硅晶层。在形成硅锗晶层之后，在形成电介质层之前，可以进行预定时间的退火。

7. 发明授权

US06835996B2 Method and device for forming an STI type isolation in a semiconductor device 失效
标题翻译：在半导体器件中形成STI型隔离的方法和装置
公开(公告)号：US06835996B2
公开(公告)日：2004-12-28
申请号：US10684451
申请日：2003-10-15
申请人： Chul-Sung Kim , Si-Young Choi , Jung-Woo Park , Jong-Ryol Ryu , Byeong-Chan Lee
发明人： Chul-Sung Kim , Si-Young Choi , Jung-Woo Park , Jong-Ryol Ryu , Byeong-Chan Lee
IPC分类号： H01L2900
CPC分类号： H01L21/76224
摘要： A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.
摘要翻译：半导体器件中的沟槽隔离及其制造方法包括：在硅衬底中形成具有用于器件隔离的内侧壁的沟槽; 在形成沟槽的内侧壁的硅衬底的表面上形成氧化物层; 向硅衬底提供愈合元件以去除悬挂键; 并用器件隔离层填充沟槽，从而形成沟槽隔离，而不产生悬挂键导致电荷陷阱。

8. 发明授权

US06577175B2 Method for generating internal clock of semiconductor memory device and circuit thereof 失效
公开(公告)号：US06577175B2
公开(公告)日：2003-06-10
申请号：US10041091
申请日：2002-01-07
申请人： Nam-Seog Kim , Jung-Woo Park
发明人： Nam-Seog Kim , Jung-Woo Park
IPC分类号： H03L706
CPC分类号： G11C7/222 , G11C7/22 , H03L7/0812
摘要： The invention relates to a semiconductor memory device and a method for generating an internal clock, the circuit of the semiconductor device including: a receiver for receiving an external clock; a delay compensation circuit for receiving an output of the receiver and delaying it by as much as the compensation delay time and control delay time subtracted out of a cycle of the external clock; an external control delay part for delaying an output of the delay compensation circuit by as much as the control delay time and unit increase/decrease delay time in response to an external control code; and an internal clock driver for driving an output of the external control delay part and generating an internal clock centered to externally applied data, thereby performing an accurate timing control to an external clock without loss of performance.

9. 发明授权

US06562707B2 Method of forming a semiconductor device using selective epitaxial growth 有权
公开(公告)号：US06562707B2
公开(公告)日：2003-05-13
申请号：US10043942
申请日：2002-01-10
申请人： Jong-Ryol Ryu , Jung-Woo Park , Jung-Min Ha , Si-Young Choi
发明人： Jong-Ryol Ryu , Jung-Woo Park , Jung-Min Ha , Si-Young Choi
IPC分类号： H01L213205
CPC分类号： H01L29/66636 , H01L21/02052 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/28525 , H01L21/28562 , H01L21/76879 , H01L29/7834
摘要： A method of forming a semiconductor device using selective epitaxial growth (SEG) is provided. This method includes forming an insulating layer pattern having a window on a semiconductor substrate. The window exposes a predetermined region of the semiconductor substrate. The substrate having the window is cleaned, thereby removing any native oxide layer on the exposed substrate. The cleaned substrate is oxidized. Accordingly, a sacrificial oxide layer is formed thereon. The sacrificial oxide layer is removed. Thus, the exposed substrate has substantially no crystalline defects. A single crystalline semiconductor layer is then grown on the exposed substrate using SEG.

10. 发明申请

US20110156118A1 SEMICONDUCTOR DEVICE WITH VERTICAL CELLS AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：具有垂直电池的半导体器件及其制造方法
公开(公告)号：US20110156118A1
公开(公告)日：2011-06-30
申请号：US12830654
申请日：2010-07-06
申请人： Jung-Woo Park
发明人： Jung-Woo Park
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L29/0649 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/10876 , H01L29/0657 , H01L29/0692 , H01L29/66666 , H01L29/7827
摘要： A method for fabricating a semiconductor substrate includes defining an active region by forming a device isolation layer over the substrate, forming a first trench dividing the active region into a first active region and a second active region, forming a buried bit line filling a portion of the first trench, forming a gap-filling layer gap-filling an upper portion of the first trench over the buried bit line, forming second trenches by etching the gap-filling layer and the device isolation layer in a direction crossing the buried bit line, and forming a first buried word line and a second buried word line filling the second trenches, wherein the first buried word line and the second buried word line are shaped around sidewalls of the first active region and the second active region, respectively.
摘要翻译：一种用于制造半导体衬底的方法，包括通过在衬底上形成器件隔离层来限定有源区，形成将有源区分成第一有源区和第二有源区的第一沟槽，形成填充部分所述第一沟槽在所述掩埋位线上形成填充所述第一沟槽的上部的间隙填充层间隙，通过在与所述掩埋位线交叉的方向上蚀刻所述间隙填充层和所述器件隔离层来形成第二沟槽，以及形成填充所述第二沟槽的第一掩埋字线和第二掩埋字线，其中所述第一掩埋字线和所述第二掩埋字线分别围绕所述第一有源区和所述第二有源区的侧壁成形。

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