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1. 发明申请

US20080052443A1 CROSS-COUPLED PERIPHERAL COMPONENT INTERCONNECT EXPRESS SWITCH 有权
标题翻译：交叉耦合外围组件互连开关
公开(公告)号：US20080052443A1
公开(公告)日：2008-02-28
申请号：US11466734
申请日：2006-08-23
申请人： Daniel R. Cassiday , Andrew W. Wilson , John Acton , Charles Binford , Raymond J. Lanza
发明人： Daniel R. Cassiday , Andrew W. Wilson , John Acton , Charles Binford , Raymond J. Lanza
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： A plurality of PCIe switch complexes are interposed between a plurality of I/O devices and a plurality of microprocessor complexes. Each PCIe switching complex comprises a plurality of PCIe switches wherein each switch possesses at least one non-transparent port. The non-transparent port is used to cross-couple each PCIe switch creating an active matrix of paths between the HBAs associated with each I/O device and each microprocessor. The paths between each HBA (I/O device) and each microprocessor are mapped using a recursive algorithm providing each I/O device with direct memory access to each microprocessor.
摘要翻译：多个PCIe交换机复合体被插入在多个I / O设备和多个微处理器复合体之间。每个PCIe交换机包括多个PCIe交换机，其中每个交换机具有至少一个非透明端口。非透明端口用于交叉耦合每个PCIe交换机，创建与每个I / O设备和每个微处理器相关联的HBA之间的路径的有源矩阵。使用递归算法映射每个HBA（I / O设备）和每个微处理器之间的路径，为每个I / O设备提供对每个微处理器的直接存储器访问。

2. 发明授权

US07676625B2 Cross-coupled peripheral component interconnect express switch 有权
标题翻译：交叉耦合外设组件互连快速开关
公开(公告)号：US07676625B2
公开(公告)日：2010-03-09
申请号：US11466734
申请日：2006-08-23
申请人： Daniel R. Cassiday , Andrew W. Wilson , John Acton , Charles Binford , Raymond J. Lanza
发明人： Daniel R. Cassiday , Andrew W. Wilson , John Acton , Charles Binford , Raymond J. Lanza
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： A plurality of PCIe switch complexes are interposed between a plurality of I/O devices and a plurality of microprocessor complexes. Each PCIe switching complex comprises a plurality of PCIe switches wherein each switch possesses at least one non-transparent port. The non-transparent port is used to cross-couple each PCIe switch creating an active matrix of paths between the HBAs associated with each I/O device and each microprocessor. The paths between each HBA (I/O device) and each microprocessor are mapped using a recursive algorithm providing each I/O device with direct memory access to each microprocessor.
摘要翻译：多个PCIe交换机复合体被插入在多个I / O设备和多个微处理器复合体之间。每个PCIe交换机包括多个PCIe交换机，其中每个交换机具有至少一个非透明端口。非透明端口用于交叉耦合每个PCIe交换机，创建与每个I / O设备和每个微处理器相关联的HBA之间的路径的有源矩阵。使用递归算法映射每个HBA（I / O设备）和每个微处理器之间的路径，为每个I / O设备提供对每个微处理器的直接存储器访问。

3. 发明申请

US20080052432A1 DATA BUFFER ALLOCATION IN A NON-BLOCKING DATA SERVICES PLATFORM USING INPUT/OUTPUT SWITCHING FABRIC 有权
标题翻译：使用输入/输出开关织物的非阻塞数据服务平台中的数据缓冲区分配
公开(公告)号：US20080052432A1
公开(公告)日：2008-02-28
申请号：US11466726
申请日：2006-08-23
申请人： Andrew W. Wilson , John Acton , Charles Binford , Daniel R. Cassiday , Raymond J. Lanza
发明人： Andrew W. Wilson , John Acton , Charles Binford , Daniel R. Cassiday , Raymond J. Lanza
IPC分类号： G06F13/00
CPC分类号： G06F3/0658 , G06F3/0611 , G06F3/0656 , G06F3/0689
摘要： Data buffering allocation in a microprocessor complex for a request of memory allocation is supported through a remote buffer batch allocation protocol. The separation of control and data placement allows simultaneous maximization of microprocessor complex load sharing, and minimization of inter-processor signaling/metadata migration. Separating processing control from data placement allows the location of data buffering to be chosen so as to maximize bus bandwidth utilization and achieve non-blocking switch behavior. This separation reduces the need for inter-processor communication and associated interrupts thus improving computation efficiency and performance.
摘要翻译：通过远程缓冲区批量分配协议支持用于内存分配请求的微处理器复杂数据缓冲分配。控制和数据放置的分离允许微处理器复杂负载共享的同时最大化，以及处理器间信令/元数据迁移的最小化。分离处理控制与数据布局允许选择数据缓冲的位置，以便最大化总线带宽利用率并实现非阻塞交换行为。这种分离减少了对处理器间通信和相关中断的需求，从而提高了计算效率和性能。

4. 发明授权

US07594060B2 Data buffer allocation in a non-blocking data services platform using input/output switching fabric 有权
标题翻译：数据缓冲区在使用输入/输出交换结构的非阻塞数据服务平台中进行分配
公开(公告)号：US07594060B2
公开(公告)日：2009-09-22
申请号：US11466726
申请日：2006-08-23
申请人： Andrew W. Wilson , John Acton , Charles Binford , Daniel R. Cassiday , Raymond J. Lanza
发明人： Andrew W. Wilson , John Acton , Charles Binford , Daniel R. Cassiday , Raymond J. Lanza
IPC分类号： G06F13/00
CPC分类号： G06F3/0658 , G06F3/0611 , G06F3/0656 , G06F3/0689
摘要： Data buffering allocation in a microprocessor complex for a request of memory allocation is supported through a remote buffer batch allocation protocol. The separation of control and data placement allows simultaneous maximization of microprocessor complex load sharing, and minimization of inter-processor signaling/metadata migration. Separating processing control from data placement allows the location of data buffering to be chosen so as to maximize bus bandwidth utilization and achieve non-blocking switch behavior. This separation reduces the need for inter-processor communication and associated interrupts thus improving computation efficiency and performance.
摘要翻译：通过远程缓冲区批量分配协议支持用于内存分配请求的微处理器复杂数据缓冲分配。控制和数据放置的分离允许微处理器复杂负载共享的同时最大化，以及处理器间信令/元数据迁移的最小化。分离处理控制与数据布局允许选择数据缓冲的位置，以便最大化总线带宽利用率并实现非阻塞交换行为。这种分离减少了对处理器间通信和相关中断的需求，从而提高了计算效率和性能。

5. 发明申请

US20080052403A1 INPUT/OUTPUT ROUTERS WITH DUAL INTERNAL PORTS 审中-公开
标题翻译：输入/输出路由器与双内部端口
公开(公告)号：US20080052403A1
公开(公告)日：2008-02-28
申请号：US11466729
申请日：2006-08-23
申请人： John Acton , Charles Binford , Daniel R. Cassiday , Raymond J. Lanza , Andrew W. Wilson
发明人： John Acton , Charles Binford , Daniel R. Cassiday , Raymond J. Lanza , Andrew W. Wilson
IPC分类号： G06F15/16 , G06F11/00
CPC分类号： G06F11/2007 , G06F3/0601 , G06F2003/0692 , H04L49/1523 , H04L49/351 , H04L49/357 , H04L49/358
摘要： Dual ported Input/Output (“I/O”) routers couple I/O devices to a cross-coupled switching fabric providing multiple levels of data path redundancy. Each I/O router possesses two or more internal ports allowing each I/O router to access multiple switches in a cross-coupled switching fabric. The additional redundant paths between each I/O device and each microprocessor complex provide additional means to balance data traffic and thereby maximize bandwidth utilization. I/O routers can be interleaved with single HBAs establishing access a switching fabric that uses cross-coupled nontransparent ports thus providing each I/O device with multiple paths upon which to pass data. Data paths are identified by a recursive address scheme that uniquely identifies each data path option available to each I/O device.
摘要翻译：双端口输入/输出（“I / O”）路由器将I / O设备耦合到交叉耦合交换结构，提供多级数据路径冗余。每个I / O路由器拥有两个或多个内部端口，允许每个I / O路由器访问交叉耦合交换结构中的多个交换机。每个I / O设备和每个微处理器复合体之间的附加冗余路径提供了额外的平衡数据流量的手段，从而最大化带宽利用率。 I / O路由器可以与单个HBA交织，建立访问交换结构，该交换结构使用交叉耦合的非透明端口，从而为每个I / O设备提供传递数据的多个路径。数据路径由唯一标识每个I / O设备可用的每个数据路径选项的递归地址方案来标识。

6. 发明授权

US07860941B1 InfiniBand layer 4 router and methods for implementing same in an InfiniBand based external storage device 有权
标题翻译： InfiniBand第4层路由器和在基于InfiniBand的外部存储设备中实现相同的方法
公开(公告)号：US07860941B1
公开(公告)日：2010-12-28
申请号：US10198337
申请日：2002-07-17
申请人： Andrew W. Wilson
发明人： Andrew W. Wilson
IPC分类号： G06F15/16
CPC分类号： H04L45/00
摘要： In one of many embodiments, an InfiniBand network architecture is provided where a router circuitry communicates data between a host and a target device where the router circuitry includes circuitry for generating an external queue pair (QP) for establishing communication between the router circuitry and the host through a reliable connection (RC) session. The router circuitry also includes circuitry for generating internal queue pairs where the internal queue pairs establishes communication between the router circuitry and a device controller, between the between the device controller and the target device, and between the router circuitry and the target device by using reliable connection (RC) sessions. The router circuitry also includes mapping circuitry capable of establishing data destinations in communications between the target and the host. The internal queue pairs are coupled with the external queue pair through the mapping circuitry.
摘要翻译：在许多实施例中的一个实施例中，提供InfiniBand网络架构，其中路由器电路在主机和目标设备之间传送数据，其中路由器电路包括用于生成用于在路由器电路和主机之间建立通信的外部队列对（QP）的电路通过可靠的连接（RC）会话。路由器电路还包括用于产生内部队列对的电路，其中内部队列对通过使用可靠的方式在路由器电路和设备控制器之间，设备控制器和目标设备之间以及路由器电路与目标设备之间建立通信连接（RC）会话。路由器电路还包括能够在目标和主机之间的通信中建立数据目的地的映射电路。内部队列对通过映射电路与外部队列对耦合。

7. 发明授权

US07058723B2 Congestion control for internet protocol storage 失效
标题翻译：互联网协议存储的拥塞控制
公开(公告)号：US07058723B2
公开(公告)日：2006-06-06
申请号：US09726676
申请日：2000-11-29
申请人： Andrew W. Wilson
发明人： Andrew W. Wilson
IPC分类号： G06F15/16 , G06F3/06 , G06F11/00
CPC分类号： H04L47/193 , H04L47/10 , H04L47/12 , H04L47/263 , H04L47/283 , H04L47/30 , H04L47/31 , H04L69/16 , H04L69/161 , H04L69/163 , H04L69/22 , H04L69/32 , Y02D50/10
摘要： A network system for actively controlling congestion to optimize throughput is provided. The network system includes a sending host which is configured to send packet traffic at a set rate. The network system also includes a sending switch for receiving the packet traffic. The sending switch includes an input buffer for receiving the packet traffic at the set rate where the input buffer is actively monitored to ascertain a capacity level. The sending switch also includes code for setting a probability factor that is correlated to the capacity level where the probability factor increases as the capacity level increases and decreases as the capacity level decreases. The sending switch also has code for randomly generating a value where the value is indicative of whether packets being sent by the sending switch are to be marked with a congestion indicator. The sending switch also includes transmit code that forwards the packet traffic out of the sending switch where the packet traffic includes one of marked packets and unmarked packets. The network system also has a receiving end which is the recipient of the packet traffic and also generates acknowledgment packets back to the sending host where the acknowledgment packets are marked with the congestion indicator when receiving marked packets and are not marked with the congestion indicator when receiving unmarked packets. In another example, the sending host is configured to monitor the acknowledgment packets and to adjust the set rate based on whether the acknowledgment packets are marked with the congestion indicator. In a further example, the set rate is decreased every time one of the marked packets is detected and increased when no marked packets are detected per round trip time (PRTT).
摘要翻译：提供了一种用于主动控制拥塞以优化吞吐量的网络系统。网络系统包括被配置为以设定速率发送分组业务的发送主机。网络系统还包括用于接收分组业务的发送交换机。发送交换机包括用于以设定速率接收分组业务的输入缓冲器，其中主动监视输入缓冲器以确定容量级别。发送开关还包括用于设置与容量级别相关的概率因子的代码，其中容量级别随容量级别增加而降低，随着容量级别降低。发送开关还具有用于随机生成值的代码，其中值表示发送交换机发送的分组是否被标记有拥塞指示符。发送交换机还包括将分组业务转发出发送交换机的发送代码，其中分组业务包括标记分组和未标记分组之一。网络系统还具有作为分组业务的接收者的接收端，并且当接收到标记的分组时，将确认分组生成到发送主机，其中确认分组被标记为拥塞指示符，并且在接收时未标记拥塞指示符未标记的数据包。在另一示例中，发送主机被配置为监视确认分组，并且基于确认分组是否用拥塞指示符标记来调整设置速率。在另一示例中，每当检测到标记的分组之一时，设置速率降低，并且当每往返时间（PRTT）没有检测到标记的分组时增加。

8. 发明授权

US07031904B1 Methods for implementing an ethernet storage protocol in computer networks 有权
标题翻译：在计算机网络中实现以太网存储协议的方法
公开(公告)号：US07031904B1
公开(公告)日：2006-04-18
申请号：US09490630
申请日：2000-01-24
申请人： Andrew W. Wilson , Paul J. von Stamwitz , Laurence B. Boucher
发明人： Andrew W. Wilson , Paul J. von Stamwitz , Laurence B. Boucher
IPC分类号： G06F15/16
CPC分类号： H04L67/1097
摘要： A method for processing storage data that is to be communicated over a network is provided. Initially, storage data to be transmitted over a network is provided. Once the data is provided, the method includes serializing the storage data using storage encapsulation protocol headers to generate serialized storage data. Then, the serialized storage data is encapsulated using a simple transport protocol to generate simple transport protocol data segments of the storage data. At this point, each of the simple transport protocol data segments are encapsulated into Ethernet frames. The Ethernet frames can then be communicated over standard Ethernet hubs and switches to enable communication to a selected storage target. In one example, the storage data is provided in the form of SCSI data, ATAPI data, and the like. This data can then be communicated to any storage target that may be connected to the network that is capable of processing the storage data.
摘要翻译：提供一种用于处理要通过网络传送的存储数据的方法。最初提供通过网络发送的存储数据。一旦提供了数据，该方法包括使用存储封装协议头序列化存储数据，以生成序列化的存储数据。然后，使用简单的传输协议来封装序列化的存储数据，以生成存储数据的简单的传输协议数据段。此时，每个简单的传输协议数据段被封装成以太网帧。以太网帧然后可以通过标准以太网集线器和交换机进行通信，以实现与所选存储目标的通信。在一个示例中，存储数据以SCSI数据，ATAPI数据等的形式提供。然后，该数据可以被传送到可以连接到能够处理存储数据的网络的任何存储目标。

9. 发明授权

US06996105B1 Method for processing data packet headers 失效
标题翻译：处理数据包头的方法
公开(公告)号：US06996105B1
公开(公告)日：2006-02-07
申请号：US10029186
申请日：2001-12-19
申请人： Andrew W. Wilson
发明人： Andrew W. Wilson
IPC分类号： H04I12/28
CPC分类号： H04L67/1097 , H04L69/16 , H04L69/161 , H04L69/22
摘要： A method for processing data packets received at a computing system is provided. The method includes receiving a data packet and processing lower layer protocol headers of the data packet to expose overlying headers of the data packet. The overlying headers in a shared hardware component capable of executing header data for a transmission control protocol (TCP) communication and a storage transport protocol (STP) communication are processed. The header data for the TCP communication and the STP communication are positioned into standard header field locations. It is determined whether the data packet is from the TCP communication or the STP communication. If the data packet is from the TCP communication the processing of the overlying headers of the data packet separately in TCP processing is completed. If the data packet is from the STP communication, the processing of the overlying headers of the data packet separately in STP processing is completed.
摘要翻译：提供了一种用于处理在计算系统处接收的数据分组的方法。该方法包括接收数据分组并处理数据分组的下层协议报头，以暴露数据分组的上覆报头。处理能够执行传输控制协议（TCP）通信和存储传输协议（STP）通信的报头数据的共享硬件组件中的覆盖报头被处理。用于TCP通信和STP通信的报头数据被定位到标准报头字段位置。确定数据分组是来自TCP通信还是STP通信。如果数据分组来自TCP通信，则在TCP处理中单独处理数据分组的上位报头。如果数据分组来自STP通信，则在STP处理中分别处理数据分组的上位报头。

10. 发明授权

US06738821B1 Ethernet storage protocol networks 有权
标题翻译：以太网存储协议网络
公开(公告)号：US06738821B1
公开(公告)日：2004-05-18
申请号：US09490629
申请日：2000-01-24
申请人： Andrew W. Wilson , Paul J. von Stamwitz , Laurence B. Boucher
发明人： Andrew W. Wilson , Paul J. von Stamwitz , Laurence B. Boucher
IPC分类号： G06F15177
CPC分类号： H04L67/1097 , H04L12/413 , H04L12/4633 , H04L69/16 , H04L69/22 , H04L69/32 , H04L69/329
摘要： An Ethernet storage protocol (ESP) enabled network is provided. The network includes a host computer having host interface circuitry for communicating data in an Ethernet network, and the host interface circuitry is configured to receive parallel data from the host computer provided in accordance with a peripheral device protocol, serialize the parallel data, and encapsulate the serialized parallel data into Ethernet frames for transmission over the Ethernet network. The network also includes a target having target interface circuitry for communicating data in the Ethernet network. The target interface circuitry is configured to receive the encapsulated serialized parallel data and reconstruct the serialized parallel data into the peripheral device protocol. The peripheral device protocol is one of a SCSI protocol, an ATAPI protocol, and a UDMA protocol. The data can be storage data, network data, file data, virtual interface data, or any other type of data that will benefit from high bandwidth transmission over a network.
摘要翻译：提供了支持以太网存储协议（ESP）的网络。网络包括具有用于在以太网中传送数据的主机接口电路的主计算机，并且主机接口电路被配置为从根据外围设备协议提供的主计算机接收并行数据，串行化并行数据，并封装将并行数据串行化为以太网帧，以通过以太网进行传输。网络还包括具有用于在以太网中传送数据的目标接口电路的目标。目标接口电路被配置为接收封装的串行并行数据，并将串行并行数据重构成外围设备协议。外围设备协议是SCSI协议，ATAPI协议和UDMA协议之一。数据可以是存储数据，网络数据，文件数据，虚拟接口数据，或者将通过网络从高带宽传输中受益的任何其他类型的数据。

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