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1. 发明申请

US20060115937A1 Devices for an insulated dielectric interface between high-k material and silicon 审中-公开
标题翻译：高k材料和硅之间绝缘电介质界面的器件
公开(公告)号：US20060115937A1
公开(公告)日：2006-06-01
申请号：US11324934
申请日：2006-01-04
申请人： Joel Barnett , Mark Gardner , Naim Moumen , Jim Gutt
发明人： Joel Barnett , Mark Gardner , Naim Moumen , Jim Gutt
IPC分类号： H01L21/84 , H01L21/31 , H01L21/302
CPC分类号： H01L21/02337 , H01L21/02142 , H01L21/02148 , H01L21/02175 , H01L21/022 , H01L21/02238 , H01L21/28185 , H01L21/28194 , H01L21/31116 , H01L21/3144 , H01L21/31662 , H01L21/31691 , H01L29/513 , H01L29/517 , H01L29/6659
摘要： Methods and devices are described for an insulated dielectric interface between a high-k material and silicon for improving electrical characteristics of devices. A method includes forming an oxide layer on a silicon substrate using an in situ steam generation process, etching the oxide layer to form a reduced thickness oxide layer of less than 10 Angstroms, and annealing the reduced thickness oxide layer with ammonia. A semiconductor wafer comprises a silicon substrate, an oxide layer coupled to the silicon substrate where the oxide layer having a thickness of less than 10 Angstroms, and a high-k dielectric material deposited onto the oxide layer.
摘要翻译：描述了用于高k材料和硅之间的绝缘电介质界面的方法和装置，以改善器件的电特性。一种方法包括使用原位蒸汽产生工艺在硅衬底上形成氧化物层，蚀刻氧化物层以形成小于10埃的厚度减小的氧化物层，并且用氨将还原厚度的氧化物层退火。半导体晶片包括硅衬底，耦合到硅衬底的氧化物层，其中氧化物层具有小于10埃的厚度，以及沉积在氧化物层上的高k电介质材料。

2. 发明申请

US20050070120A1 Methods and devices for an insulated dielectric interface between high-k material and silicon 审中-公开
标题翻译：高k材料与硅之间绝缘电介质界面的方法和装置
公开(公告)号：US20050070120A1
公开(公告)日：2005-03-31
申请号：US10911981
申请日：2004-08-05
申请人： Joel Barnett , Mark Gardner , Naim Moumen , Jim Gutt
发明人： Joel Barnett , Mark Gardner , Naim Moumen , Jim Gutt
IPC分类号： H01L21/28 , H01L21/311 , H01L21/314 , H01L21/316 , H01L21/336 , H01L21/8242 , H01L29/51
CPC分类号： H01L21/02337 , H01L21/02142 , H01L21/02148 , H01L21/02175 , H01L21/022 , H01L21/02238 , H01L21/28185 , H01L21/28194 , H01L21/31116 , H01L21/3144 , H01L21/31662 , H01L21/31691 , H01L29/513 , H01L29/517 , H01L29/6659
摘要： Methods and devices are described for an insulated dielectric interface between a high-k material and silicon for improving electrical characteristics of devices. A method includes forming an oxide layer on a silicon substrate using an in situ steam generation process, etching the oxide layer to form a reduced thickness oxide layer of less than 10 Angstroms, and annealing the reduced thickness oxide layer with ammonia. A semiconductor wafer comprises a silicon substrate, an oxide layer coupled to the silicon substrate where the oxide layer having a thickness of less than 10 Angstroms, and a high-k dielectric material deposited onto the oxide layer.
摘要翻译：描述了用于高k材料和硅之间的绝缘电介质界面的方法和装置，以改善器件的电特性。一种方法包括使用原位蒸汽产生工艺在硅衬底上形成氧化物层，蚀刻氧化物层以形成小于10埃的厚度减小的氧化物层，并且用氨将还原厚度的氧化物层退火。半导体晶片包括硅衬底，耦合到硅衬底的氧化物层，其中氧化物层具有小于10埃的厚度，以及沉积在氧化物层上的高k电介质材料。

3. 发明申请

US20050202659A1 Ion implantation of high-k materials in semiconductor devices 审中-公开
标题翻译：半导体器件中高k材料的离子注入
公开(公告)号：US20050202659A1
公开(公告)日：2005-09-15
申请号：US10799910
申请日：2004-03-12
申请人： Hong-Jyh Li , Mark Gardner
发明人： Hong-Jyh Li , Mark Gardner
IPC分类号： H01L21/425 , H01L21/8238
CPC分类号： H01J37/32706 , C23C16/405 , C23C16/56 , H01J37/32412
摘要： A semiconductor device comprises a substrate including isolation regions and active regions, a high-k material layer implanted with a species, the high-k material layer proximate the substrate, and a gate electrode proximate the high-k material layer.
摘要翻译：半导体器件包括包括隔离区域和有源区域的衬底，注入物质的高k材料层，靠近衬底的高k材料层和靠近高k材料层的栅电极。

4. 发明申请

US20060054943A1 Flash EEPROM with metal floating gate electrode 有权
标题翻译：闪存EEPROM带金属浮栅电极
公开(公告)号：US20060054943A1
公开(公告)日：2006-03-16
申请号：US10940513
申请日：2004-09-14
申请人： Hong-Jyh Li , Mark Gardner
发明人： Hong-Jyh Li , Mark Gardner
IPC分类号： H01L21/8238 , H01L21/336 , H01L29/788 , H01L29/80 , H01L31/112
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/28273 , H01L29/42324 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/7883
摘要： A memory device comprises a substrate including isolation regions and active regions, and a floating gate stack proximate the substrate. The floating gate stack comprises a first high-k dielectric layer proximate the substrate, a first metal layer proximate the first high-k dielectric layer, and a second high-k dielectric layer proximate the first metal layer. The memory device comprises a control gate electrode proximate the floating gate stack.
摘要翻译：存储器件包括包括隔离区域和有源区域的衬底以及靠近衬底的浮置栅极堆叠。浮栅堆叠包括靠近衬底的第一高k电介质层，靠近第一高k电介质层的第一金属层和靠近第一金属层的第二高k电介质层。存储器件包括靠近浮置栅极堆叠的控制栅电极。

5. 发明授权

US09221166B1 Protective shield for hand-held tools 有权
标题翻译：手持工具防护罩
公开(公告)号：US09221166B1
公开(公告)日：2015-12-29
申请号：US14313880
申请日：2014-06-24
申请人： Ronald Jacobs , Mark Gardner , John Randolph Fisher
发明人： Ronald Jacobs , Mark Gardner , John Randolph Fisher
IPC分类号： B25G1/00 , B25G1/10
CPC分类号： B25G1/00 , B25G1/10
摘要： A protective device for a hand-held tool includes a protective shield having a first end and an opposing second end, a first clamp portion attached to the first end of the protective shield, and a second clamp portion removably attached to the first clamp portion. The first and second clamp portions are configured to securely fix a portion of the handle of the hand-held tool therebetween when the second clamp portion is attached to the first clamp portion.
摘要翻译：一种用于手持式工具的保护装置包括具有第一端和相对的第二端的保护屏蔽件，附接到保护屏蔽的第一端的第一夹紧部分和可移除地附接到第一夹持部分的第二夹紧部分。第一和第二夹持部构造成当第二夹持部附接到第一夹持部时，将手持工具的手柄的一部分牢固地固定在其间。

6. 发明授权

US07282773B2 Semiconductor device with high-k dielectric layer 有权
标题翻译：具有高k电介质层的半导体器件
公开(公告)号：US07282773B2
公开(公告)日：2007-10-16
申请号：US10940055
申请日：2004-09-14
申请人： Hong-Jyh Li , Mark Gardner
发明人： Hong-Jyh Li , Mark Gardner
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/02175 , H01L21/02194 , H01L21/02255 , H01L21/28185 , H01L21/28194 , H01L21/3142 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/6659
摘要： A semiconductor device comprises a substrate including isolation regions and active regions, and a high-k dielectric layer proximate the substrate. The high-k dielectric layer comprises a mixture formed by annealing at least one high-k material and at least one metal to oxidize the metal. The semiconductor device comprises a gate electrode proximate the high-k dielectric layer.
摘要翻译：半导体器件包括包括隔离区域和有源区域的衬底以及靠近衬底的高k电介质层。高k介电层包括通过退火至少一种高k材料和至少一种金属以氧化金属而形成的混合物。半导体器件包括靠近高k电介质层的栅电极。

7. 发明授权

US6150695A Multilevel transistor formation employing a local substrate formed within a shallow trench 失效
标题翻译：使用在浅沟槽内形成的局部衬底的多晶体管形成
公开(公告)号：US6150695A
公开(公告)日：2000-11-21
申请号：US741812
申请日：1996-10-30
申请人： Mark Gardner , Daniel Kadosh , Derick J. Wristers
发明人： Mark Gardner , Daniel Kadosh , Derick J. Wristers
IPC分类号： H01L21/822 , H01L27/06 , H01L27/01
CPC分类号： H01L27/0688 , H01L21/8221
摘要： A dual level transistor and a fabrication technique. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an upper surface of a first local substrate such that the second transistor is vertically displaced from the first transistor. The first local substrate is formed within a local trench etched into a first inter-substrate dielectric. By vertically displacing the first and second transistors, the lateral separation required to isolate first and second transistors in a typical single plane process is eliminated. The integrated circuit includes a semiconductor global substrate and a first transistor formed on the global substrate. The first transistor includes a first gate dielectric formed on an upper surface of the global substrate and a first conductive gate structure formed on an upper surface of the first dielectric. The integrated circuit further includes a first inter-substrate dielectric that is formed on the first conductive gate structure and the global substrate. The first inter-substrate dielectric includes a local trench. A first local substrate is formed within the local trench. A second transistor is located within the first local substrate. The second transistor includes a second gate dielectric formed on an upper surface of the first local substrate and a second conductive gate structure formed on an upper surface of the second gate dielectric.
摘要翻译：双级晶体管和制造技术。双电平晶体管是集成电路，其中第一晶体管形成在全局电介质的上表面上，并且第二晶体管形成在第一局部衬底的上表面上，使得第二晶体管垂直从第一晶体管。第一局部衬底形成在蚀刻到第一衬底间电介质中的局部沟槽内。通过垂直移位第一和第二晶体管，消除了在典型的单平面工艺中隔离第一和第二晶体管所需的横向分离。集成电路包括半导体全局基板和形成在全局基板上的第一晶体管。第一晶体管包括形成在全局衬底的上表面上的第一栅极电介质和形成在第一电介质的上表面上的第一导电栅极结构。集成电路还包括形成在第一导电栅极结构和全局基板上的第一基板间电介质。第一基板间电介质包括局部沟槽。第一局部衬底形成在局部沟槽内。第二晶体管位于第一局部衬底内。第二晶体管包括形成在第一局部衬底的上表面上的第二栅极电介质和形成在第二栅极电介质的上表面上的第二导电栅极结构。

8. 发明申请

US20060125026A1 Semiconductor device with high-k dielectric layer 有权
标题翻译：具有高k电介质层的半导体器件
公开(公告)号：US20060125026A1
公开(公告)日：2006-06-15
申请号：US10940055
申请日：2004-09-14
申请人： Hong-Jyh Li , Mark Gardner
发明人： Hong-Jyh Li , Mark Gardner
IPC分类号： H01L29/94
CPC分类号： H01L21/02175 , H01L21/02194 , H01L21/02255 , H01L21/28185 , H01L21/28194 , H01L21/3142 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/6659
摘要： A semiconductor device comprises a substrate including isolation regions and active regions, and a high-k dielectric layer proximate the substrate. The high-k dielectric layer comprises a mixture formed by annealing at least one high-k material and at least one metal to oxidize the metal. The semiconductor device comprises a gate electrode proximate the high-k dielectric layer.
摘要翻译：半导体器件包括包括隔离区域和有源区域的衬底以及靠近衬底的高k电介质层。高k介电层包括通过退火至少一种高k材料和至少一种金属以氧化金属而形成的混合物。半导体器件包括靠近高k电介质层的栅电极。

9. 发明授权

US6159814A Spacer formation by poly stack dopant profile design 失效
标题翻译：通过多层掺杂剂分布设计形成间隔物
公开(公告)号：US6159814A
公开(公告)日：2000-12-12
申请号：US968444
申请日：1997-11-12
申请人： Mark Gardner , Fred Hause , Charles May
发明人： Mark Gardner , Fred Hause , Charles May
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78
CPC分类号： H01L21/28211 , H01L21/28052 , H01L21/28176 , H01L29/6659 , H01L29/7833
摘要： A method for forming a semiconductor device to produce graded doping in the source region and the drain region includes the steps of implanting the gate material, usually a polysilicon, with a dopant ion that varies the level of oxide formation on the gate. The dopant ion is driven into undoped polysilicon. Nitrogen ions, may also be implanted in the polysilicon to contain the previously implanted ions. For N-type transistors, typically arsenic is implanted. For P-type transistors, typically boron is implanted. Gates are formed. The gate structure is then oxidized. The oxidation process is controlled to grow a desired thickness of silicon dioxide on the gate. The portion of the gate carrying the dopant grows silicon dioxide either more quickly or more slowly. An isotropic etch can then used to remove a portion of the silicon oxide and form a knob on each sidewall of the gate. A heavy ion implant is then done to convert a portion of the lightly doped source region into a heavily doped region within the source region, and to convert a portion of the lightly doped drain region into a heavily doped region within the drain region. Some of the implanted ions are stopped by the knobs on the gate sidewalls. The regions under the knobs do not have as deep an ion implantation resulting in a shallow region beneath the knob. This forms a graded junction having a specific geometry. The geometry of the interface between the lightly doped region and the heavily doped region in the source region and the drain region depends on the geometry (thickness) of silicon dioxide knobs formed on the sidewall of the gate.
摘要翻译：用于形成在源极区域和漏极区域中产生渐变掺杂的半导体器件的方法包括以下步骤：通过改变栅极上的氧化物形成水平的掺杂剂离子注入栅极材料（通常为多晶硅）。掺杂剂离子被驱入未掺杂的多晶硅。氮离子也可以注入到多晶硅中以容纳先前注入的离子。对于N型晶体管，通常植入砷。对于P型晶体管，通常植入硼。门形成。然后将栅极结构氧化。控制氧化过程以在栅极上生长所需的二氧化硅厚度。携带掺杂剂的栅极部分会更快或更慢地生长二氧化硅。然后可以使用各向同性蚀刻去除氧化硅的一部分并在栅极的每个侧壁上形成旋钮。然后进行重离子注入以将轻掺杂源区的一部分转换为源区内的重掺杂区，并将轻掺杂漏区的一部分转换为漏区内的重掺杂区。一些注入的离子被栅极侧壁上的旋钮阻挡。旋钮下面的区域没有深度的离子注入，导致旋钮下方的浅区域。这形成具有特定几何形状的渐变连接点。源极区域和漏极区域中的轻掺杂区域和重掺杂区域之间的界面的几何形状取决于形成在栅极侧壁上的二氧化硅旋钮的几何形状（厚度）。

10. 发明授权

US07138680B2 Memory device with floating gate stack 有权
标题翻译：带浮动堆栈的存储器件
公开(公告)号：US07138680B2
公开(公告)日：2006-11-21
申请号：US10940513
申请日：2004-09-14
申请人： Hong-Jyh Li , Mark Gardner
发明人： Hong-Jyh Li , Mark Gardner
IPC分类号： H01L29/788
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/28273 , H01L29/42324 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/7883
摘要： A memory device comprises a substrate including isolation regions and active regions, and a floating gate stack proximate the substrate. The floating gate stack comprises a first high-k dielectric layer proximate the substrate, a first metal layer proximate the first high-k dielectric layer, and a second high-k dielectric layer proximate the first metal layer. The memory device comprises a control gate electrode proximate the floating gate stack.
摘要翻译：存储器件包括包括隔离区域和有源区域的衬底以及靠近衬底的浮置栅极堆叠。浮栅堆叠包括靠近衬底的第一高k电介质层，靠近第一高k电介质层的第一金属层和靠近第一金属层的第二高k电介质层。存储器件包括靠近浮置栅极堆叠的控制栅电极。

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