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1. 发明授权

US07082501B2 Remote node accessing local memory by using distributed shared memory 有权
公开(公告)号：US07082501B2
公开(公告)日：2006-07-25
申请号：US10405571
申请日：2003-04-02
申请人： Wei-Long Chen , Jiin Lai , Wayne Tseng
发明人： Wei-Long Chen , Jiin Lai , Wayne Tseng
IPC分类号： G06F12/00
CPC分类号： G06F13/1663 , G06F12/0817
摘要： A DSM system includes a local node, a first remote node, and a second remote nodes. The data access method for a remote node to access a local node in the DSM system includes the steps of directly receiving data of a local memory line from a local memory of the local node, and transmitting the data to the first remote node when the local memory line is in HOME-N or SHARED status; directly receiving data of the local memory line from the second remote node, and transmitting the data to the first remote node when the local memory line is in a GONE status; and asserting a transaction to a system bus to read data of the local memory line, receiving the data via the system bus, and transmitting the data to the first remote node when the local memory line is in HOME-M status.

2. 发明授权

US06931496B2 Data-maintenance method of distributed shared memory system 有权
标题翻译：分布式共享存储系统的数据维护方法
公开(公告)号：US06931496B2
公开(公告)日：2005-08-16
申请号：US10409756
申请日：2003-04-09
申请人： Wei-Long Chen , Wayne Tseng , Jiin Lai
发明人： Wei-Long Chen , Wayne Tseng , Jiin Lai
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F2212/2542
摘要： A distributed shared memory (DSM) system includes at least a first and a second nodes. The first node includes an external cache for storing a data from a local memory of the second node and at least two processors optionally accessing the data from the external cache. Whether the data has been modified into a modified data by a first certain one of the at least two processors is first determined. If positive, whether a second certain one of the at least two processors is allowed to share the modified data is further determined. If the second certain processor is allowed to share the modified data, it may directly request the modified data from the first certain processor via a bus inside the first node.
摘要翻译：分布式共享存储器（DSM）系统至少包括第一和第二节点。第一节点包括用于存储来自第二节点的本地存储器的数据的外部高速缓存，以及可选地从外部高速缓存访问数据的至少两个处理器。首先确定数据是否已被至少两个处理器中的第一特定处理器修改为修改数据。如果是肯定的，则进一步确定至少两个处理器中的第二个特定的一个被允许共享修改的数据。如果第二特定处理器被允许共享修改的数据，则它可以经由第一节点内的总线从第一特定处理器直接请求修改的数据。

3. 发明授权

US07231560B2 Apparatus and method for testing motherboard having PCI express devices 有权
标题翻译：用于测试具有PCI Express设备的主板的装置和方法
公开(公告)号：US07231560B2
公开(公告)日：2007-06-12
申请号：US10985461
申请日：2004-11-10
申请人： Jiin Lai , Wayne Tseng
发明人： Jiin Lai , Wayne Tseng
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31716 , G01R31/043 , G01R31/2815
摘要： This invention discloses a method for testing at least one physical link on a motherboard associated with an on-board PCI Express device. A test card is connected to an input/output port on the motherboard, wherein the test card has a PCI Express test device. A test pattern is transmitted from the test card to the PCI Express device and receiving a test result pattern by the test card from the PCI Express device through the physical link for testing thereof. The test result pattern is examined to determine defects of the physical link on the motherboard.
摘要翻译：本发明公开了一种用于测试与板载PCI Express设备相关联的母板上的至少一个物理链路的方法。测试卡连接到母板上的输入/输出端口，其中测试卡具有PCI Express测试设备。测试模式从测试卡发送到PCI Express设备，并通过测试卡从PCI Express设备通过物理链路接收测试结果模式，以进行测试。检查测试结果模式，以确定主板上物理链路的缺陷。

4. 发明申请

US20050235187A1 Apparatus and method for testing motherboard having PCI express devices 有权
标题翻译：用于测试具有PCI Express设备的主板的装置和方法
公开(公告)号：US20050235187A1
公开(公告)日：2005-10-20
申请号：US10985461
申请日：2004-11-10
申请人： Jiin Lai , Wayne Tseng
发明人： Jiin Lai , Wayne Tseng
IPC分类号： G01R31/04 , G01R31/28 , G01R31/317 , G06F11/22 , G06F13/00
CPC分类号： G01R31/31716 , G01R31/043 , G01R31/2815
摘要： This invention discloses a method for testing at least one physical link on a motherboard associated with an on-board PCI Express device. A test card is connected to an input/output port on the motherboard, wherein the test card has a PCI Express test device. A test pattern is transmitted from the test card to the PCI Express device and receiving a test result pattern by the test card from the PCI Express device through the physical link for testing thereof. The test result pattern is examined to determine defects of the physical link on the motherboard.
摘要翻译：本发明公开了一种用于测试与板载PCI Express设备相关联的母板上的至少一个物理链路的方法。测试卡连接到母板上的输入/输出端口，其中测试卡具有PCI Express测试设备。测试模式从测试卡发送到PCI Express设备，并通过测试卡从PCI Express设备通过物理链路接收测试结果模式，以进行测试。检查测试结果模式，以确定主板上物理链路的缺陷。

5. 发明授权

US08051350B2 Serial interface device built-in self test 有权
标题翻译：串行接口设备内置自检
公开(公告)号：US08051350B2
公开(公告)日：2011-11-01
申请号：US12346800
申请日：2008-12-30
申请人： Wayne Tseng
发明人： Wayne Tseng
IPC分类号： G06F11/00 , G06F7/02 , G01R31/28 , G01R31/30 , H03M13/00
CPC分类号： G06F11/27 , G06F17/505 , G06F2217/14 , H04L25/03866
摘要： A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.
摘要翻译：内置的自检电路包括图案发生器，弹性缓冲器，符号检测器和比较单元。模式生成器生成第一个测试模式以测试被测端口，然后获取并存储在弹性缓冲区中的结果模式。符号检测器检测测试结果模式中是否存在起始符号。如果存在，则生成与测试结果模式进行比较的第二测试模式。结果，确定被测端口的数据传输的可靠性。

6. 发明授权

US07613959B2 Data receiving apparatus of a PCI express device 有权
标题翻译： PCI Express设备的数据接收设备
公开(公告)号：US07613959B2
公开(公告)日：2009-11-03
申请号：US11162151
申请日：2005-08-30
申请人： Wayne Tseng
发明人： Wayne Tseng
IPC分类号： G06F11/00 , H04N1/00 , H04W4/00 , H04B10/08
CPC分类号： G06F11/27 , H04L25/03866
摘要： A data receiving apparatus of a PCI Express system includes a receiving device, an 8B10B decoder, a forged packet removing device, and a descrambling circuit. The forged packet removing device determines whether a disparity error occurs; and an offset removing circuit compensates a number of cycles of the lane offset. The data receiving apparatus is capable of eliminating error packet caused by framing error and preventing the problem of symbol disorder and disconnection caused by set ordered noise. Furthermore, the data receiving apparatus is also capable of removing offset.
摘要翻译： PCI Express系统的数据接收装置包括接收装置，8B10B解码器，伪造分组去除装置和解扰电路。伪造的分组去除装置确定是否出现视差错误; 并且偏移消除电路补偿车道偏移的多个周期。数据接收装置能够消除由成帧错误引起的错误分组，并且防止由设置的有序噪声引起的符号无序和断开的问题。此外，数据接收装置也能够去除偏移。

7. 发明授权

US08234530B2 Serial interface device built-in self test 有权
标题翻译：串行接口设备内置自检
公开(公告)号：US08234530B2
公开(公告)日：2012-07-31
申请号：US13110235
申请日：2011-05-18
申请人： Wayne Tseng
发明人： Wayne Tseng
IPC分类号： G06F11/00 , G06F7/02 , G01R31/28 , G01R31/30 , H03M13/00
CPC分类号： G06F11/27 , G06F17/505 , G06F2217/14 , H04L25/03866
摘要： A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.
摘要翻译：内置的自检电路包括图案发生器，弹性缓冲器，符号检测器和比较单元。模式生成器生成第一个测试模式以测试被测端口，然后获取并存储在弹性缓冲区中的结果模式。符号检测器检测测试结果模式中是否存在起始符号。如果存在，则生成与测试结果模式进行比较的第二测试模式。结果，确定被测端口的数据传输的可靠性。

8. 发明申请

US20110225470A1 Serial Interface Device Built-In Self Test 有权
标题翻译：串行接口设备内置自检
公开(公告)号：US20110225470A1
公开(公告)日：2011-09-15
申请号：US13110235
申请日：2011-05-18
申请人： Wayne Tseng
发明人： Wayne Tseng
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G06F11/27 , G06F17/505 , G06F2217/14 , H04L25/03866
摘要： A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.
摘要翻译：内置的自检电路包括图案发生器，弹性缓冲器，符号检测器和比较单元。模式生成器生成第一个测试模式以测试被测端口，然后获取并存储在弹性缓冲区中的结果模式。符号检测器检测测试结果模式中是否存在起始符号。如果存在，则生成与测试结果模式进行比较的第二测试模式。结果，确定被测端口的数据传输的可靠性。

9. 发明授权

US07640383B2 Method and related apparatus for configuring lanes to access ports 有权
标题翻译：用于配置车道以访问端口的方法和相关装置
公开(公告)号：US07640383B2
公开(公告)日：2009-12-29
申请号：US11162031
申请日：2005-08-26
申请人： Wayne Tseng
发明人： Wayne Tseng
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： A method and related apparatus for different lane and access port configurations of a bus. Such different configurations can apply to different applications requirements. In a preferred embodiment of the invention, a chipset can configure 18 lanes to 4 access ports of a peripheral communication interconnect express bus for selectively 4 different configurations. A first configuration provides single access port with 16 lanes, and two access ports for each has one lane. A second configuration provides two access ports for each has eight lanes, and two access ports for each has single lane. A third configuration provides one access port with eight lanes, two access ports for each has four lanes and another one access port with single lane. And a fourth configuration provides four access ports for each has four lanes.
摘要翻译：一种总线不同通道和接入端口配置的方法和相关设备。这种不同的配置可以应用于不同的应用需求。在本发明的优选实施例中，芯片组可以配置18个通道到4个外围通信互连快速总线的访问端口，用于选择性地4种不同的配置。第一种配置提供具有16个通道的单个访问端口，每个具有一个通道的两个访问端口。第二个配置提供两个接入端口，每个接口具有八个通道，每个接入端口具有单个通道。第三种配置提供一个具有八个通道的接入端口，每个具有四个通道的两个接入端口和具有单个通道的另一个接入端口。而第四个配置提供四个接入端口，每个接入端口有四个通道。

10. 发明授权

US07490278B2 PCI express physical layer built-in self test architecture 有权
标题翻译： PCI express物理层内置自检架构
公开(公告)号：US07490278B2
公开(公告)日：2009-02-10
申请号：US11162153
申请日：2005-08-30
申请人： Wayne Tseng
发明人： Wayne Tseng
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/27 , H04L25/03866
摘要： A built-in self test circuit includes a first pattern generator, an elastic buffer receiver, a command symbol detector, a second pattern generator, and a logic unit. The architecture is capable of compensating loopback latency automatically without having to utilize a device that stores test patterns generated by the first pattern generator, and error warning can be greatly reduced. Also, the architecture can reduce the effect of phase jitter and error rate count is provided. Hence, accuracy of test can be increased.
摘要翻译：内置自检电路包括第一图案发生器，弹性缓冲接收器，命令符号检测器，第二图案发生器和逻辑单元。该架构能够自动补偿环回延迟，而不必使用存储由第一模式发生器产生的测试模式的设备，并且可以大大降低错误警告。此外，架构可以减少相位抖动的影响，并提供错误率计数。因此，可以提高测试的准确性。

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