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    • 2. 发明授权
    • Method of fabricating thin film transistor by crystallization through metal layer forming source and drain electrodes
    • 通过金属层形成源极和漏极结晶化制造薄膜晶体管的方法
    • US08343796B2
    • 2013-01-01
    • US13206227
    • 2011-08-09
    • Ji-Su AhnSung-Chul Kim
    • Ji-Su AhnSung-Chul Kim
    • H01L21/00
    • H01L21/02532H01L21/02667H01L27/124H01L27/1281H01L27/3262H01L29/66757
    • A method of fabricating a thin film transistor includes patterning the amorphous semiconductor layer to form an amorphous semiconductor layer pattern, forming a gate electrode corresponding to the amorphous semiconductor layer pattern on a gate insulating layer, forming an interlayer insulating layer on the entire surface of the substrate, forming a first contact hole partially exposing the amorphous semiconductor layer pattern, forming a second contact hole partially exposing the gate electrode, and forming a metal layer on the entire surface of the substrate. The method also includes applying an electrical field to the metal layer such that a semiconductor layer is formed by crystallization of the amorphous semiconductor layer pattern, and patterning the metal layer to form source and drain electrodes that are insulated from the gate electrode and that are electrically connected with the semiconductor layer through the first contact hole.
    • 一种制造薄膜晶体管的方法,包括图案化非晶半导体层以形成非晶半导体层图案,在栅绝缘层上形成对应于非晶半导体层图案的栅电极,在该绝缘层的整个表面上形成层间绝缘层 形成部分暴露非晶半导体层图案的第一接触孔,形成部分暴露栅电极的第二接触孔,以及在基板的整个表面上形成金属层。 该方法还包括向金属层施加电场,使得通过非晶半导体层图案的结晶形成半导体层,并且图案化金属层以形成与栅电极绝缘的电极和漏电极,并且是电 通过第一接触孔与半导体层连接。
    • 4. 发明申请
    • Apparatus for Fabricating Thin Film Transistor
    • 薄膜晶体管制造装置
    • US20110139611A1
    • 2011-06-16
    • US12963193
    • 2010-12-08
    • Beong-Ju KimJi-Su AhnCheol-Ho YuSung-Chul Kim
    • Beong-Ju KimJi-Su AhnCheol-Ho YuSung-Chul Kim
    • C23C16/24C23C14/34C23C14/14
    • H01L21/67184H01L21/67196H01L21/67201
    • In an apparatus for fabricating a thin film transistor, amorphous silicon is deposited on a substrate in a first multi-chamber and is crystallized into polycrystalline silicon without using a separate process chamber or multi-chamber, and the substrate deposited with the amorphous silicon is loaded into a second multi-chamber for forming electrodes, thereby making it possible to minimize a characteristic deviation and improve fabrication process efficiency. The apparatus includes a first multi-chamber in which amorphous silicon is deposited on a substrate, a second multi-chamber in which electrodes are formed on the substrate, and a loading/unloading chamber interposed between the first multi-chamber and the second multi-chamber. The loading/unloading chamber includes a substrate holder on a lower side thereof and a power voltage supplier on an upper side thereof.
    • 在用于制造薄膜晶体管的装置中,非晶硅沉积在第一多腔中的衬底上,并且在不使用单独的处理室或多腔的情况下被结晶成多晶硅,并且将沉积有非晶硅的衬底加载 进入用于形成电极的第二多室中,从而使得可以使特性偏差最小化并提高制造工艺效率。 该装置包括:第一多腔室,其中非晶硅沉积在基底上;第二多腔室,其中在基底上形成电极;以及装载/卸载室,介于第一多腔室和第二多腔室之间, 房间。 装载/卸载室包括在其下侧的基板保持件和在其上侧的电源电压供应器。
    • 6. 发明申请
    • METHOD OF FABRICATING THIN FILM TRANSISTOR
    • 薄膜晶体管的制作方法
    • US20110294267A1
    • 2011-12-01
    • US13206227
    • 2011-08-09
    • Ji-Su AhnSung-Chul Kim
    • Ji-Su AhnSung-Chul Kim
    • H01L21/336
    • H01L21/02532H01L21/02667H01L27/124H01L27/1281H01L27/3262H01L29/66757
    • A thin film transistor includes a substrate, a buffer layer on the substrate, a semiconductor layer on the buffer layer, a gate insulating layer on the semiconductor layer, a gate electrode on the gate insulating layer, an interlayer insulating layer on the entire surface of the substrate having the gate electrode, a first contact hole and a second contact hole, and source and drain electrodes on the interlayer insulating layer, insulated from the gate electrode, and having a portion connected with the semiconductor layer through the first contact hole. An organic light emitting diode display may include the thin film transistor along with a passivation layer on the entire surface of the substrate, and a first electrode, an organic layer, and a second electrode, which are on the passivation layer and electrically connected with the source and drain electrodes.
    • 薄膜晶体管包括衬底,衬底上的缓冲层,缓冲层上的半导体层,半导体层上的栅极绝缘层,栅极绝缘层上的栅极电极,整个表面上的层间绝缘层 具有栅电极的基板,第一接触孔和第二接触孔,以及与栅电极绝缘的层间绝缘层上的源电极和漏电极,并且具有通过第一接触孔与半导体层连接的部分。 有机发光二极管显示器可以包括薄膜晶体管以及在基板的整个表面上的钝化层,以及第一电极,有机层和第二电极,它们位于钝化层上并与 源极和漏极。
    • 9. 发明授权
    • Method of fabricating thin film transistor
    • 制造薄膜晶体管的方法
    • US08420513B2
    • 2013-04-16
    • US13419757
    • 2012-03-14
    • Ji-Su AhnEui-Hoon HwangCheol-Ho YuKwang-Nam KimSung-Chul Kim
    • Ji-Su AhnEui-Hoon HwangCheol-Ho YuKwang-Nam KimSung-Chul Kim
    • H01L29/04H01L21/20
    • H01L29/78675H01L27/1248H01L27/1285H01L27/3262H01L29/66757
    • A thin film transistor (TFT), including a crystalline semiconductor pattern on a substrate, a gate insulating layer on the crystalline semiconductor pattern, the gate insulating layer having two first source/drain contact holes and a semiconductor pattern access hole therein, a gate electrode on the gate insulating layer, the gate electrode being between the two first source/drain contact holes, an interlayer insulating layer covering the gate electrode, the interlayer insulating layer having two second source/drain contact holes therein, and source and drain electrodes on the interlayer insulating layer, each of the source and drain electrodes being insulated from the gate electrode, and having a portion connected to the crystalline semiconductor pattern through the first and second source/drain contact holes.
    • 一种薄膜晶体管(TFT),包括在基板上的晶体半导体图形,在晶体半导体图案上的栅极绝缘层,栅极绝缘层具有两个第一源极/漏极接触孔和半导体图案访问孔,栅电极 在栅极绝缘层上,栅电极位于两个第一源极/漏极接触孔之间,覆盖栅电极的层间绝缘层,其中具有两个第二源极/漏极接触孔的层间绝缘层,以及栅电极上的源极和漏极 层间绝缘层,源极和漏极中的每一个与栅电极绝缘,并且具有通过第一和第二源极/漏极接触孔连接到晶体半导体图案的部分。