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1. 发明授权

US06432318B1 Dielectric etch process reducing striations and maintaining critical dimensions 失效
标题翻译：电介质蚀刻工艺减少条纹并维持临界尺寸
公开(公告)号：US06432318B1
公开(公告)日：2002-08-13
申请号：US09506112
申请日：2000-02-17
申请人： Ji Ding , Hidehiro Kojiri , Yoshio Ishikawa , Keiji Horioka , Ruiping Wang , Robert W. Wu , Hoiman Hung
发明人： Ji Ding , Hidehiro Kojiri , Yoshio Ishikawa , Keiji Horioka , Ruiping Wang , Robert W. Wu , Hoiman Hung
IPC分类号： H01L213065
CPC分类号： H01L21/31116
摘要： An oxide etching recipe including a heavy hydrogen-free fluorocarbon having F/C ratios less than 2 such as C4F6 or C5F8, an oxygen-containing gas such as O2, CO or CO2, a lighter fluorocarbon or hydrofluorocarbon, and a noble diluent gas such as Ar or Xe. The amounts of the first three gases are chosen such that the ratio (F—H)/(C—O) is at least 1.5 and no more than 2. Alternatively, the gas mixture may include the heavy fluorocarbon, carbon tetrafluoride, and the diluent with the ratio of the first two chosen such the ratio F/C is between 1.5 and 2.
摘要翻译：氧化物蚀刻配方包括F / C比小于2的重氢无碳氟化合物，例如C 4 F 6或C 5 F 8，含氧气体如O 2，CO或CO 2，较轻碳氟化合物或氢氟烃，以及稀有稀释气体作为Ar或Xe。选择前三种气体的量，使得比值（FH）/（CO）至少为1.5且不大于2.或者，气体混合物可以包括重碳氟化合物，四氟化碳和稀释剂，其比例的前两个被选择的比例F / C在1.5和2之间。

2. 发明授权

US06387287B1 Process for etching oxide using a hexafluorobutadiene and manifesting a wide process window 失效
标题翻译：使用六氟丁二烯蚀刻氧化物的方法，并呈现宽的工艺窗口
公开(公告)号：US06387287B1
公开(公告)日：2002-05-14
申请号：US09276311
申请日：1999-03-25
申请人： Hoiman Hung , Joseph P Caulfield , Hongqing Shan , Ruiping Wang , Gerald Zheyao Yin
发明人： Hoiman Hung , Joseph P Caulfield , Hongqing Shan , Ruiping Wang , Gerald Zheyao Yin
IPC分类号： H01L213065
CPC分类号： H01L21/31116
摘要： An oxide etching process, particularly useful for selectively etching oxide over a feature having a non-oxide composition, such as silicon nitride and especially when that feature has a corner that is prone to faceting during the oxide etch. The invention uses one of three hydrogen-free fluorocarbons having a low F/C ratio, specifically hexafluorobutadiene (C4F6), hexafluorocyclobutene (C4F6), and hexafluorobenzene (C6F6). At least hexafluorobutadiene has a boiling point below 10° C. and is commercially available. The fluorocarbon together with a substantial amount of a noble gas such as argon is excited into a high-density plasma in a reactor which inductively couples plasma source power into the chamber and RF biases the pedestal electrode supporting the wafer. Preferably, one of two two-step etch process is used. In the first, the source and bias power are reduced towards the end of the etch. In the second, the fluorocarbon is used in the main step to provide a good vertical profile and a more strongly polymerizing fluorocarbon such as difluoromethane (CH2F2) is added in the over etch to protect the nitride corner. The same chemistry can be used in a magnetically enhanced reactive ion etcher (MERIE), preferably with an even larger amount of argon.
摘要翻译：氧化物蚀刻工艺，特别适用于在具有非氧化物组成的特征（例如氮化硅）上选择性地蚀刻氧化物，特别是当该特征具有在氧化物蚀刻期间易于刻面的拐角时。本发明使用具有低F / C比的三种无氢碳氟化合物之一，特别是六氟丁二烯（C 4 F 6），六氟环丁烯（C 4 F 6）和六氟苯（C 6 F 6）。至少六氟丁二烯的沸点低于10℃，并且可商购。将碳氟化合物与大量惰性气体如氩气一起激发到反应器中的高密度等离子体中，该反应器将等离子体源功率感应耦合到腔室中，并且RF偏压支撑晶片的基座电极。优选地，使用两个两步蚀刻工艺中的一个。首先，源极和偏置功率在蚀刻结束时减小。第二，在主要步骤中使用碳氟化合物以提供良好的垂直分布，并且在过蚀刻中加入更强的聚合碳氟化合物如二氟甲烷（CH 2 F 2）以保护氮化物角。相同的化学成分可用于磁增强反应离子蚀刻剂（MERIE）中，优选具有甚至更大量的氩。

3. 发明授权

US06849193B2 Highly selective process for etching oxide over nitride using hexafluorobutadiene 失效
标题翻译：使用六氟丁二烯在氮化物上蚀刻氧化物的高选择性方法
公开(公告)号：US06849193B2
公开(公告)日：2005-02-01
申请号：US10144635
申请日：2002-05-13
申请人： Hoiman Hung , Joseph P Caulfield , Hongqing Shan , Ruiping Wang , Gerald Zheyao Yin
发明人： Hoiman Hung , Joseph P Caulfield , Hongqing Shan , Ruiping Wang , Gerald Zheyao Yin
IPC分类号： H01L21/311 , H01L21/00
CPC分类号： H01L21/31116
摘要： An oxide etching process, particularly useful for selectively etching oxide over a feature having a non-oxide composition, such as silicon nitride and especially when that feature has a corner that is prone to faceting during the oxide etch. The invention uses a heavy perfluorocarbon, for example, hexafluorobutadiene (C4F6) or hexafluorobenzene (C6F6). The fluorocarbon together with a substantial amount of a noble gas such as argon is excited into a high-density plasma in a reactor which inductively couples plasma source power into the chamber and RF biases the pedestal electrode supporting the wafer. A more strongly polymerizing fluorocarbon such as difluoromethane (CH2F2) is added in the over etch to protect the nitride corner. Oxygen or nitrogen may be added to counteract the polymerization. The same chemistry can be used in a magnetically enhanced reactive ion etcher (MERIE) or with a remote plasma source.
摘要翻译：氧化物蚀刻工艺，特别适用于在具有非氧化物组成的特征（例如氮化硅）上选择性地蚀刻氧化物，特别是当该特征具有在氧化物蚀刻期间易于刻面的拐角时。本发明使用重质全氟化碳，例如六氟丁二烯（C 4 F 6）或六氟苯（C 6 F 6）。将碳氟化合物与大量惰性气体如氩气一起激发到反应器中的高密度等离子体中，该反应器将等离子体源功率感应耦合到腔室中，并且RF偏压支撑晶片的基座电极。在过蚀刻中加入更强烈聚合的碳氟化合物如二氟甲烷（CH 2 F 2）以保护氮化物角。可以加入氧气或氮气以抵抗聚合反应。相同的化学成分可用于磁增强反应离子蚀刻器（MERIE）或远程等离子体源。

4. 发明授权

US07547621B2 LPCVD gate hard mask 失效
标题翻译： LPCVD门硬掩模
公开(公告)号：US07547621B2
公开(公告)日：2009-06-16
申请号：US11492316
申请日：2006-07-25
申请人： Rajesh Kanuri , Chorng-Ping Chang , Christopher Dennis Bencher , Hoiman Hung
发明人： Rajesh Kanuri , Chorng-Ping Chang , Christopher Dennis Bencher , Hoiman Hung
IPC分类号： H01L21/20
CPC分类号： H01L21/32139 , H01L21/02123 , H01L21/02271 , H01L21/02337 , H01L21/31612
摘要： A gate hard mask is deposited on a gate structure using low pressure chemical vapor deposition (LPCVD). By doing so, the wet etch removal ratio (WERR) of the gate hard mask relative to the underlying polysilicon gate layer is increased when compared to prior art hard masks. The LPCVD gate hard mask will not only etch faster than prior art hard masks, but it will also reduce undercutting of the gate oxide. To provide additional control of the wet etch rate, the LPCVD hard mask can be annealed. The annealing can be tailored to achieve the desired etching rate.
摘要翻译：使用低压化学气相沉积（LPCVD）将栅极硬掩模沉积在栅极结构上。通过这样做，与现有技术的硬掩模相比，栅极硬掩模相对于下面的多晶硅栅极层的湿蚀刻去除率（WERR）增加。 LPCVD栅极硬掩模将不仅比现有技术的硬掩模蚀刻更快，而且还将减少栅极氧化物的底切。为了提供对湿蚀刻速率的额外控制，LPCVD硬掩模可被退火。可以定制退火以实现所需的蚀刻速率。

5. 发明授权

US06380096B2 In-situ integrated oxide etch process particularly useful for copper dual damascene 失效
标题翻译：原位一体化氧化物蚀刻工艺特别适用于铜双镶嵌
公开(公告)号：US06380096B2
公开(公告)日：2002-04-30
申请号：US09201590
申请日：1998-11-30
申请人： Hoiman Hung , Joseph P Caulfield , Sum-Yee Betty Tang , Jian Ding , Tianzong Xu
发明人： Hoiman Hung , Joseph P Caulfield , Sum-Yee Betty Tang , Jian Ding , Tianzong Xu
IPC分类号： H01L21302
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/76802 , H01L21/76808 , Y10S438/906 , Y10S438/954
摘要： An integrated in situ oxide etch process particularly useful for a counterbore dual-damascene structure over copper having in one inter-layer dielectric level a lower nitride stop layer, a lower oxide dielectric, a lower nitride stop layer, an upper oxide dielectric layer, and an anti-reflective coating (ARC). The process is divided into a counterbore etch and a trench etch with photolithography for each, and each step is preferably performed in a high-density plasma reactor having an inductively coupled plasma source primarily generating the plasma and a capacitively coupled pedestal supporting the wafer and producing the bias power. The counterbore etch preferably includes at least four substeps of opening the ARC, etching through the upper oxide and nitride layers, selectively etching the lower oxide layer but stopping on the lower nitride layer, and a post-etch treatment for removing residue. The trench etch preferably includes the five substeps of opening the ARC, etching through the upper oxide layer but stopping on the upper nitride layers, a first post-etch treatment for removing residue, a nitride removal of the exposed portions of the upper and lower nitride layers, and a second post-etch treatment for remaining further residues. The oxide etches selective to nitride are accomplished using a fluorocarbon chemistry with high bias and a high temperature for a silicon-based scavenger for fluorine placed next to the plasma. The nitride etches and removal are accomplished by adding an oxygen-containing gas to a fluorocarbon. The final nitride removal is accomplished with very low bias power to increase selectivity to nitride and reduce sputtering of the underlying copper. The post-etch treatments are oxygen plasmas with zero bias power.
摘要翻译：一种集成的原位氧化物蚀刻工艺，特别适用于铜上的沉孔双镶嵌结构，具有一层间电介质层，一层较低的氮化物阻挡层，一层较低的氧化物介电层，一层较低的氮化物阻挡层，抗反射涂层（ARC）。该工艺分别用光刻法分为沉孔蚀刻和沟槽蚀刻，并且每个步骤优选在具有主要产生等离子体的电感耦合等离子体源的高密度等离子体反应器和支撑晶片的电容耦合基座并且产生偏置力。沉孔蚀刻优选包括打开ARC的至少四个子步骤，蚀刻通过上部氧化物和氮化物层，选择性地蚀刻低氧化物层但停止在下部氮化物层上，以及用于去除残留物的蚀刻后处理。沟槽蚀刻优选包括打开ARC的五个子步骤，蚀刻穿过上部氧化物层但停止在上部氮化物层上，第一次蚀刻后处理以除去残余物，去除上部和下部氮化物的暴露部分的氮化物层，以及用于剩余另外的残余物的第二次蚀刻后处理。对氮化物的选择性的氧化物蚀刻是使用氟离子化学方法实现的，该化合物具有高偏压和高温，用于放置在等离子体旁边的用于氟的硅基清除剂。通过向碳氟化合物中加入含氧气体来实现氮化物蚀刻和去除。最终的氮化物去除通过非常低的偏置功率实现，以增加对氮化物的选择性并减少底层铜的溅射。蚀刻后处理是具有零偏压功率的氧等离子体。

6. 发明授权

US06921727B2 Method for modifying dielectric characteristics of dielectric layers 失效
标题翻译：介电层介电特性的修正方法
公开(公告)号：US06921727B2
公开(公告)日：2005-07-26
申请号：US10387160
申请日：2003-03-11
申请人： Kang-Lie Chiang , Mahmoud Dahimene , Xiaoye Zhao , Yan Ye , Gerardo A. Delgadino , Hoiman Hung , Li-Qun Xia , Giuseppina R. Conti
发明人： Kang-Lie Chiang , Mahmoud Dahimene , Xiaoye Zhao , Yan Ye , Gerardo A. Delgadino , Hoiman Hung , Li-Qun Xia , Giuseppina R. Conti
IPC分类号： H01L21/3105 , H01L21/311 , H01L21/768 , H01L21/31 , H01L21/469
CPC分类号： H01L21/31138 , H01L21/3105 , H01L21/31058 , H01L21/31111 , H01L21/31116 , H01L21/31133 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76831
摘要： A method of treating a dielectric layer having a low dielectric constant, where the dielectric layer has been processed in a manner that causes a change in the dielectric constant of an affected region of the layer. The treatment of the affected region may comprise etching, sputtering, annealing, or combinations thereof. The treatment returns the dielectric constant of the dielectric layer to substantially the dielectric constant that existed before processing.
摘要翻译：一种处理具有低介电常数的电介质层的方法，其中介电层已经以导致该层的受影响区域的介电常数变化的方式被处理。受影响区域的处理可以包括蚀刻，溅射，退火或其组合。处理使介电层的介电常数恢复到加工前存在的介电常数。

7. 发明申请

US20080026584A1 LPCVD gate hard mask 失效
标题翻译： LPCVD门硬掩模
公开(公告)号：US20080026584A1
公开(公告)日：2008-01-31
申请号：US11492316
申请日：2006-07-25
申请人： Rajesh Kanuri , Chorng-Ping Chang , Christopher Dennis Bencher , Hoiman Hung
发明人： Rajesh Kanuri , Chorng-Ping Chang , Christopher Dennis Bencher , Hoiman Hung
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/02123 , H01L21/02271 , H01L21/02337 , H01L21/31612
摘要： A gate hard mask is deposited on a gate structure using low pressure chemical vapor deposition (LPCVD). By doing so, the wet etch removal ratio (WERR) of the gate hard mask relative to the underlying polysilicon gate layer is increased when compared to prior art hard masks. The LPCVD gate hard mask will not only etch faster than prior art hard masks, but it will also reduce undercutting of the gate oxide. To provide additional control of the wet etch rate, the LPCVD hard mask can be annealed. The annealing can be tailored to achieve the desired etching rate.
摘要翻译：使用低压化学气相沉积（LPCVD）将栅极硬掩模沉积在栅极结构上。通过这样做，与现有技术的硬掩模相比，栅极硬掩模相对于下面的多晶硅栅极层的湿蚀刻去除率（WERR）增加。 LPCVD栅极硬掩模将不仅比现有技术的硬掩模蚀刻更快，而且还将减少栅极氧化物的底切。为了提供对湿蚀刻速率的额外控制，LPCVD硬掩模可被退火。可以定制退火以实现所需的蚀刻速率。

8. 发明申请

US20060246683A1 Integrated equipment set for forming a low K dielectric interconnect on a substrate 审中-公开
标题翻译：用于在基板上形成低K电介质互连的集成设备
公开(公告)号：US20060246683A1
公开(公告)日：2006-11-02
申请号：US11472662
申请日：2006-06-21
申请人： Judon Pan , Michael Armacost , Hoiman Hung , Hongwen Li , Arulkumar Shanmugasundram , Moshe Sarfaty , Dimitris Lymberopoulos , Mehul Naik
发明人： Judon Pan , Michael Armacost , Hoiman Hung , Hongwen Li , Arulkumar Shanmugasundram , Moshe Sarfaty , Dimitris Lymberopoulos , Mehul Naik
IPC分类号： H01L21/76
CPC分类号： H01L21/67161 , H01L21/67167 , H01L21/67173 , H01L21/67184 , H01L21/67219 , H01L21/6723 , H01L21/67276 , H01L22/20
摘要： A method is provided that includes (1) receiving information about a substrate processed within a low K dielectric deposition subsystem from an integrated inspection system of the low K dielectric deposition subsystem; (2) determining an etch process to perform within an etch subsystem based at least in part on the information received from the inspection system of the low K dielectric deposition subsystem; and (3) directing the etch subsystem to etch at least one low K dielectric layer on the substrate based on the etch process. Other methods, systems, apparatus, data structures and computer program products are provided.
摘要翻译：提供一种方法，其包括（1）从低K电介质沉积子系统的综合检查系统接收关于在低K电介质沉积子系统内处理的衬底的信息; （2）至少部分地基于从低K电介质沉积子系统的检查系统接收的信息来确定在蚀刻子系统内执行的蚀刻工艺; 和（3）引导蚀刻子系统基于蚀刻工艺蚀刻衬底上的至少一个低K电介质层。提供其他方法，系统，设备，数据结构和计算机程序产品。

9. 发明授权

US06762127B2 Etch process for dielectric materials comprising oxidized organo silane materials 失效
标题翻译：包括氧化有机硅烷材料的电介质材料的蚀刻工艺
公开(公告)号：US06762127B2
公开(公告)日：2004-07-13
申请号：US09938432
申请日：2001-08-23
申请人： Yves Pierre Boiteux , Hui Chen , Ivano Gregoratto , Chang-Lin Hsieh , Hoiman Hung , Sum-Yee Betty Tang
发明人： Yves Pierre Boiteux , Hui Chen , Ivano Gregoratto , Chang-Lin Hsieh , Hoiman Hung , Sum-Yee Betty Tang
IPC分类号： H01L21304
CPC分类号： H01L21/76808 , H01L21/02126 , H01L21/02164 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/31116 , H01L21/31633 , H01L21/76802 , H01L21/76807 , H01L2221/1036
摘要： The present invention provides a novel etching technique for etching a layer of C-doped silicon oxide, such as a partially oxidized organo silane material. This technique, employing CH2F2/Ar chemistry at low bias and low to intermediate pressure, provides high etch selectivity to silicon oxide and improved selectivity to organic photoresist. Structures including a layer of partially oxidized organo silane material (1004) deposited on a layer of silicon oxide (1002) were etched according to the novel technique, forming relatively narrow trenches (1010, 1012, 1014, 1016, 1030, 1032, 1034 and 1036) and wider trenches (1020, 1022, 1040 and 1042). The technique is also suitable for forming dual damascene structures (1152, 1154 and 1156). In additional embodiments, manufacturing systems (1410) are provided for fabricating IC structures of the present invention. These systems include a controller (1400) that is adapted for interacting with a plurality of fabricating stations (1420, 1422, 1424, 1426 and 1428).
摘要翻译：本发明提供一种用于蚀刻C掺杂氧化硅层的新颖蚀刻技术，例如部分氧化的有机硅烷材料。这种在低偏压和低至中压下使用CH2F2 / Ar化学的技术为氧化硅提供了高蚀刻选择性，并提高了对有机光致抗蚀剂的选择性。根据新技术蚀刻包括沉积在氧化硅层（1002）上的部分氧化的有机硅烷材料层（1004）的结构，形成相对窄的沟槽（1010,1012,1014,1016,1030,1032,1034和 1036）和较宽的沟槽（1020,1022,1040和1042）。该技术也适用于形成双镶嵌结构（1152,1154和1156）。在另外的实施例中，提供制造系统（1410）用于制造本发明的IC结构。这些系统包括适于与多个制造站（1420,1422,1424,1426和1428）相互作用的控制器（1400）。

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