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1. 发明授权

US6047373A Method and apparatus for setting the operating parameters of a computer system 失效
标题翻译：用于设置计算机系统的操作参数的方法和装置
公开(公告)号：US6047373A
公开(公告)日：2000-04-04
申请号：US940636
申请日：1997-09-30
申请人： Jerald N. Hall , Orville H. Christeson , Mike Kinion , Sean R. Babcock , Frank L. Wildgrube , Frank E. LeClerg , John Yuratovac
发明人： Jerald N. Hall , Orville H. Christeson , Mike Kinion , Sean R. Babcock , Frank L. Wildgrube , Frank E. LeClerg , John Yuratovac
IPC分类号： G06F9/445 , G06F11/14 , G06F13/10 , G06F13/40 , G06F9/00 , G06F9/44
CPC分类号： G06F9/4401 , G06F11/1433 , G06F13/10 , G06F13/4068
摘要： An apparatus includes a configuration selector that is selectively configurable to denote one of a plurality of operating modes for the apparatus, including a configuration mode. The apparatus further comprising a programmable multiplexer, a processor, a bus, and a storage medium having stored therein a basic input/output system (BIOS) equipped to operate in any one of the plurality of operating modes, including the configuration mode wherein the BIOS facilitates user programming of a plurality of operating parameters for the apparatus. The programmable multiplexer, responsive to the configuration selector, asserts a default bus/core ratio common to a plurality of processors and buses that can be employed to form the apparatus when the configuration selector is configured to denote the configuration mode of operation. The processor, coupled to the storage medium and the programmable multiplexer, operates to execute the BIOS, in a speed consistent with the asserted bus/core ratio. The bus, coupled to the programmable multiplexer, the processor and the storage medium, operates to provide instructions and data to the processor, including the BIOS, in a speed consistent with the asserted bus/core ratio.
摘要翻译：一种装置包括配置选择器，其被选择性地配置为表示该设备的多种操作模式中的一种，包括配置模式。该装置还包括可编程多路复用器，处理器，总线和存储介质，其中存储有配置为以多种操作模式中的任一种操作的基本输入/输出系统（BIOS），包括其中BIOS 便于用户编程设备的多个操作参数。响应于配置选择器，可编程多路复用器断言当配置选择器配置为表示配置操作模式时，可以用于形成设备的多个处理器和总线公共的默认总线/内核比。耦合到存储介质和可编程多路复用器的处理器以与断言的总线/内核比率一致的速度操作以执行BIOS。耦合到可编程多路复用器，处理器和存储介质的总线，以与断言的总线/内核比率一致的速度来操作以向处理器（包括BIOS）提供指令和数据。

2. 发明授权

US06256731B1 Method and apparatus for setting the operating parameters of a computer system 有权
标题翻译：用于设置计算机系统的操作参数的方法和装置
公开(公告)号：US06256731B1
公开(公告)日：2001-07-03
申请号：US09440150
申请日：1999-11-15
申请人： Jerald N. Hall , Orville H. Christeson , Mike Kinion , Sean R. Babcock , Frank L. Wildgrube , Frank E. LeClerg , John Yuratovac
发明人： Jerald N. Hall , Orville H. Christeson , Mike Kinion , Sean R. Babcock , Frank L. Wildgrube , Frank E. LeClerg , John Yuratovac
IPC分类号： G06F900
CPC分类号： G06F9/4401 , G06F11/1433 , G06F13/10 , G06F13/4068
摘要： An apparatus includes a configuration selector that is selectively configurable to denote one of a plurality of operating modes for the apparatus, including a configuration mode. The apparatus further comprising a programmable multiplexer, a processor, a bus, and a storage medium having stored therein a basic input/output system (BIOS) equipped to operate in any one of the plurality of operating modes, including the configuration mode wherein the BIOS facilitates user programming of a plurality of operating parameters for the apparatus. The programmable multiplexer, responsive to the configuration selector, asserts a default bus/core ratio common to a plurality of processors and buses that can be employed to form the apparatus when the configuration selector is configured to denote the configuration mode of operation. The processor, coupled to the storage medium and the programmable multiplexer, operates to execute the BIOS, in a speed consistent with the asserted bus/core ratio. The bus, coupled to the programmable multiplexer, the processor and the storage medium, operates to provide instructions and data to the processor, including the BIOS, in a speed consistent with the asserted bus/core ratio.
摘要翻译：一种装置包括配置选择器，其被选择性地配置为表示该设备的多种操作模式中的一种，包括配置模式。该装置还包括可编程多路复用器，处理器，总线和存储介质，其中存储有配置为以多种操作模式中的任一种操作的基本输入/输出系统（BIOS），其包括配置模式，其中BIOS 便于用户编程设备的多个操作参数。响应于配置选择器，可编程多路复用器断言当配置选择器配置为表示配置操作模式时，可以用于形成设备的多个处理器和总线公共的默认总线/内核比。耦合到存储介质和可编程多路复用器的处理器以与断言的总线/内核比率一致的速度操作以执行BIOS。耦合到可编程多路复用器，处理器和存储介质的总线，以与断言的总线/内核比率一致的速度来操作以向处理器（包括BIOS）提供指令和数据。

3. 发明授权

US6122733A Method and apparatus for updating a basic input/output system 失效
标题翻译：用于更新基本输入/输出系统的方法和装置
公开(公告)号：US6122733A
公开(公告)日：2000-09-19
申请号：US941535
申请日：1997-09-30
申请人： Orville H. Christeson , Frank L. Wildgrube , Frank E. LeClerg , Jerald Nevin Hall , Mike Kinion , Sean R. Babcock , John Yuratovac
发明人： Orville H. Christeson , Frank L. Wildgrube , Frank E. LeClerg , Jerald Nevin Hall , Mike Kinion , Sean R. Babcock , John Yuratovac
IPC分类号： G06F9/445 , G06F11/14 , G06F13/10 , G06F13/40
CPC分类号： G06F11/1433 , G06F13/10 , G06F13/4068 , G06F9/4401
摘要： An apparatus includes a storage medium having stored therein a segmented basic input/output system (BIOS) divided among a plurality of segments within the storage medium, and a processor operative to execute the segmented BIOS. In accordance with the teachings of the present invention, the BIOS includes a recovery function that is mode dependent in that while the apparatus is in an update mode the recovery function executes a full reflash of all relevant segments of the segmented BIOS, whereas while the apparatus is in a normal mode the recovery function executes a partial reflash of only identified corrupted BIOS segments.
摘要翻译：一种设备包括存储介质，其中存储有分段的基本输入/输出系统（BIOS），所述基本输入/输出系统（BIOS）被划分为存储介质内的多个段，以及处理器，用于执行分段的BIOS。根据本发明的教导，BIOS包括恢复功能，该恢复功能的模式取决于当设备处于更新模式时，恢复功能执行分段BIOS的所有相关段的完全重新擦除，而在该设备处于正常模式下，恢复功能执行仅识别的损坏的BIOS段的部分刷新。

4. 发明授权

US6089879A Dual-in-line universal serial bus connector 有权
标题翻译：双列直插通用串行总线连接器
公开(公告)号：US6089879A
公开(公告)日：2000-07-18
申请号：US325059
申请日：1999-06-02
申请人： Sean R. Babcock
发明人： Sean R. Babcock
IPC分类号： G06F13/40 , H01R13/648
CPC分类号： G06F13/409
摘要： A dual-in-line Universal Serial Bus (USB) connector including a plurality of USB ports, a plurality of signal pins associated with the ports, and a pair of mounting tabs. The USB connector is adapted for a circuit board including a first footprint for the dual-in-line USB connector situated at a predetermined location of the circuit board. Also, a second footprint is situated at a predetermined location of the circuit board for receipt of a different type of connector instead of the USB connector.
摘要翻译：包括多个USB端口的双列直插通用串行总线（USB）连接器，与端口相关联的多个信号引脚和一对安装接头。 USB连接器适用于包括位于电路板的预定位置处的双列直插USB连接器的第一覆盖区的电路板。此外，第二覆盖区位于电路板的预定位置，用于接收不同类型的连接器而不是USB连接器。

5. 发明授权

US06826100B2 Push button mode automatic pattern switching for interconnect built-in self test 失效
公开(公告)号：US06826100B2
公开(公告)日：2004-11-30
申请号：US10404405
申请日：2003-03-31
申请人： David G. Ellis , Bruce Querbach , Jay J. Nejedlo , Amjad Khan , Sean R. Babcock , Eric S. Gayles , Eshwar Gollapudi
发明人： David G. Ellis , Bruce Querbach , Jay J. Nejedlo , Amjad Khan , Sean R. Babcock , Eric S. Gayles , Eshwar Gollapudi
IPC分类号： G11C700
CPC分类号： G01R31/2853 , G01R31/31855 , G01R31/3187 , G06F11/27
摘要： A built-in self test (BIST) unit, of a primary integrated circuit (IC) component of a computer system, is programmed or hardwired with a test pattern. The test pattern is launched in multiple test cycles, to test an interconnect bus of the computer system or perform a device validation test of the component. A pin assignment of the pattern is automatically changed after each test cycle, without requiring re-programming of the BIST unit to do so.

6. 发明授权

US5954523A Dual-in line universal serial bus connector 失效
标题翻译：双列直插通用串行总线连接器
公开(公告)号：US5954523A
公开(公告)日：1999-09-21
申请号：US959962
申请日：1997-10-24
申请人： Sean R. Babcock
发明人： Sean R. Babcock
IPC分类号： G06F13/40 , H01R13/648
CPC分类号： G06F13/409
摘要： A dual-in-line Universal Serial Bus connector including a plurality of Universal Serial Bus ports oriented adjacent to each other in a longitudinal direction. The dual-in-line Universal Serial Bus connector further includes a plurality of signal pins and a pair of mounting tabs. The signal pins are coupled to the plurality of Universal Serial Bus ports in order to receive data input into at least one of the plurality of Universal Serial Bus ports. The positioning of the mounting tabs and signal pins enable this connector to be used as a substitute for a serial communication (COM) port connector.
摘要翻译：一种双列直插式通用串行总线连接器，包括沿纵向方向彼此相邻定向的多个通用串行总线端口。双列直插通用串行总线连接器还包括多个信号引脚和一对安装片。信号引脚耦合到多个通用串行总线端口，以便接收数据输入到多个通用串行总线端口中的至少一个。安装卡舌和信号引脚的定位可使该连接器用作串行通信（COM）端口连接器的替代品。

7. 发明授权

US07047458B2 Testing methodology and apparatus for interconnects 失效
标题翻译：互连测试方法和设备
公开(公告)号：US07047458B2
公开(公告)日：2006-05-16
申请号：US10319517
申请日：2002-12-16
申请人： Jay Nejedlo , Sean R. Babcock
发明人： Jay Nejedlo , Sean R. Babcock
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G06F11/27 , G01R31/2853 , G01R31/31855 , G01R31/3187
摘要： A built-in self test (IBIST) architecture/methodology is provided for testing the functionality of an interconnect (such as a bus) between two components. This IBIST architecture may include a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.
摘要翻译：提供内置自检（IBIST）架构/方法来测试两个组件之间的互连（如总线）的功能。该IBIST架构可以包括模式生成器和模式检查器。模式检查器操作以将接收到的多个比特（对于模式生成器）与先前存储的多个比特进行比较。

8. 发明授权

US06271704B1 Method and apparatus for balancing current in a system with two sets of termination devices 有权
标题翻译：用于平衡具有两组终端装置的系统中的电流的方法和装置
公开(公告)号：US06271704B1
公开(公告)日：2001-08-07
申请号：US09459854
申请日：1999-12-14
申请人： Sean R. Babcock , Ananda Sarangi
发明人： Sean R. Babcock , Ananda Sarangi
IPC分类号： H03K509
CPC分类号： H04L25/0298
摘要： A method and devices for a current dump circuit that includes a first termination device, a second termination device, and a current dump device. The first termination device resides outside the die of an IC. One end of the first termination device is operatively connected to a first voltage regulator. Another end of the first termination is device operatively connected to a signal line of the IC. The second termination device resides on a die of the IC. One end of the second termination device is operatively connected to a second voltage regulator. Another end of the second termination device is operatively connected to the signal line of the IC. The current dump device provides a path to remove any current flow between the first voltage regulator and the second voltage regulator.
摘要翻译：一种用于当前转储电路的方法和装置，包括第一终端装置，第二终端装置和当前转储装置。第一终端设备位于IC的管芯外部。第一终端装置的一端可操作地连接到第一电压调节器。第一终端的另一端是可操作地连接到IC的信号线的设备。第二终端装置位于IC的管芯上。第二终端装置的一端可操作地连接到第二电压调节器。第二终端装置的另一端可操作地连接到IC的信号线。当前的转储装置提供了去除第一电压调节器和第二电压调节器之间的任何电流的路径。

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