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1. 发明授权

US06436763B1 Process for making embedded DRAM circuits having capacitor under bit-line (CUB) 有权
标题翻译：在位线（CUB）下制造具有电容器的嵌入式DRAM电路的工艺
公开(公告)号：US06436763B1
公开(公告)日：2002-08-20
申请号：US09498738
申请日：2000-02-07
申请人： Jenn Ming Huang , Yu-Hua Lee , Cheng Ming Wu
发明人： Jenn Ming Huang , Yu-Hua Lee , Cheng Ming Wu
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10811 , H01L27/10894 , H01L28/84 , H01L28/90
摘要： A method for fabricating capacitor-under-bit line (CUB) DRAMs with logic circuits is achieved. CUB are better than capacitor-over-bit line (COB) DRAM circuits because of reduced contact aspect ratios, but CUB require patterning the capacitor top plate over the capacitor rough topography while providing openings to bit line contacts between closely spaced capacitors. A bottom antireflecting coating (BARC) is used in a first method; a non-conform PECVD oxide is used in a second method to make reliable high aspect ratio openings between the capacitors. The BARC is deposited to fill the space between capacitors. A photo-resist layer with improved uniformity is then deposited over the BARC and exposed and developed to form an etch mask with improved resolution for the capacitor top plate. The BARC is plasma etched, and the polysilicon plate is patterned. In the second method a non-conformal PECVD oxide is deposited that is thicker on the top of the capacitors than in the narrow space between capacitors. The PECVD oxide is anisotropically etched back to form self-aligned openings over the bit line contacts, and openings are etched in the polysilicon capacitor top plate aligned over the bit line contact openings. A photoresist etch mask is then used to complete the patterning of the top plate.
摘要翻译：实现了具有逻辑电路的用于制造电容器下位线（CUB）DRAM的方法。 CUB比电容器位线（COB）DRAM电路更好，因为接触宽高比减小，但是CUB需要在电容器粗糙的形状图上形成电容器顶板，同时为紧密间隔的电容器之间的位线接触提供开口。在第一种方法中使用底部抗反射涂层（BARC）; 在第二种方法中使用不合格的PECVD氧化物，以在电容器之间形成可靠的高纵横比开口。 BARC存放以填补电容器之间的空间。然后将具有改善的均匀性的光致抗蚀剂层沉积在BARC上，并暴露和显影以形成具有改进的用于电容器顶板的分辨率的蚀刻掩模。 BARC被等离子体蚀刻，多晶硅板被图案化。在第二种方法中，沉积在电容器顶部比在电容器之间的狭窄空间中更厚的非共形PECVD氧化物。 PECVD氧化物被各向异性地回蚀以在位线触点上形成自对准的开口，并且在多晶硅电容器顶板上蚀刻开口，在位线接触开口上对齐。然后使用光致抗蚀剂蚀刻掩模来完成顶板的图案化。

2. 发明授权

US6042999A Robust dual damascene process 失效
标题翻译：坚固的双镶嵌工艺
公开(公告)号：US6042999A
公开(公告)日：2000-03-28
申请号：US73952
申请日：1998-05-07
申请人： Cheng-Tung Lin , Yu-Hua Lee , Jenn Ming Huang , Cheng-Ming Wu
发明人： Cheng-Tung Lin , Yu-Hua Lee , Jenn Ming Huang , Cheng-Ming Wu
IPC分类号： G03F7/00 , H01L21/027 , H01L21/768 , G03F7/26
CPC分类号： H01L21/76808 , G03F7/0035 , H01L21/0276
摘要： A robust dual damascene process is disclosed where the substructure in a substrate is protected from damage caused by multiple etchings required in a damascene process by filling a contact or via hole opening with a protective material prior to the forming of the conductive line opening of the damascene structure having an etch-stop layer separating a lower and an upper dielectric layer. In the first embodiment, the protective material is partially removed from the hole opening reaching the substructure prior to the forming of the upper conductive line opening by etching. In the second embodiment, the protective material in the hole is removed at the same time the upper conductive line opening is formed by etching. In a third embodiment, the disclosed process is applied without the need of an etch-stop layer for the dual damascene process of this invention.
摘要翻译：公开了一种稳健的双镶嵌工艺，其中通过在形成镶嵌导电线开口之前通过填充具有保护材料的接触或通孔开口来保护衬底中的子结构免受由镶嵌工艺中所需的多次蚀刻所造成的损伤具有分隔下电介质层和上电介质层的蚀刻停止层的结构。在第一实施例中，在通过蚀刻形成上导电线开口之前，保护材料部分地从到达底层结构的开孔中去除。在第二实施例中，在通过蚀刻形成上导电线开口的同时去除孔中的保护材料。在第三个实施例中，应用所公开的工艺，而不需要用于本发明的双镶嵌工艺的蚀刻停止层。

3. 发明授权

US06600228B2 Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal rule 有权
标题翻译：顶部金属水平的锁孔预填充光致抗蚀剂，以防止钝化损坏，即使是严重的顶级金属规则
公开(公告)号：US06600228B2
公开(公告)日：2003-07-29
申请号：US09929676
申请日：2001-08-15
申请人： Yu-Hua Lee , Min-Hsiung Chiang , Jenn Ming Huang
发明人： Yu-Hua Lee , Min-Hsiung Chiang , Jenn Ming Huang
IPC分类号： H01L214763
CPC分类号： H01L23/3192 , H01L2924/0002 , H01L2924/00
摘要： A planarized surface of a photoresist layer is formed above a layer formed over a hole in a blanket, conformal, silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device. A blanket, first photoresist layer was formed above the blanket silicon nitride to fill the damage to the surface caused by the hole. Then the first photoresist layer was stripped leaving a residual portion of the first photoresist layer filling the hole. Next, a blanket, second photoresist layer was formed above the blanket layer. The hole has a neck with a width from about 200 Å to about 500 Å and the hole has a deep, pocket-like gap with a cross-section with a width from about 500 Å to about 1200 Å below the narrow neck.
摘要翻译：光致抗蚀剂层的平坦化表面形成在形成在覆盖层中的孔的上方的层上，保形的氮化硅层，其又形成在半导体器件的表面上的SOG层之间的金属化中的锁孔上方。在覆盖氮化硅上方形成毯状的第一光致抗蚀剂层，以填充由孔引起的对表面的损伤。然后剥离第一光致抗蚀剂层，留下填充孔的第一光致抗蚀剂层的残留部分。接下来，在覆盖层上方形成毯状的第二光致抗蚀剂层。该孔具有宽度从大约至大约500埃的颈部，并且该孔具有深的袋状间隙，其横截面的宽度从窄到90度到大约在1200度。

4. 发明授权

US5989954A Method for forming a cylinder capacitor in the dram process 失效
标题翻译：在戏剧过程中形成圆筒电容器的方法
公开(公告)号：US5989954A
公开(公告)日：1999-11-23
申请号：US35056
申请日：1998-03-05
申请人： Yu-Hua Lee , Jenn Ming Huang
发明人： Yu-Hua Lee , Jenn Ming Huang
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method for fabricating a cylindrical capacitor is described. Semiconductor device structures, including a capacitor node contact region, are formed on a semiconductor substrate. A first insulating layer is deposited over the device structures and planarized. A silicon nitride layer and then a second insulating layer are deposited over the first insulating layer. A contact opening having a first width is etched through the insulating layers and the silicon nitride layer to the capacitor node contact region. A photoresist mask is formed over the second insulating layer having a mask opening over the contact opening wherein the mask opening has a second width wider than the first width and wherein photoresist residue remains at the bottom of the contact opening. A second opening is etched in the second insulating layer corresponding to the mask opening wherein the photoresist residue protects the semiconductor substrate within the contact opening during etching. The photoresist mask and residue are removed. A first layer of polysilicon is deposited to fill the contact opening. The first polysilicon layer overlying the second insulating layer is polished away to form the bottom electrode of the capacitor. The second insulating layer is removed. A capacitor dielectric layer is deposited over the silicon nitride layer and the first polysilicon layer. A second polysilicon layer is deposited overlying the capacitor dielectric layer to form the top electrode of the capacitor.
摘要翻译：描述了一种用于制造圆柱形电容器的方法。包括电容器节点接触区域的半导体器件结构形成在半导体衬底上。第一绝缘层沉积在器件结构上并且被平坦化。在第一绝缘层上沉积氮化硅层，然后沉积第二绝缘层。具有第一宽度的接触开口通过绝缘层和氮化硅层蚀刻到电容器节点接触区域。在具有在接触开口上方的掩模开口的第二绝缘层上形成光致抗蚀剂掩模，其中掩模开口具有比第一宽度宽的第二宽度，并且其中光致抗蚀剂残留物保留在接触开口的底部。在对应于掩模开口的第二绝缘层中蚀刻第二开口，其中光致抗蚀剂残留物在蚀刻期间保护接触开口内的半导体衬底。去除光致抗蚀剂掩模和残留物。沉积第一层多晶硅以填充接触开口。覆盖第二绝缘层的第一多晶硅层被抛光以形成电容器的底部电极。去除第二绝缘层。在氮化硅层和第一多晶硅层上沉积电容器介电层。沉积在电容器介电层上的第二多晶硅层以形成电容器的顶部电极。

5. 发明授权

US5854119A Robust method of forming a cylinder capacitor for DRAM circuits 失效
标题翻译：形成用于DRAM电路的圆柱电容器的坚固的方法
公开(公告)号：US5854119A
公开(公告)日：1998-12-29
申请号：US058794
申请日：1998-04-13
申请人： James Wu , Yu-Hua Lee , Jenn Ming Huang
发明人： James Wu , Yu-Hua Lee , Jenn Ming Huang
IPC分类号： H01L21/02 , H01L21/311 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10852 , H01L21/31116 , H01L28/40
摘要： A method of forming a capacitor for DRAM or other circuits is described which avoids the problem of weak spots or gaps forming between a polysilicon contact plug and the first capacitor plate. A layer of first dielectric is formed on a substrate, A layer of second dielectric is formed on the layer of first dielectric. A layer of third dielectric is formed on the layer of second dielectric. A first hole is formed in the first, second, and third dielectrics exposing a contact region of the substrate. The first hole is then filled with a protective material and a second hole is formed in the layer of third dielectric using the layer of second dielectric as an etch stop. The first hole lies within the periphery of the second hole. The protective material prevents re-deposition of the third dielectric. The remaining protective material is then removed and a layer of conducting material is formed on the top surface of the layer of third dielectric, the sidewalls of the second hole, the sidewalls of the first hole, and the contact region of the substrate thereby forming a first capacitor plate.
摘要翻译：描述了形成用于DRAM或其他电路的电容器的方法，其避免了在多晶硅接触插塞和第一电容器板之间形成的弱点或间隙的问题。在基板上形成第一电介质层。在第一电介质层上形成第二电介质层。在第二电介质层上形成第三电介质层。在暴露基板的接触区域的第一，第二和第三电介质中形成第一孔。然后用保护材料填充第一孔，并且使用第二电介质层作为蚀刻停止件在第三电介质层中形成第二孔。第一个孔位于第二个孔的周围。保护材料防止第三电介质的再沉积。然后去除剩余的保护材料，并且在第三电介质层的顶表面，第二孔的侧壁，第一孔的侧壁和衬底的接触区域上形成导电材料层，从而形成第一电容器板。

6. 发明授权

US06294456B1 Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule 有权
标题翻译：使用光刻胶在顶部金属层预填孔眼的方法，以防止钝化损坏，即使是严格的顶级金属规则
公开(公告)号：US06294456B1
公开(公告)日：2001-09-25
申请号：US09200589
申请日：1998-11-27
申请人： Yu-Hua Lee , Min-Hsiung Chiang , Jenn Ming Huang
发明人： Yu-Hua Lee , Min-Hsiung Chiang , Jenn Ming Huang
IPC分类号： H01L214763
CPC分类号： H01L23/3192 , H01L2924/0002 , H01L2924/00
摘要： This is a method of planarizing a surface of a photoresist layer formed above a layer formed over a gap in a blanket silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device. The following steps are performed. Form a blanket, first photoresist layer above the blanket silicon nitride with a damaged surface caused by the gap. Then strip the first photoresist layer leaving a residual portion of the first photoresist layer in the gap. Next, form a blanket, second photoresist layer above the blanket layer. The gap has a neck with a width from about 200 Å to about 500 Å and the gap has a deep, pocket-like cross-section with a width from about 500 Å to about 1,200 Å below the narrow neck. Partial stripping of the first photoresist layer, which follows, is performed by an etching process including wet and dry processing.
摘要翻译：这是在形成在覆盖氮化硅层的间隙上形成的层上形成的光致抗蚀剂层的表面的平面化方法，该覆盖氮化硅层又在半导体器件的表面上的SOG层之间的金属化形成在键孔上方。执行以下步骤。在覆盖氮化硅之上形成一个毯子，第一个光刻胶层，由间隙引起损坏的表面。然后剥离第一光致抗蚀剂层，留下间隙中的第一光致抗蚀剂层的残留部分。接下来，在覆盖层上方形成毯状的第二光致抗蚀剂层。间隙具有宽度从大约至大约500埃的颈部，并且间隙具有深的袋状横截面，宽度在窄的颈部以下从大约500到大约1,200埃。通过包括湿法和干法处理的蚀刻工艺进行随后的第一光致抗蚀剂层的部分剥离。

7. 发明授权

US6100116A Method to form a protected metal fuse 失效
标题翻译：形成保护金属保险丝的方法
公开(公告)号：US6100116A
公开(公告)日：2000-08-08
申请号：US99144
申请日：1998-06-18
申请人： Yu-Hua Lee , James Wu , Jenn Ming Huang , Cheng-Yeh Shih , Min-Hsiung Chiang
发明人： Yu-Hua Lee , James Wu , Jenn Ming Huang , Cheng-Yeh Shih , Min-Hsiung Chiang
IPC分类号： H01L23/525 , H01L21/82
CPC分类号： H01L23/5258 , H01L2924/0002
摘要： A method for forming protection layers completely around a metal fuse to protect the metal fuse 74A and metal lines 74B from moisture corrosion from fuse opening and micro-cracks in dielectric layers. The invention surrounds the fuse on all sides with two protection layers: a bottom protection layer 70 and a top protection layer 78. The top protection layer 78 is formed over the fuse metal, the sidewalls of the metal fuse and the bottom protection layer 70. The protection layers 70 78 of the invention form a moisture proof seal structure around the metal fuse 74A and protect the metal fuse 74A and metal lines 74B from moisture and contaminates.
摘要翻译：一种用于在金属保险丝周围完全形成保护层的方法，用于保护金属保险丝74A和金属线74B免受保险丝开口的湿度腐蚀和电介质层中的微裂纹。本发明在所有侧面上具有两个保护层的保险丝：底部保护层70和顶部保护层78.顶部保护层78形成在熔丝金属，金属熔断器的侧壁和底部保护层70上。本发明的保护层70 78在金属熔断器74A周围形成防潮密封结构，并且保护金属熔断器74A和金属线74B免受潮湿和污染。

8. 发明授权

US06579784B1 Method for forming a metal gate integrated with a source and drain salicide process with oxynitride spacers 有权
标题翻译：用氮氧化物间隔物形成与源极和排水硅化物工艺一体化的金属栅的方法
公开(公告)号：US06579784B1
公开(公告)日：2003-06-17
申请号：US09419511
申请日：1999-10-18
申请人： Jenn Ming Huang
发明人： Jenn Ming Huang
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28044 , H01L21/28518 , H01L21/76838 , H01L29/66545
摘要： A method of forming a metal gate integrated with a salicide process on the source and drain regions. A gate dielectric layer and polysilicon/silicon dioxide/silicon nitride dummy gate layers are formed over a substrate structure and patterned to form dummy structures, comprising at least one dummy gate structure. Lightly doped source and drain regions, sidewall spacers, and source and drain regions are formed adjacent to the dummy gate structure. A silicide layer is formed on the source and drain regions by depositing titanium/titanium nitride, performing a rapid thermal anneal, selectively removing unreacted titanium/titanium nitride using NH4OH, and performing a second rapid thermal anneal. A blanket dielectric layer is formed over the dummy structures. The blanket dielectric layer, the spacers and the silicon nitride layer of the dummy structures are planarized using a chemical mechanical polishing process. The silicon nitride layer and the silicon dioxide layer of the dummy structures are removed. A titanium nitride layer is formed over the polysilicon layer of the dummy structures, and a tungsten layer is deposited over the titanium nitride layer. The tungsten layer and titanium nitride layer are planarized using a chemical mechanical polishing process, thereby forming polysilicon/titanium nitride/tungsten structures.
摘要翻译：在源极和漏极区域上形成与自对准硅化物工艺集成的金属栅极的方法。栅介质层和多晶硅/二氧化硅/氮化硅虚拟栅极层形成在衬底结构之上并被图案化以形成包括至少一个虚拟栅极结构的虚设结构。在虚拟栅极结构附近形成轻掺杂源极和漏极区域，侧壁间隔物以及源极和漏极区域。通过沉积钛/氮化钛，进行快速热退火，使用NH 4 OH选择性除去未反应的钛/氮化钛，并进行第二快速热退火，在源区和漏区上形成硅化物层。在虚拟结构上形成有覆盖层的介电层。使用化学机械抛光工艺将哑结构的覆盖层介电层，间隔物和氮化硅层平坦化。去除了氮化硅层和虚拟结构的二氧化硅层。在虚设结构的多晶硅层上形成氮化钛层，在氮化钛层上沉积钨层。使用化学机械抛光工艺将钨层和氮化钛层平坦化，从而形成多晶硅/氮化钛/钨结构。

9. 发明授权

US06251726B1 Method for making an enlarged DRAM capacitor using an additional polysilicon plug as a center pillar 有权
标题翻译：使用附加的多晶硅插塞作为中心柱来制造放大的DRAM电容器的方法
公开(公告)号：US06251726B1
公开(公告)日：2001-06-26
申请号：US09489495
申请日：2000-01-21
申请人： Jenn Ming Huang
发明人： Jenn Ming Huang
IPC分类号： H01L21336
CPC分类号： H01L27/10894 , H01L27/10855 , H01L27/10888 , H01L28/84 , H01L28/91
摘要： A method is provided for making capacitors for future high density circuits. The method increases capacitance while reducing the difficulty in etching the high aspect ratio holes for the capacitor node contacts. After FETs are formed in device areas, a first insulator is deposited and first contact openings are etched for the capacitor node contact. First polysilicon (polySi) plugs are formed in the first contact openings. An etch-stop layer and a second insulating layer are deposited. Second contact openings are aligned over and etched in the second insulating layer to the first polySi plugs. Second polySi plugs are formed in the second contact openings. Openings for capacitors, aligned over and wider than the second polySi plug, are etched in the second insulating layer. The capacitors are completed by forming bottom electrodes with a thin dielectric layer in the capacitor openings and forming a top electrode. This two polysi plug method reduces the need to etch a single high aspect ratio (deep) contacts holes. The second polysi plug also serves as a pillar for increased capacitance. The second contact openings and capacitor openings are etched using a very controllable etch to the etch-stop layer without disturbing the underlying DRAM structure. This allows capacitor design changes for future product generation beyond 0.25 um.
摘要翻译：提供了一种为将来的高密度电路制造电容器的方法。该方法增加了电容，同时降低了蚀刻用于电容器节点触点的高纵横比孔的难度。在器件区域中形成FET之后，沉积第一绝缘体并蚀刻电容器节点接触的第一接触开口。在第一接触开口中形成第一多晶硅（polySi）插头。沉积蚀刻停止层和第二绝缘层。第二接触开口对准并在第二绝缘层中蚀刻到第一多晶硅插塞。在第二接触开口中形成第二多晶硅塞。在第二绝缘层中蚀刻用于比第二多晶硅插塞更宽且宽的电容器开口。通过在电容器开口中形成具有薄介电层的底部电极并形成顶部电极来完成电容器。这两种多芯插头方法减少了蚀刻单个高宽比（深）接触孔的需要。第二个聚合物塞还用作增加电容的支柱。使用对蚀刻停止层的非常可控的蚀刻蚀刻第二接触开口和电容器开口，而不会干扰下面的DRAM结构。这允许电容器设计更改，以便将来的产品生成超过0.25um。

10. 发明授权

US06235593B1 Self aligned contact using spacers on the ILD layer sidewalls 有权
标题翻译：在ILD层侧壁上使用间隔物进行自对准接触
公开(公告)号：US06235593B1
公开(公告)日：2001-05-22
申请号：US09252628
申请日：1999-02-18
申请人： Jenn Ming Huang
发明人： Jenn Ming Huang
IPC分类号： H01L218242
CPC分类号： H01L21/76897
摘要： A method for a self-aligned contact (SAC) that forms top and bottom spacers on the sidewalls of the interlevel dielectric layer. Spaced gate structures are formed between said spaced isolation regions. The gate structure is comprised of a gate oxide layer; a conductive layer; a cap layer. Lightly doped drain regions (LDD) are formed. An interlevel dielectric (ILD) layer is formed. A contact hole is etched that exposes the LDD region between the gate structures and removes a portion of the cap layer. An interlevel dielectric spacer layer is formed over the interlevel dielectric layer, the sidewalls of the contact hole and on the LDD region. In a key step, the interlevel dielectric spacer layer is anisotropically etched forming a top spacer on the sidewalls of the upper opening and a bottom spacer on the lower opening. A contact plug is formed to fill the contact hole and electrically contacting the LDD region. The invention also forms borderless contact hole spacers. The invention's IDL spacers can be thinner than conventional spacers and allow better gap filling for the contact plug.
摘要翻译：一种用于在层间电介质层的侧壁上形成顶部和底部间隔物的自对准接触（SAC）的方法。在所述间隔开的隔离区域之间形成间隔栅极结构。栅极结构由栅极氧化物层组成; 导电层; 盖层。形成轻掺杂漏极区（LDD）。形成层间电介质（ILD）层。蚀刻接触孔，使栅极结构之间的LDD区域露出，并移除盖层的一部分。在层间电介质层，接触孔的侧壁和LDD区上形成层间电介质间隔层。在关键步骤中，层间电介质间隔层被各向异性地蚀刻，形成在上开口的侧壁上的顶部间隔物和下开口的底部间隔物。形成接触插塞以填充接触孔并与LDD区域电接触。本发明还形成无边界接触孔间隔物。本发明的IDL间隔物可以比常规间隔物更薄，并且允许接触插塞更好的间隙填充。

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