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1. 发明申请

US20070247200A1 Frequency Independent Control 有权
标题翻译：频率独立控制
公开(公告)号：US20070247200A1
公开(公告)日：2007-10-25
申请号：US11769071
申请日：2007-06-27
申请人： Jeffrey Zachan , Geoff Hatcher , Edward Youssoufian
发明人： Jeffrey Zachan , Geoff Hatcher , Edward Youssoufian
IPC分类号： H03L7/06
CPC分类号： H03L7/0898 , H03L7/0893 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/1072 , H03L7/187
摘要： A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control signal and a square root module configured to receive state information, the state information corresponding to tuning information, the square root module further configured to multiply the control signal by a square root of the state information to provide a tuning signal.
摘要翻译：公开了锁相环（PLL）。一个实施例包括提供控制信号的PLL和被配置为接收状态信息的平方根模块，对应于调谐信息的状态信息，平方根模块还被配置为将控制信号乘以状态信息以提供调谐信号。

2. 发明申请

US20060158235A1 Phase-locked loops 有权
标题翻译：锁相环
公开(公告)号：US20060158235A1
公开(公告)日：2006-07-20
申请号：US11385181
申请日：2006-03-21
申请人： Jeffrey Zachan , Geoff Hatcher , Edward Youssoufian
发明人： Jeffrey Zachan , Geoff Hatcher , Edward Youssoufian
IPC分类号： H03L7/06
CPC分类号： H03L7/0898 , H03L7/0893 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/1072 , H03L7/187
摘要： A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control signal and a square root module configured to receive state information, the state information corresponding to tuning information, the square root module further configured to multiply the control signal by a square root of the state information to provide a tuning signal.
摘要翻译：公开了锁相环（PLL）。一个实施例包括提供控制信号的PLL和被配置为接收状态信息的平方根模块，对应于调谐信息的状态信息，平方根模块还被配置为将控制信号乘以状态信息以提供调谐信号。

3. 发明授权

US07576614B2 Frequency independent control 有权
标题翻译：频率独立控制
公开(公告)号：US07576614B2
公开(公告)日：2009-08-18
申请号：US11769071
申请日：2007-06-27
申请人： Jeffrey Zachan , Geoff Hatcher , Edward Youssoufian
发明人： Jeffrey Zachan , Geoff Hatcher , Edward Youssoufian
IPC分类号： H03L7/00
CPC分类号： H03L7/0898 , H03L7/0893 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/1072 , H03L7/187
摘要： A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control signal and a square root module configured to receive state information, the state information corresponding to tuning information, the square root module further configured to multiply the control signal by a square root of the state information to provide a tuning signal.
摘要翻译：公开了锁相环（PLL）。一个实施例包括提供控制信号的PLL和被配置为接收状态信息的平方根模块，对应于调谐信息的状态信息，平方根模块还被配置为将控制信号乘以状态信息以提供调谐信号。

4. 发明申请

US20050258907A1 Phase-locked loops 有权
标题翻译：锁相环
公开(公告)号：US20050258907A1
公开(公告)日：2005-11-24
申请号：US10849266
申请日：2004-05-19
申请人： Jeffrey Zachan , Geoff Hatcher , Edward Youssoufian
发明人： Jeffrey Zachan , Geoff Hatcher , Edward Youssoufian
IPC分类号： H03L7/00 , H03L7/089 , H03L7/093 , H03L7/107 , H03L7/187
CPC分类号： H03L7/0898 , H03L7/0893 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/1072 , H03L7/187
摘要： A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control current and varies the control current in proportion to an inverse of N squared. N is the ratio of the output frequency of the PLL system to the reference frequency of the PLL system. The varying of the control current compensates for bandwidth changes of the PLL system.
摘要翻译：公开了锁相环（PLL）。其中一个实施例包括提供控制电流的PLL，并且与N平方的倒数成比例地改变控制电流。 N是PLL系统的输出频率与PLL系统的参考频率的比率。控制电流的变化补偿了PLL系统的带宽变化。

5. 发明授权

US07256629B2 Phase-locked loops 有权
标题翻译：锁相环
公开(公告)号：US07256629B2
公开(公告)日：2007-08-14
申请号：US11385181
申请日：2006-03-21
申请人： Jeffrey M. Zachan , Geoff Hatcher , Edward Youssoufian
发明人： Jeffrey M. Zachan , Geoff Hatcher , Edward Youssoufian
IPC分类号： H03L7/06
CPC分类号： H03L7/0898 , H03L7/0893 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/1072 , H03L7/187
摘要： A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control signal and a square root module configured to receive state information, the state information corresponding to tuning information, the square root module further configured to multiply the control signal by a square root of the state information to provide a tuning signal.
摘要翻译：公开了锁相环（PLL）。一个实施例包括提供控制信号的PLL和被配置为接收状态信息的平方根模块，对应于调谐信息的状态信息，平方根模块还被配置为将控制信号乘以状态信息以提供调谐信号。

6. 发明授权

US07138839B2 Phase-locked loops 有权
标题翻译：锁相环
公开(公告)号：US07138839B2
公开(公告)日：2006-11-21
申请号：US10849266
申请日：2004-05-19
申请人： Jeffrey M. Zachan , Geoff Hatcher , Edward Youssoufian
发明人： Jeffrey M. Zachan , Geoff Hatcher , Edward Youssoufian
IPC分类号： H03L7/06
CPC分类号： H03L7/0898 , H03L7/0893 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/1072 , H03L7/187
摘要： A phase-locked loop (PLL) is disclosed. One embodiment, among others, includes a PLL that provides a control current and varies the control current in proportion to an inverse of N squared. N is the ratio of the output frequency of the PLL system to the reference frequency of the PLL system. The varying of the control current compensates for bandwidth changes of the PLL system.
摘要翻译：公开了锁相环（PLL）。其中一个实施例包括提供控制电流的PLL，并且与N平方的倒数成比例地改变控制电流。 N是PLL系统的输出频率与PLL系统的参考频率的比率。控制电流的变化补偿了PLL系统的带宽变化。

7. 发明授权

US08005449B2 Subsampling wideband RSSI circuit 有权
标题翻译：二次采样宽带RSSI电路
公开(公告)号：US08005449B2
公开(公告)日：2011-08-23
申请号：US12136864
申请日：2008-06-11
申请人： Edward Youssoufian , Amr Fahim
发明人： Edward Youssoufian , Amr Fahim
IPC分类号： H04B17/00
CPC分类号： H04B1/1027 , H04B17/318
摘要： A Received Signal Strength Indicator (RSSI) circuit includes a subsampling circuit that processes an input signal comprising a sampling frequency, fs, wherein the subsampling circuit subsamples the input signal, wherein the input signal is subsampled to concentrate a power in a narrow bandwidth; an analog-to-digital converter (ADC) operatively connected to the subsampling circuit, wherein the ADC digitizes the subsampled signal; and a baseband detector operatively connected to the ADC, wherein the baseband detector detects a power from the digitized subsampled signal and creates an output signal. The subsampling circuit and the ADC may operate as a single subsampling ADC. The RSSI circuit may further comprise ignoring higher order aliases at a multiple of the sampling frequency if the baseband detector is clocked at the sampling frequency.
摘要翻译：接收信号强度指示器（RSSI）电路包括子采样电路，其处理包括采样频率fs的输入信号，其中所述子采样电路对所述输入信号进行子采样，其中所述输入信号被二次采样以集中在窄带宽中的功率; 模数转换器（ADC），其可操作地连接到所述子采样电路，其中所述ADC对所述子采样信号进行数字化; 以及可操作地连接到ADC的基带检测器，其中基带检测器检测来自数字化的二次采样信号的功率并产生输出信号。子采样电路和ADC可以作为单个子采样ADC工作。如果基带检测器以采样频率计时，则RSSI电路还可以包括以采样频率的倍数忽略较高阶别名。

8. 发明授权

US07973861B2 Universal tuner for mobile TV 有权
标题翻译：通用调谐器用于手机电视
公开(公告)号：US07973861B2
公开(公告)日：2011-07-05
申请号：US11737222
申请日：2007-04-19
申请人： Mohy Abdelgany , Frank Carr , Hassan Elwan , Amr Fahim , Edward Youssoufian
发明人： Mohy Abdelgany , Frank Carr , Hassan Elwan , Amr Fahim , Edward Youssoufian
IPC分类号： H04N5/50
CPC分类号： H04N5/50 , H03D3/007 , H03J1/005 , H04N21/41407
摘要： A tuner for use in mobile television devices comprises at least one RF front end component comprising a LNA adapted to amplify mobile television signals; a PLL circuit to generate signals; and a pair of mixers to receive the signals from the LNA and the PLL circuit and downconvert the signals; an analog baseband component connected to the RF front end component, wherein the analog baseband component comprises I and Q channel signal paths each comprising a tunable high order impedance filter; at least one signal amplification stage; and a signal filter stage connected to the signal amplification stage, wherein the analog baseband component further comprises a plurality of switches operatively connected to the I and Q channel signal paths, and wherein the plurality of switches are selectively opened and closed in multiple configurations in order to allow the tuner to receive mobile TV signals for all mobile TV standards.
摘要翻译：用于移动电视设备的调谐器包括至少一个RF前端组件，其包括适于放大移动电视信号的LNA; 用于产生信号的PLL电路; 和一对混频器，用于接收来自LNA和PLL电路的信号，并对信号进行下变频; 连接到所述RF前端组件的模拟基带组件，其中所述模拟基带组件包括每个包括可调谐高阶阻抗滤波器的I和Q信道信号路径; 至少一个信号放大级; 以及信号滤波器级，其连接到所述信号放大级，其中所述模拟基带分量还包括可操作地连接到所述I和Q通道信号路径的多个开关，并且其中所述多个开关按照多个配置选择性地打开和关闭以允许调谐器接收所有移动电视标准的移动电视信号。

9. 发明申请

US20090311985A1 SUBSAMPLING WIDEBAND RSSI CIRCUIT 有权
标题翻译： SUBSAMPLING宽带RSSI电路
公开(公告)号：US20090311985A1
公开(公告)日：2009-12-17
申请号：US12136864
申请日：2008-06-11
申请人： Edward Youssoufian , Amr Fahim
发明人： Edward Youssoufian , Amr Fahim
IPC分类号： H04B17/00
CPC分类号： H04B1/1027 , H04B17/318
摘要： A Received Signal Strength Indicator (RSSI) circuit includes a subsampling circuit that processes an input signal comprising a sampling frequency, fs, wherein the subsampling circuit subsamples the input signal, wherein the input signal is subsampled to concentrate a power in a narrow bandwidth; an analog-to-digital converter (ADC) operatively connected to the subsampling circuit, wherein the ADC digitizes the subsampled signal; and a baseband detector operatively connected to the ADC, wherein the baseband detector detects a power from the digitized subsampled signal and creates an output signal. The subsampling circuit and the ADC may operate as a single subsampling ADC. The RSSI circuit may further comprise ignoring higher order aliases at a multiple of the sampling frequency if the baseband detector is clocked at the sampling frequency.
摘要翻译：接收信号强度指示器（RSSI）电路包括子采样电路，其处理包括采样频率fs的输入信号，其中所述子采样电路对所述输入信号进行子采样，其中所述输入信号被二次采样以集中在窄带宽中的功率; 模数转换器（ADC），可操作地连接到所述子采样电路，其中所述ADC对所述子采样信号进行数字化; 以及可操作地连接到ADC的基带检测器，其中基带检测器检测来自数字化的二次采样信号的功率并产生输出信号。子采样电路和ADC可以作为单个子采样ADC工作。如果基带检测器以采样频率计时，则RSSI电路还可以包括以采样频率的倍数忽略较高阶别名。

10. 发明申请

US20070218855A1 System and method for performing RF filtering 审中-公开
标题翻译：执行射频滤波的系统和方法
公开(公告)号：US20070218855A1
公开(公告)日：2007-09-20
申请号：US11377721
申请日：2006-03-16
申请人： Aly Ismail , Edward Youssoufian , Hassan Elwan , Frank Carr
发明人： Aly Ismail , Edward Youssoufian , Hassan Elwan , Frank Carr
IPC分类号： H04B1/26
CPC分类号： H04B1/30 , H03D7/1441 , H03D7/1466 , H03D7/1483 , H03D7/165
摘要： A method of filtering and a RF filtering circuit comprising a LO adapted to generate in-phase and quadrature LO baseband signals; a quadrature passive mixer operatively connected to the LO; a filtering impedance operatively connected to the quadrature passive mixer, wherein the voltage at an input node of the quadrature passive mixer comprises the voltage across the filtering impedance up-converted to a frequency of a LO baseband signal received by the quadrature passive mixer. Preferably, the voltage across the filtering impedance comprises a frequency of an input signal of the quadrature passive mixer down-converted by a frequency of the in-phase and quadrature LO baseband signals and filtered by the filtering impedance.
摘要翻译：一种滤波方法和RF滤波电路，包括适于产生同相和正交LO基带信号的LO; 可操作地连接到LO的正交无源混频器; 滤波阻抗可操作地连接到正交无源混频器，其中正交无源混频器的输入节点处的电压包括上变频到由正交无源混频器接收的LO基带信号的频率的滤波阻抗上的电压。优选地，滤波阻抗两端的电压包括被同相和正交LO基带信号的频率下变频的正交无源混频器的输入信号的频率，并被滤波阻抗滤波。

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