专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07202114B2 On-chip structure for electrostatic discharge (ESD) protection 失效
标题翻译：用于静电放电（ESD）保护的片上结构
公开(公告)号：US07202114B2
公开(公告)日：2007-04-10
申请号：US11032154
申请日：2005-01-11
申请人： Javier A. Salcedo , Juin J. Liou , Joseph C. Bernier , Donald K. Whitney, Jr.
发明人： Javier A. Salcedo , Juin J. Liou , Joseph C. Bernier , Donald K. Whitney, Jr.
IPC分类号： H01L29/72 , H01L29/74 , H01L31/111
CPC分类号： H01L27/0262 , H01L29/7436
摘要： A complementary SCR-based structure enables a tunable holding voltage for robust and versatile ESD protection. The structure are n-channel high-holding-voltage low-voltage-trigger silicon controller rectifier (N-HHLVTSCR) device and p-channel high-holding-voltage low-voltage-trigger silicon controller rectifier (P-HHLVTSCR) device. The regions of the N-HHLVTSCR and P-HHLVTSCR devices are formed during normal processing steps in a CMOS or BICMOS process. The spacing and dimensions of the doped regions of N-HHLVTSCR and P-HHLVTSCR devices are used to produce the desired characteristics. The tunable HHLVTSCRs makes possible the use of this protection circuit in a broad range of ESD applications including protecting integrated circuits where the I/O signal swing can be either within the range of the bias of the internal circuit or below/above the range of the bias of the internal circuit.
摘要翻译：互补的基于SCR的结构使得可调谐的保持电压具有稳健和通用的ESD保护。结构是n沟道高保持电压低压触发硅控整流器（N-HHLVTSCR）器件和p沟道高保持电压低压触发硅控整流器（P-HHLVTSCR）器件。 N-HHLVTSCR和P-HHLVTSCR器件的区域在CMOS或BICMOS工艺的正常处理步骤期间形成。使用N-HHLVTSCR和P-HHLVTSCR器件的掺杂区域的间距和尺寸来产生所需的特性。可调谐的HHLVTSCR可以在广泛的ESD应用中使用该保护电路，包括保护集成电路，其中I / O信号摆幅可以在内部电路的偏置范围内或低于/高于内部电路的偏置。

2. 发明申请

US20090261378A1 DEVICES WITH ADJUSTABLE DUAL-POLARITY TRIGGER - AND HOLDING-VOLTAGE/CURRENT FOR HIGH LEVEL OF ELECTROSTATIC DISCHARGE PROTECTION IN SUB-MICRON MIXED SIGNAL CMOS/BICMOS INTEGRATED 有权
标题翻译：具有可调双极性触发器的器件 - 并保持电压/电流用于低分辨率混合信号中的静电放电保护CMOS / BICMOS集成
公开(公告)号：US20090261378A1
公开(公告)日：2009-10-22
申请号：US12420264
申请日：2009-04-08
申请人： Javier A. SALCEDO , Juin J. Liou , Joseph C. Bernier , Donald K. Whitney
发明人： Javier A. SALCEDO , Juin J. Liou , Joseph C. Bernier , Donald K. Whitney
IPC分类号： H01L29/74 , H01L21/30
CPC分类号： H01L27/0262 , H01L29/87
摘要： Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1—N2—P2—N1//N1—P3—N3—P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC). The ESD protection cells are tested using the TLP (Transmission Line Pulse) technique, and ESD standards including HBM (Human Body Model), MM (Machine Model), and IEC (International Electrotechnical Commission) IEC 1000-4-2_standard for ESD immunity. ESD protection performance is demonstrated also at high temperature (140° C.). The unique high ratio of dual-polarity ESD protection level per unit area, allows for integration of fast-response and compact protection cells optimized for the current tendency of the semiconductor industry toward low cost and high density-oriented IC design. Symmetric/asymmetric dual polarity ESD protection performance is demonstrated for over 15 kV HBM, 2 kV MM, and 16.5 kV IEC for sub-micron technology.
摘要翻译：通过定制实现，先进的亚微米硅化CMOS（互补金属氧化物半导体）/ BiCMOS（双极CMOS）技术获得具有10 V至40 V以上触发电压和相对较高保持电流的对称/非对称双向S形IV特性具有嵌入镇流电阻58,58A，56,56A和外围保护环隔离88-86的P1-N2-P2-N1 // N1-P3-N3-P1侧向结构。双向保护装置为高级CMOS / BiCMOS工艺提供高水平的静电放电（ESD）抗扰性，无闩锁问题。 ESD保护单元的新型设计适配多功能354 /互指向336布局方案允许放大保护结构的ESD性能和定制集成，而IV特性480可调整到集成电路（IC）的工作条件，。 ESD保护电池使用TLP（传输线脉冲）技术和ESD标准测试，包括HBM（人体模型），MM（机器模型）和IEC（国际电工委员会）IEC 1000-4-2标准的ESD抗扰度。 ESD保护性能也在高温（140°C）下得到证明。单位面积双极性ESD保护水平的独特高比例，可实现半导体行业针对低成本和高密度导向IC设计优化的快速响应和紧凑型保护单元的集成。针对超低于15 kV HBM，2 kV MM和16.5 kV IEC的亚微米技术，可以证明对称/非对称双极性ESD保护性能。

3. 发明授权

US07566914B2 Devices with adjustable dual-polarity trigger- and holding-voltage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated circuits 失效
标题翻译：具有可调双极触发和保持电压/电流的器件，用于亚微米混合信号CMOS / BiCMOS集成电路中的高电平静电放电保护
公开(公告)号：US07566914B2
公开(公告)日：2009-07-28
申请号：US11289390
申请日：2005-11-30
申请人： Javier A. Salcedo , Juin J. Liou , Joseph C. Bernier , Donald K. Whitney
发明人： Javier A. Salcedo , Juin J. Liou , Joseph C. Bernier , Donald K. Whitney
IPC分类号： H01L29/74 , H01L31/111 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L27/0262 , H01L29/87
摘要： Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1-N2-P2-N1//N1-P3-N3-P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC). The ESD protection cells are tested using the TLP (Transmission Line Pulse) technique, and ESD standards including HBM (Human Body Model), MM (Machine Model), and IEC (International Electrotechnical Commission) IEC 1000-4-2 standard for ESD immunity. ESD protection performance is demonstrated also at high temperature (140° C.). The unique high ratio of dual-polarity ESD protection level per unit area, allows for integration of fast-response and compact protection cells optimized for the current tendency of the semiconductor industry toward low cost and high density-oriented IC design. Symmetric/asymmetric dual polarity ESD protection performance is demonstrated for over 15 kV HBM, 2 kV MM, and 16.5 kV IEC for sub-micron technology.
摘要翻译：通过定制实现，先进的亚微米硅化CMOS（互补金属氧化物半导体）/ BiCMOS（双极CMOS）技术获得具有10 V至40 V以上触发电压和相对较高保持电流的对称/非对称双向S形IV特性具有嵌入镇流电阻58,58A，56,56A和外围保护环隔离88-86的P1-N2-P2-N1 // N1-P3-N3-P1侧向结构。双向保护装置为高级CMOS / BiCMOS工艺提供高水平的静电放电（ESD）抗扰性，无闩锁问题。 ESD保护单元的新型设计适配多功能354 /互指向336布局方案允许放大保护结构的ESD性能和定制集成，而IV特性480可调整到集成电路（IC）的工作条件，。 ESD保护电池使用TLP（传输线脉冲）技术和ESD标准测试，包括HBM（人体模型），MM（机器模型）和IEC（国际电工委员会）IEC 1000-4-2 ESD抗扰度标准。 ESD保护性能也在高温（140°C）下得到证明。单位面积双极性ESD保护水平的独特高比例，可实现半导体行业针对低成本和高密度导向IC设计优化的快速响应和紧凑型保护单元的集成。针对超低于15 kV HBM，2 kV MM和16.5 kV IEC的亚微米技术，可以证明对称/非对称双极性ESD保护性能。

4. 发明授权

US07479414B2 Electrostatic discharge protection device for digital circuits and for applications with input/output bipolar voltage much higher than the core circuit power supply 失效
标题翻译：用于数字电路的静电放电保护装置和输入/输出双极性电压远高于核心电路电源的应用
公开(公告)号：US07479414B2
公开(公告)日：2009-01-20
申请号：US11871269
申请日：2007-10-12
申请人： Javier A. Salcedo , Juin J. Liou , Joseph C. Bernier , Donald K. Whitney
发明人： Javier A. Salcedo , Juin J. Liou , Joseph C. Bernier , Donald K. Whitney
IPC分类号： H01L21/332
CPC分类号： H01L29/7436 , H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) device and method is provided. The ESD device can comprise a substrate doped to a first conductivity type, an epitaxial region doped to the second conductivity type, and a first well doped to the first conductivity type disposed in the substrate. The first well can comprise a first region doped to the first conductivity type, a second region doped to a second conductivity type, and a first isolation region disposed between the first region and the second region. The ESD device can also comprise a second well doped to a second conductivity type disposed in the substrate adjacent to the first well, where the second well can comprise a third region doped to the first conductivity type, a fourth region doped to the second conductivity type, and a second isolation region disposed between the third region and the fourth region. Still further, the ESD device can include a first trigger contact and second trigger contact comprising highly doped regions of either conductivity type, the first trigger contact disposed at a junction between the first well and the second well, and the second trigger contact disposed at either well.
摘要翻译：提供了静电放电（ESD）装置和方法。 ESD器件可以包括掺杂到第一导电类型的衬底，掺杂到第二导电类型的外延区域，以及掺杂到设置在衬底中的第一导电类型的第一阱。第一阱可以包括掺杂到第一导电类型的第一区域，掺杂到第二导电类型的第二区域和设置在第一区域和第二区域之间的第一隔离区域。 ESD器件还可以包括掺杂到邻近第一阱的衬底中的第二导电类型的第二阱，其中第二阱可以包括掺杂到第一导电类型的第三区域，掺杂到第二导电类型的第四区域以及设置在第三区域和第四区域之间的第二隔离区域。此外，ESD装置可以包括第一触发触点和第二触发触点，其包括导电类型的高掺杂区域，第一触发触点设置在第一阱和第二阱之间的接合处，第二触发触点设置在任一个好。

5. 发明授权

US08283695B2 Devices with adjustable dual-polarity trigger- and holding-votage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated 失效
标题翻译：具有可调双极触发和保持电流的器件，用于亚微米混合信号CMOS / BiCMOS集成中的高电平静电放电保护
公开(公告)号：US08283695B2
公开(公告)日：2012-10-09
申请号：US13114895
申请日：2011-05-24
申请人： Javier A. Salcedo , Juin J. Liou , Joseph C. Bernier , Donald K. Whitney
发明人： Javier A. Salcedo , Juin J. Liou , Joseph C. Bernier , Donald K. Whitney
IPC分类号： H01L29/74 , H01L31/111 , H01L27/10 , H01L23/62
CPC分类号： H01L27/0262 , H01L29/87
摘要： Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1-N2-P2-N1//N1-P3-N3-P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC). The ESD protection cells are tested using the TLP (Transmission Line Pulse) technique, and ESD standards including HBM (Human Body Model), MM (Machine Model), and IEC (International Electrotechnical Commission) IEC 1000-4-2 standard for ESD immunity. ESD protection performance is demonstrated also at high temperature (140° C.). The unique high ratio of dual-polarity ESD protection level per unit area, allows for integration of fast-response and compact protection cells optimized for the current tendency of the semiconductor industry toward low cost and high density-oriented IC design. Symmetric/asymmetric dual polarity ESD protection performance is demonstrated for over 15 kV HBM, 2 kV MM, and 16.5 kV IEC for sub-micron technology.
摘要翻译：通过定制实现，先进的亚微米硅化CMOS（互补金属氧化物半导体）/ BiCMOS（双极CMOS）技术获得具有10 V至40 V以上触发电压和相对较高保持电流的对称/非对称双向S形IV特性具有嵌入镇流电阻58,58A，56,56A和外围保护环隔离88-86的P1-N2-P2-N1 // N1-P3-N3-P1侧向结构。双向保护装置为高级CMOS / BiCMOS工艺提供高水平的静电放电（ESD）抗扰性，无闩锁问题。 ESD保护单元的新型设计适配多功能354 /互指向336布局方案允许放大保护结构的ESD性能和定制集成，而IV特性480可调整到集成电路（IC）的工作条件，。 ESD保护电池使用TLP（传输线脉冲）技术和ESD标准测试，包括HBM（人体模型），MM（机器模型）和IEC（国际电工委员会）IEC 1000-4-2 ESD抗扰度标准。 ESD保护性能也在高温（140°C）下得到证明。单位面积双极性ESD保护水平的独特高比例，可实现半导体行业针对低成本和高密度导向IC设计优化的快速响应和紧凑型保护单元的集成。针对超低于15 kV HBM，2 kV MM和16.5 kV IEC的亚微米技术，可以证明对称/非对称双极性ESD保护性能。

6. 发明授权

US07985640B2 Devices with adjustable dual-polarity trigger-and holding-voltage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated 有权
标题翻译：具有可调双极触发和保持电压/电流的器件，用于亚微米混合信号CMOS / BiCMOS集成中的高电平静电放电保护
公开(公告)号：US07985640B2
公开(公告)日：2011-07-26
申请号：US12420264
申请日：2009-04-08
申请人： Javier A. Salcedo , Juin J. Liou , Joseph C. Bernier , Donald K. Whitney
发明人： Javier A. Salcedo , Juin J. Liou , Joseph C. Bernier , Donald K. Whitney
IPC分类号： H01L21/8238 , H01L21/82 , H01L21/00 , H01L21/84
CPC分类号： H01L27/0262 , H01L29/87
摘要： Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1-N2-P2-N1//N1-P3-N3-P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC). The ESD protection cells are tested using the TLP (Transmission Line Pulse) technique, and ESD standards including HBM (Human Body Model), MM (Machine Model), and IEC (International Electrotechnical Commission) IEC 1000-4-2_standard for ESD immunity. ESD protection performance is demonstrated also at high temperature (140° C.). The unique high ratio of dual-polarity ESD protection level per unit area, allows for integration of fast-response and compact protection cells optimized for the current tendency of the semiconductor industry toward low cost and high density-oriented IC design. Symmetric/asymmetric dual polarity ESD protection performance is demonstrated for over 15 kV HBM, 2 kV MM, and 16.5 kV IEC for sub-micron technology.
摘要翻译：通过定制实现，先进的亚微米硅化CMOS（互补金属氧化物半导体）/ BiCMOS（双极CMOS）技术获得具有10 V至40 V以上触发电压和相对较高保持电流的对称/非对称双向S形IV特性具有嵌入镇流电阻58,58A，56,56A和外围保护环隔离88-86的P1-N2-P2-N1 // N1-P3-N3-P1侧向结构。双向保护装置为高级CMOS / BiCMOS工艺提供高水平的静电放电（ESD）抗扰性，无闩锁问题。 ESD保护单元的新型设计适配多功能354 /互指向336布局方案允许放大保护结构的ESD性能和定制集成，而IV特性480可调整到集成电路（IC）的工作条件，。 ESD保护电池使用TLP（传输线脉冲）技术和ESD标准测试，包括HBM（人体模型），MM（机器模型）和IEC（国际电工委员会）IEC 1000-4-2标准的ESD抗扰度。 ESD保护性能也在高温（140°C）下得到证明。单位面积双极性ESD保护水平的独特高比例，可实现半导体行业针对低成本和高密度导向IC设计优化的快速响应和紧凑型保护单元的集成。针对超低于15 kV HBM，2 kV MM和16.5 kV IEC的亚微米技术，可以证明对称/非对称双极性ESD保护性能。

7. 发明授权

US07601991B2 On-chip structure for electrostatic discharge (ESD) protection 失效
标题翻译：用于静电放电（ESD）保护的片上结构
公开(公告)号：US07601991B2
公开(公告)日：2009-10-13
申请号：US11691018
申请日：2007-03-26
申请人： Javier A. Salcedo , Juin J. Liou , Joseph C. Bernier , Donald K. Whitney, Jr.
发明人： Javier A. Salcedo , Juin J. Liou , Joseph C. Bernier , Donald K. Whitney, Jr.
IPC分类号： H01L29/72
CPC分类号： H01L27/0262 , H01L29/7436
摘要： A complementary SCR-based structure enables a tunable holding voltage for robust and versatile ESD protection. The structureare n-channel high-holding-voltage low-voltage -trigger silicon controller rectifier (N-HHLVTSCR) device and p-channel high-holding-voltage low-voltage -trigger silicon controller rectifier (P-HHLVTSCR) device. The regions of the N-HHLVTSCR and P-HHLVTSCR devices are formed during normal processing steps in a CMOS or BICMOS process. The spacing and dimensions of the doped regions of N-HHLVTSCR and P-HHLVTSCR devices are used to produce the desired characteristics. The tunable HHLVTSCRs makes possible the use of this protection circuit in a broad range of ESD applications including protecting integrated circuits where the I/O signal swing can be either within the range of the bias of the internal circuit or below/above the range of the bias of the internal circuit.
摘要翻译：互补的基于SCR的结构使得可调谐的保持电压具有稳健和通用的ESD保护。结构为n沟道高压保护电压低电压触发器硅控整流器（N-HHLVTSCR）器件和p沟道高保持电压低电压触发器硅控整流器（P-HHLVTSCR）器件。 N-HHLVTSCR和P-HHLVTSCR器件的区域在CMOS或BICMOS工艺的正常处理步骤期间形成。使用N-HHLVTSCR和P-HHLVTSCR器件的掺杂区域的间距和尺寸来产生所需的特性。可调谐的HHLVTSCR可以在广泛的ESD应用中使用该保护电路，包括保护集成电路，其中I / O信号摆幅可以在内部电路的偏置范围内或低于/高于内部电路的偏置。

8. 发明授权

US07285828B2 Electrostatic discharge protection device for digital circuits and for applications with input/output bipolar voltage much higher than the core circuit power supply 失效
标题翻译：用于数字电路的静电放电保护装置和输入/输出双极性电压远高于核心电路电源的应用
公开(公告)号：US07285828B2
公开(公告)日：2007-10-23
申请号：US11330139
申请日：2006-01-12
申请人： Javier A. Salcedo , Juin J. Liou , Joseph C. Bernier , Donald K. Whitney
发明人： Javier A. Salcedo , Juin J. Liou , Joseph C. Bernier , Donald K. Whitney
IPC分类号： H01L23/62
CPC分类号： H01L29/7436 , H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) device and method is provided. The ESD device can comprise a substrate doped to a first conductivity type, an epitaxial region doped to the second conductivity type, and a first well doped to the first conductivity type disposed in the substrate. The first well can comprise a first region doped to the first conductivity type, a second region doped to a second conductivity type, and a first isolation region disposed between the first region and the second region. The ESD device can also comprise a second well doped to a second conductivity type disposed in the substrate adjacent to the first well, where the second well can comprise a third region doped to the first conductivity type, a fourth region doped to the second conductivity type, and a second isolation region disposed between the third region and the fourth region. Still further, the ESD device can include a first trigger contact and second trigger contact comprising highly doped regions of either conductivity type, the first trigger contact disposed at a junction between the first well and the second well, and the second trigger contact disposed at either well.
摘要翻译：提供了静电放电（ESD）装置和方法。 ESD器件可以包括掺杂到第一导电类型的衬底，掺杂到第二导电类型的外延区域，以及掺杂到设置在衬底中的第一导电类型的第一阱。第一阱可以包括掺杂到第一导电类型的第一区域，掺杂到第二导电类型的第二区域和设置在第一区域和第二区域之间的第一隔离区域。 ESD器件还可以包括掺杂到与第一阱相邻的衬底中的第二导电类型的第二阱，其中第二阱可以包括掺杂到第一导电类型的第三区域，掺杂到第二导电类型的第四区域以及设置在第三区域和第四区域之间的第二隔离区域。此外，ESD装置可以包括第一触发触点和第二触发触点，其包括导电类型的高掺杂区域，第一触发触点设置在第一阱和第二阱之间的接合处，第二触发触点设置在任一个好。

9. 发明申请

US20110284922A1 DEVICES WITH ADJUSTABLE DUAL-POLARITY TRIGGER-AND HOLDING-VOTAGE/CURRENT FOR HIGH LEVEL OF ELECTROSTATIC DISCHARGE PROTECTION IN SUB-MICRON MIXED SIGNAL CMOS/BICMOS INTEGRATED 失效
标题翻译：具有可调双极性触发器和保持电压/电流的低电压放电保护功能CMOS / BICMOS集成
公开(公告)号：US20110284922A1
公开(公告)日：2011-11-24
申请号：US13114895
申请日：2011-05-24
申请人： Javier A. Salcedo , Juin J. Liou , Joseph C. Bernier , Donald K. Whitsey
发明人： Javier A. Salcedo , Juin J. Liou , Joseph C. Bernier , Donald K. Whitsey
IPC分类号： H01L29/747
CPC分类号： H01L27/0262 , H01L29/87
摘要： Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1-N2-P2-N1//N1-P3-N3-P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC). The ESD protection cells are tested using the TLP (Transmission Line Pulse) technique, and ESD standards including HBM (Human Body Model), MM (Machine Model), and IEC (International Electrotechnical Commission) IEC 1000-4-2 standard for ESD immunity. ESD protection performance is demonstrated also at high temperature (140° C.). The unique high ratio of dual-polarity ESD protection level per unit area, allows for integration of fast-response and compact protection cells optimized for the current tendency of the semiconductor industry toward low cost and high density-oriented IC design. Symmetric/asymmetric dual polarity ESD protection performance is demonstrated for over 15 kV HBM, 2 kV MM, and 16.5 kV IEC for sub-micron technology.
摘要翻译：通过定制实现，先进的亚微米硅化CMOS（互补金属氧化物半导体）/ BiCMOS（双极CMOS）技术获得具有10 V至40 V以上触发电压和相对较高保持电流的对称/非对称双向S形IV特性具有嵌入镇流电阻58,58A，56,56A和外围保护环隔离88-86的P1-N2-P2-N1 // N1-P3-N3-P1侧向结构。双向保护装置为高级CMOS / BiCMOS工艺提供高水平的静电放电（ESD）抗扰性，无闩锁问题。 ESD保护单元的新型设计适配多功能354 /互指向336布局方案允许放大保护结构的ESD性能和定制集成，而IV特性480可调整到集成电路（IC）的工作条件，。 ESD保护电池使用TLP（传输线脉冲）技术和ESD标准测试，包括HBM（人体模型），MM（机器模型）和IEC（国际电工委员会）IEC 1000-4-2 ESD抗扰度标准。 ESD保护性能也在高温（140°C）下得到证明。单位面积双极性ESD保护水平的独特高比例，可实现半导体行业针对低成本和高密度导向IC设计优化的快速响应和紧凑型保护单元的集成。针对超低于15 kV HBM，2 kV MM和16.5 kV IEC的亚微米技术，可以证明对称/非对称双极性ESD保护性能。

10. 发明授权

US07842971B2 Silicon-controlled rectifier (SCR) device for high-voltage electrostatic discharge (ESD) applications 失效
标题翻译：用于高压静电放电（ESD）应用的硅控整流器（SCR）器件
公开(公告)号：US07842971B2
公开(公告)日：2010-11-30
申请号：US12366159
申请日：2009-02-05
申请人： Zhiwei Liu , Juin J. Liou , James E. Vinson
发明人： Zhiwei Liu , Juin J. Liou , James E. Vinson
IPC分类号： H01L29/74
CPC分类号： H01L29/87 , H01L27/0262 , H01L29/0692
摘要： A silicon-controlled rectifier (SCR) device having a high holding voltage includes a PNP transistor and an NPN transistor, each transistor having both p-type and n-type dopant regions in their respective emitter areas. The device is particularly suited to high voltage applications, as the high holding voltage provides a device which is more resistant to latchup subsequent to an electrostatic discharge event compared to devices having a low holding voltage.
摘要翻译：具有高保持电压的硅控整流器（SCR）器件包括PNP晶体管和NPN晶体管，每个晶体管在其各自的发射极区域中都具有p型掺杂区域和n型掺杂区域。该器件特别适用于高电压应用，因为高保持电压提供了与具有低保持电压的器件相比，在静电放电事件之后更能抵抗闩锁的器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式