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1. 发明授权

US08029975B2 Fused aromatic structures and methods for photolithographic applications 有权
标题翻译：熔融芳族结构和光刻应用的方法
公开(公告)号：US08029975B2
公开(公告)日：2011-10-04
申请号：US12508652
申请日：2009-07-24
申请人： James J. Bucchignano , Wu-Song Huang , Pushkara R. Varanasi , Roy R. Yu
发明人： James J. Bucchignano , Wu-Song Huang , Pushkara R. Varanasi , Roy R. Yu
IPC分类号： G03F7/004 , G03F7/039 , G03F7/20 , G03F7/30 , G03F7/38
CPC分类号： G03F7/0045 , G03F7/0392 , Y10S430/12 , Y10S430/122 , Y10S430/126 , Y10S430/143
摘要： A resist composition and a method for forming a patterned feature on a substrate. The composition comprises a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, and a photosensitive acid generator. The method includes providing a composition including a photosensitive acid generator and a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, forming a film of the composition on the substrate, patternwise imaging the film, wherein at least one region of the film is exposed to radiation or a beam of particles, resulting in production of an acid catalyst in the exposed region, baking the film, developing the film, resulting in removal of base-soluble exposed regions, wherein a patterned feature from the film remains following the removal.
摘要翻译：抗蚀剂组合物和在基材上形成图案化特征的方法。该组合物包含具有至少一个稠合多环部分和至少一个被酸不稳定保护基团保护的碱溶性官能团的分子玻璃和光敏酸产生剂。该方法包括提供包含光敏酸产生剂和具有至少一个稠合多环部分的分子玻璃和至少一个被酸不稳定保护基团保护的碱可溶官能团的组合物，在该基质上形成该组合物的膜，图案成像所述膜，其中所述膜的至少一个区域暴露于辐射或颗粒束，导致在所述暴露区域中产生酸催化剂，烘烤所述膜，显影所述膜，导致去除可溶于碱的暴露区域，其中来自膜的图案化特征在去除之后保持不变。

2. 发明申请

US20090004596A1 FUSED AROMATIC STRUCTURES AND METHODS FOR PHOTOLITHOGRAPHIC APPLICATIONS 失效
公开(公告)号：US20090004596A1
公开(公告)日：2009-01-01
申请号：US11769089
申请日：2007-06-27
申请人： James J. Bucchignano , Wu-Song Huang , Pushkara R. Varanasi , Roy R. Yu
发明人： James J. Bucchignano , Wu-Song Huang , Pushkara R. Varanasi , Roy R. Yu
IPC分类号： G03C1/73 , G03C5/00
CPC分类号： G03F7/0045 , G03F7/0392 , Y10S430/12 , Y10S430/122 , Y10S430/126 , Y10S430/143
摘要： A resist composition and a method for forming a patterned feature on a substrate. The composition comprises a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, and a photosensitive acid generator. The method includes providing a composition including a photosensitive acid generator and a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, forming a film of the composition on the substrate, patternwise imaging the film, wherein at least one region of the film is exposed to radiation or a beam of particles, resulting in production of an acid catalyst in the exposed region, baking the film, developing the film, resulting in removal of base-soluble exposed regions, wherein a patterned feature from the film remains following the removal.

3. 发明申请

US20090286180A1 FUSED AROMATIC STRUCTURES AND METHODS FOR PHOTOLITHOGRAPHIC APPLICATIONS 有权
标题翻译：用于光刻应用的熔融芳构结构和方法
公开(公告)号：US20090286180A1
公开(公告)日：2009-11-19
申请号：US12508652
申请日：2009-07-24
申请人： James J. Bucchignano , Wu-Song Huang , Pushkara R. Varanasi , Roy R. Yu
发明人： James J. Bucchignano , Wu-Song Huang , Pushkara R. Varanasi , Roy R. Yu
IPC分类号： G03F7/20 , G03F7/004
CPC分类号： G03F7/0045 , G03F7/0392 , Y10S430/12 , Y10S430/122 , Y10S430/126 , Y10S430/143
摘要： A resist composition and a method for forming a patterned feature on a substrate. The composition comprises a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, and a photosensitive acid generator. The method includes providing a composition including a photosensitive acid generator and a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, forming a film of the composition on the substrate, patternwise imaging the film, wherein at least one region of the film is exposed to radiation or a beam of particles, resulting in production of an acid catalyst in the exposed region, baking the film, developing the film, resulting in removal of base-soluble exposed regions, wherein a patterned feature from the film remains following the removal.
摘要翻译：抗蚀剂组合物和在基材上形成图案化特征的方法。该组合物包含具有至少一个稠合多环部分和至少一个被酸不稳定保护基团保护的碱溶性官能团的分子玻璃和光敏酸产生剂。该方法包括提供包含光敏酸产生剂和具有至少一个稠合多环部分的分子玻璃和至少一个被酸不稳定保护基团保护的碱可溶官能团的组合物，在该基质上形成该组合物的膜，图案成像所述膜，其中所述膜的至少一个区域暴露于辐射或颗粒束，导致在所述暴露区域中产生酸催化剂，烘烤所述膜，显影所述膜，导致去除可溶于碱的暴露区域，其中来自膜的图案化特征在去除之后保持不变。

4. 发明授权

US07566527B2 Fused aromatic structures and methods for photolithographic applications 失效
标题翻译：熔融芳族结构和光刻应用的方法
公开(公告)号：US07566527B2
公开(公告)日：2009-07-28
申请号：US11769089
申请日：2007-06-27
申请人： James J. Bucchignano , Wu-Song Huang , Pushkara R. Varanasi , Roy R. Yu
发明人： James J. Bucchignano , Wu-Song Huang , Pushkara R. Varanasi , Roy R. Yu
IPC分类号： G03F7/039 , G03F7/20 , G03F7/30 , G03F7/36 , G03F7/38
CPC分类号： G03F7/0045 , G03F7/0392 , Y10S430/12 , Y10S430/122 , Y10S430/126 , Y10S430/143
摘要： A resist composition and a method for forming a patterned feature on a substrate. The composition comprises a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, and a photosensitive acid generator. The method includes providing a composition including a photosensitive acid generator and a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, forming a film of the composition on the substrate, patternwise imaging the film, wherein at least one region of the film is exposed to radiation or a beam of particles, resulting in production of an acid catalyst in the exposed region, baking the film, developing the film, resulting in removal of base-soluble exposed regions, wherein a patterned feature from the film remains following the removal.
摘要翻译：抗蚀剂组合物和在基材上形成图案化特征的方法。该组合物包含具有至少一个稠合多环部分和至少一个被酸不稳定保护基团保护的碱溶性官能团的分子玻璃和光敏酸产生剂。该方法包括提供包含光敏酸产生剂和具有至少一个稠合多环部分的分子玻璃和至少一个被酸不稳定保护基团保护的碱可溶官能团的组合物，在该基质上形成该组合物的膜，图案成像所述膜，其中所述膜的至少一个区域暴露于辐射或颗粒束，导致在所述暴露区域中产生酸催化剂，烘烤所述膜，显影所述膜，导致去除可溶于碱的暴露区域，其中来自膜的图案化特征在去除之后保持不变。

5. 发明申请

US20100196806A1 STRUCTURES AND METHODS FOR LOW-K OR ULTRA LOW-K INTERLAYER DIELECTRIC PATTERN TRANSFER 审中-公开
标题翻译：低K或超低介电常数介质转移的结构与方法
公开(公告)号：US20100196806A1
公开(公告)日：2010-08-05
申请号：US12758431
申请日：2010-04-12
申请人： James J. Bucchignano , Gerald W. Gibson , Mary B. Rothwell , Roy R. Yu
发明人： James J. Bucchignano , Gerald W. Gibson , Mary B. Rothwell , Roy R. Yu
IPC分类号： G03F1/00
CPC分类号： H01L21/31144 , H01L21/76802 , H01L21/76813
摘要： The present invention relates to improved methods and structures for forming interconnect patterns in low-k or ultra low-k (i.e., having a dielectric constant ranging from about 1.5 to about 3.5) interlevel dielectric (ILD) materials. Specifically, reduced lithographic critical dimensions (CDs) (i.e., in comparison with target CDs) are initially used for forming a patterned resist layer with an increased thickness, which in turn allows use of a simple hard mask stack comprising a lower nitride mask layer and an upper oxide mask layer for subsequent pattern transfer. The hard mask stack is next patterned by a first reactive ion etching (RIE) process using an oxygen-containing chemistry to form hard mask openings with restored CDs that are substantially the same as the target CDs. The ILD materials are then patterned by a second RIE process using a nitrogen-containing chemistry to form the interconnect pattern with the target CDs.
摘要翻译：本发明涉及用于形成低k或超低k（即介电常数范围为约1.5至约3.5）层间电介质（ILD）材料的互连图案的改进方法和结构。具体地说，减小的光刻关键尺寸（CD）（即与目标CD相比）最初用于形成具有增加的厚度的图案化抗蚀剂层，其又允许使用包括下部氮化物掩模层的简单硬掩模层，用于随后的图案转印的上氧化物掩模层。接下来通过使用含氧化学物质的第一反应离子蚀刻（RIE）工艺来形成硬掩模叠层，以形成具有与目标CD基本相同的恢复的CD的硬掩模开口。然后通过使用含氮化学物质的第二RIE方法将ILD材料图案化，以形成与目标CD的互连图案。

6. 发明授权

US07695897B2 Structures and methods for low-k or ultra low-k interlayer dielectric pattern transfer 失效
标题翻译：低k或超低k层间电介质图案转移的结构和方法
公开(公告)号：US07695897B2
公开(公告)日：2010-04-13
申请号：US11429709
申请日：2006-05-08
申请人： James J. Bucchignano , Gerald W. Gibson , Mary B. Rothwell , Roy R. Yu
发明人： James J. Bucchignano , Gerald W. Gibson , Mary B. Rothwell , Roy R. Yu
IPC分类号： G03F7/00 , G03F7/26
CPC分类号： H01L21/31144 , H01L21/76802 , H01L21/76813
摘要： The present invention relates to improved methods and structures for forming interconnect patterns in low-k or ultra low-k (i.e., having a dielectric constant ranging from about 1.5 to about 3.5) interlevel dielectric (ILD) materials. Specifically, reduced lithographic critical dimensions (CDs) (i.e., in comparison with target CDs) are initially used for forming a patterned resist layer with an increased thickness, which in turn allows use of a simple hard mask stack comprising a lower nitride mask layer and an upper oxide mask layer for subsequent pattern transfer. The hard mask stack is next patterned by a first reactive ion etching (RIE) process using an oxygen-containing chemistry to form hard mask openings with restored CDs that are substantially the same as the target CDs. The ILD materials are then patterned by a second RIE process using a nitrogen-containing chemistry to form the interconnect pattern with the target CDs.
摘要翻译：本发明涉及用于形成低k或超低k（即介电常数范围为约1.5至约3.5）层间电介质（ILD）材料的互连图案的改进方法和结构。具体地说，减小的光刻关键尺寸（CD）（即与目标CD相比）最初用于形成具有增加的厚度的图案化抗蚀剂层，其又允许使用包括下部氮化物掩模层的简单硬掩模层，用于随后的图案转印的上氧化物掩模层。接下来通过使用含氧化学物质的第一反应离子蚀刻（RIE）工艺来形成硬掩模叠层，以形成具有与目标CD基本相同的恢复的CD的硬掩模开口。然后通过使用含氮化学物质的第二RIE方法将ILD材料图案化，以形成与目标CD的互连图案。

7. 发明申请

US20150024548A1 COMPUTER READABLE MEDIUM ENCODED WITH A PROGRAM FOR FABRICATING 3D INTEGRATED CIRCUIT DEVICE USING INTERFACE WAFER AS PERMANENT CARRIER 有权
标题翻译：使用接口作为永久载体制作3D集成电路设备的程序编写的计算机可读介质
公开(公告)号：US20150024548A1
公开(公告)日：2015-01-22
申请号：US13572004
申请日：2012-08-10
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
IPC分类号： H01L25/065 , H01L25/00
CPC分类号： H01L25/0657 , H01L21/6835 , H01L25/18 , H01L25/50 , H01L2221/68377 , H01L2224/0401 , H01L2224/05001 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05558 , H01L2224/05568 , H01L2224/0557 , H01L2224/056 , H01L2224/131 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73153 , H01L2224/73253 , H01L2224/83121 , H01L2224/83895 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/157 , H01L2924/37001 , H01L2224/83 , H01L2224/11 , H01L2924/014 , H01L2924/00014
摘要： A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.
摘要翻译：提供了一种计算机可读介质，其由包含用于执行制造3D集成电路结构的方法的指令的程序编码。提供了包括第一布线层和穿硅通孔的接口晶片，以及包括有源电路的第一有源电路层晶片。第一有源电路层晶片被结合到界面晶片。然后，去除第一有源电路层晶片的第一部分，使得第二部分保持附着到界面晶片。包括接口晶片和第一有源电路层晶片的第二部分的堆叠结构被结合到基底晶片。接下来，将界面晶片减薄以形成界面层，并且在界面层上形成通过界面层中的穿硅通孔耦合到第一布线层的金属化。

8. 发明授权

US08738167B2 3D integrated circuit device fabrication with precisely controllable substrate removal 有权
标题翻译： 3D集成电路器件制造具有精确可控的衬底去除
公开(公告)号：US08738167B2
公开(公告)日：2014-05-27
申请号：US13398481
申请日：2012-02-16
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Sampath Purushothaman , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Sampath Purushothaman , Roy R. Yu
IPC分类号： G06F19/00 , H01L21/30 , H01L21/46 , H01L23/48 , H01L23/52
CPC分类号： H01L27/105 , H01L24/11 , H01L27/0688 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05147 , H01L2224/05184 , H01L2224/05568 , H01L2224/0557 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/05599
摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a non-transitory computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.
摘要翻译：提供了一种用于制造3D集成电路结构的方法。根据该方法，提供第一有源电路层晶片。第一有源电路层晶片包括由P层覆盖的P +部分，并且P层包括有源电路。第一有源电路层晶片面向下接合到包括第一布线层的接口晶片，然后相对于第一有源电路层晶片的P层选择性地去除第一有源电路层晶片的P +部分。接下来，在P-层的背面上制造布线层。还提供了编码有用于制造3D集成电路结构的程序的非暂时计算机可读介质，以及3D集成电路结构。

9. 发明授权

US08629553B2 3D integrated circuit device fabrication with precisely controllable substrate removal 有权
标题翻译： 3D集成电路器件制造具有精确可控的衬底去除
公开(公告)号：US08629553B2
公开(公告)日：2014-01-14
申请号：US13398505
申请日：2012-02-16
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Sampath Purushothaman , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Sampath Purushothaman , Roy R. Yu
IPC分类号： H01L23/34 , H01L21/30
CPC分类号： H01L27/105 , H01L24/11 , H01L27/0688 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05147 , H01L2224/05184 , H01L2224/05568 , H01L2224/0557 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/05599
摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.
摘要翻译：提供了一种用于制造3D集成电路结构的方法。根据该方法，提供第一有源电路层晶片。第一有源电路层晶片包括由P层覆盖的P +部分，并且P层包括有源电路。第一有源电路层晶片面向下接合到包括第一布线层的接口晶片，然后相对于第一有源电路层晶片的P层选择性地去除第一有源电路层晶片的P +部分。接下来，在P-层的背面上制造布线层。还提供了用用于制造3D集成电路结构的程序编码的有形计算机可读介质和3D集成电路结构。

10. 发明申请

US20120308241A1 Process for Enhanced 3D Integration and Structures Generated Using the Same 审中-公开
公开(公告)号：US20120308241A1
公开(公告)日：2012-12-06
申请号：US13585942
申请日：2012-08-15
申请人： Egan G. Colgan , Sampath Purushothaman , Roy R. Yu
发明人： Egan G. Colgan , Sampath Purushothaman , Roy R. Yu
IPC分类号： H04B10/12
CPC分类号： H01L23/49816 , B23P11/00 , H01L21/78 , H01L2924/0002 , H05K1/11 , H05K1/14 , H05K7/00 , Y10T29/49826 , H01L2924/00
摘要： An enhanced 3D integration structure comprises a logic microprocessor chip bonded to a collection of vertically stacked memory slices and an optional set of outer vertical slices comprising optoelectronic devices. Such a device enables both high memory content in close proximity to the logic circuits and a high bandwidth for logic to memory communication. Additionally, the provision of optoelectronic devices in the outer slices of the vertical slice stack enables high bandwidth direct communication between logic processor chips on adjacent enhanced 3D modules mounted next to each other or on adjacent packaging substrates. A method to fabricate such structures comprises using a template assembly which enables wafer format processing of vertical slice stacks.

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