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1. 发明授权

US08878860B2 Accessing memory using multi-tiling 有权
标题翻译：使用多个平铺来访问内存
公开(公告)号：US08878860B2
公开(公告)日：2014-11-04
申请号：US11648469
申请日：2006-12-28
申请人： James Akiyama , William H. Clifford
发明人： James Akiyama , William H. Clifford
IPC分类号： G06F13/28 , G06F13/16 , G06F12/06 , G11C11/408 , G11C8/12 , G06F12/02
CPC分类号： G06F13/1684 , G06F12/0207 , G06F12/0646 , G09G5/395 , G09G2360/122 , G09G2360/123 , G11C8/12 , G11C11/4082
摘要： An embodiment of the present invention is a technique to control memory access. An address pre-swizzle circuit conditions address bits provided by a processor according to access control signals. A data steering circuit connects to N sub-channels of memory to dynamically steer data for a memory access type including tiled and untiled memory accesses according to the access control signals, the conditioned address bits, and sub-channel identifiers associated with the N sub-channels. The tiled memory access includes horizontally and vertically tiled memory accesses. An address post-swizzle circuit generates sub-channel address bits to the N sub-channels using the conditioned address bits and according to the access control signals and the sub-channel identifiers.
摘要翻译：本发明的一个实施例是一种控制存储器访问的技术。地址预先转换电路根据访问控制信号条件来处理由处理器提供的地址位。数据转向电路连接到存储器的N个子通道，以根据与N个子通道相关联的访问控制信号，经调节的地址位和子信道标识符动态地引导包括平铺和直到的存储器访问的存储器访问类型的数据，频道平铺内存访问包括水平和垂直平铺的内存访问。地址后转换电路使用经调节的地址位并根据访问控制信号和子信道标识符向N个子信道生成子信道地址位。

2. 发明授权

US08332598B2 Memory micro-tiling request reordering 有权
标题翻译：内存微贴请求重新排序
公开(公告)号：US08332598B2
公开(公告)日：2012-12-11
申请号：US11159741
申请日：2005-06-23
申请人： James Akiyama , William H. Clifford , Paul M. Brown
发明人： James Akiyama , William H. Clifford , Paul M. Brown
IPC分类号： G06F12/00
CPC分类号： G06F13/1626 , G06F13/1684 , G09G5/393 , G09G2360/122 , G09G2360/125
摘要： According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic, a reorder table and a transaction assembler. The assignment logic receives a request to access a memory channel and assigns the request to access one of two or more independently addressable subchannels within the channel. The reorder table includes two or more table elements. Each table element includes a shared address component and an independent address component corresponding to each of the two or more independently addressable subchannels. The transaction assembler combines the shared and independent address components in a reorder table element and issue a single memory transaction.
摘要翻译：根据一个实施例，公开了一种存储器控制器。存储器控制器包括分配逻辑，重排序表和事务汇编器。分配逻辑接收访问存储器通道的请求，并分配请求以访问通道内的两个或更多个可独立寻址的子信道中的一个。重排序表包括两个或多个表元素。每个表格元素包括共享地址组件和对应于两个或更多个可独立寻址的子信道中的每一个的独立地址组件。事务汇编器将重新排序表元素中的共享和独立地址组件合并并发出单个内存事务。

3. 发明申请

US20100122046A1 Memory Micro-Tiling 有权
标题翻译：内存微平铺
公开(公告)号：US20100122046A1
公开(公告)日：2010-05-13
申请号：US12690551
申请日：2010-01-20
申请人： James Akiyama , Randy B. Osborne , William H. Clifford
发明人： James Akiyama , Randy B. Osborne , William H. Clifford
IPC分类号： G06F12/02
CPC分类号： G06F13/1684 , G09G5/393 , G09G2360/122 , G09G2360/125
摘要： According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel. The transaction assembler combines the request into one or more additional requests to access two or more independently addressable subchannels within the channel.
摘要翻译：根据一个实施例，公开了一种存储器控制器。存储器控制器包括分配逻辑和事务汇编器。分配逻辑接收访问存储器通道的请求。交易汇编器将该请求组合成一个或多个附加请求以访问频道内的两个或更多个可独立寻址的子信道。

4. 发明申请

US20080162802A1 Accessing memory using multi-tiling 有权
标题翻译：使用多个平铺来访问内存
公开(公告)号：US20080162802A1
公开(公告)日：2008-07-03
申请号：US11648469
申请日：2006-12-28
申请人： James Akiyama , William H. Clifford
发明人： James Akiyama , William H. Clifford
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G06F12/0207 , G06F12/0646 , G09G5/395 , G09G2360/122 , G09G2360/123 , G11C8/12 , G11C11/4082
摘要： An embodiment of the present invention is a technique to control memory access. An address pre-swizzle circuit conditions address bits provided by a processor according to access control signals. A data steering circuit connects to N sub-channels of memory to dynamically steer data for a memory access type including tiled and untiled memory accesses according to the access control signals, the conditioned address bits, and sub-channel identifiers associated with the N sub-channels. The tiled memory access includes horizontally and vertically tiled memory accesses. An address post-swizzle circuit generates sub-channel address bits to the N sub-channels using the conditioned address bits and according to the access control signals and the sub-channel identifiers.
摘要翻译：本发明的一个实施例是一种控制存储器访问的技术。地址预先转换电路根据访问控制信号条件来处理由处理器提供的地址位。数据转向电路连接到存储器的N个子通道，以根据与N个子通道相关联的访问控制信号，经调节的地址位和子信道标识符动态地引导包括平铺和直到的存储器访问的存储器访问类型的数据，频道平铺内存访问包括水平和垂直平铺的内存访问。地址后转换电路使用经调节的地址位并根据访问控制信号和子信道标识符向N个子信道生成子信道地址位。

5. 发明授权

US07765366B2 Memory micro-tiling 失效
标题翻译：内存微贴
公开(公告)号：US07765366B2
公开(公告)日：2010-07-27
申请号：US11159745
申请日：2005-06-23
申请人： James Akiyama , Randy B. Osborne , William H. Clifford
发明人： James Akiyama , Randy B. Osborne , William H. Clifford
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/1684 , G09G5/393 , G09G2360/122 , G09G2360/125
摘要： According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel. The transaction assembler combines the request into one or more additional requests to access two or more independently addressable subchannels within the channel.
摘要翻译：根据一个实施例，公开了一种存储器控制器。存储器控制器包括分配逻辑和事务汇编器。分配逻辑接收访问存储器通道的请求。交易汇编器将该请求组合成一个或多个附加请求以访问频道内的两个或更多个可独立寻址的子信道。

6. 发明授权

US07587521B2 Mechanism for assembling memory access requests while speculatively returning data 失效
标题翻译：在推测返回数据时组装内存访问请求的机制
公开(公告)号：US07587521B2
公开(公告)日：2009-09-08
申请号：US11165390
申请日：2005-06-23
申请人： James Akiyama , William H. Clifford
发明人： James Akiyama , William H. Clifford
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F13/1684 , G06F13/1626
摘要： According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel and assigns the request to access one of two or more independently addressable subchannels within the channel. The transaction assembler combines the request with one or more additional requests to access the two or more independently addressable subchannels within the channel and facilitates a speculative return of data from a subchannel for which a subchannel request is not available.
摘要翻译：根据一个实施例，公开了一种存储器控制器。存储器控制器包括分配逻辑和事务汇编器。分配逻辑接收访问存储器通道的请求，并分配请求以访问通道内的两个或更多个可独立寻址的子信道中的一个。事务汇编器将请求与一个或多个附加请求组合以访问信道内的两个或更多个可独立寻址的子信道，并且促进从子信道请求不可用的子信道的数据的推测返回。

7. 发明授权

US08010754B2 Memory micro-tiling 有权
标题翻译：内存微贴
公开(公告)号：US08010754B2
公开(公告)日：2011-08-30
申请号：US12690551
申请日：2010-01-20
申请人： James Akiyama , Randy B. Osborne , William H. Clifford
发明人： James Akiyama , Randy B. Osborne , William H. Clifford
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G09G5/393 , G09G2360/122 , G09G2360/125
摘要： According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel. The transaction assembler combines the request into one or more additional requests to access two or more independently addressable subchannels within the channel.
摘要翻译：根据一个实施例，公开了一种存储器控制器。存储器控制器包括分配逻辑和事务汇编器。分配逻辑接收访问存储器通道的请求。交易汇编器将该请求组合成一个或多个附加请求以访问频道内的两个或更多个可独立寻址的子信道。

8. 发明申请

US20130132683A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 审中-公开
公开(公告)号：US20130132683A1
公开(公告)日：2013-05-23
申请号：US13713614
申请日：2012-12-13
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

9. 发明授权

US08099523B2 PCI express enhancements and extensions including transactions having prefetch parameters 有权
标题翻译： PCI Express增强和扩展，包括具有预取参数的事务
公开(公告)号：US08099523B2
公开(公告)日：2012-01-17
申请号：US13073219
申请日：2011-03-28
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Abraham Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Abraham Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F3/00
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
摘要翻译：这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。包括有功功率子状态及其设置以允许更有效的电源管理。并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

10. 发明申请

US20110238882A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 有权
公开(公告)号：US20110238882A1
公开(公告)日：2011-09-29
申请号：US13073149
申请日：2011-03-28
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Avi (Abraham) Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Avi (Abraham) Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F13/14
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

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