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    • 4. 发明授权
    • Substrate supports for semiconductor applications
    • 基板支持半导体应用
    • US08619406B2
    • 2013-12-31
    • US13117262
    • 2011-05-27
    • Jaeyong ChoJohn Sirman
    • Jaeyong ChoJohn Sirman
    • H01T23/00
    • H01L21/6833H01L21/6831
    • This invention relates to substrate supports, e.g., coated electrostatic chucks, having a dielectric multilayer formed thereon; dielectric multilayers that provide erosive and corrosive barrier protection in harsh environments such as plasma treating vessels used in semiconductor device manufacture; process chambers, e.g., deposition chambers, for processing substrates; methods for protecting substrate supports; and methods for producing substrate supports and electronic devices. The dielectric multilayer comprises (a) an undercoat dielectric layer comprising a metal oxide or metal nitride formed on a surface; and (b) a topcoat dielectric layer comprising a metal oxide formed on the undercoat dielectric layer. The topcoat dielectric layer has an aluminum oxide content of less than about 1 weight percent. The topcoat dielectric layer has a corrosion resistance and/or plasma erosion resistance greater than the corrosion resistance and/or plasma erosion resistance of the undercoat dielectric layer. The undercoat dielectric layer can have a resistivity greater than the resistivity of the topcoat dielectric layer. The topcoat dielectric layer can have a dielectric constant greater than the dielectric constant of the undercoat dielectric layer. The undercoat dielectric layer can have a porosity greater than the porosity of the topcoat dielectric layer. The invention is useful, for example, in the manufacture and protection of electrostatic chucks used in semiconductor device manufacture.
    • 本发明涉及其上形成有电介质多层的衬底支撑体,例如涂覆的静电吸盘; 在诸如半导体器件制造中使用的等离子体处理容器等恶劣环境中提供腐蚀性和腐蚀性屏障保护的电介质多层膜; 处理室,例如沉积室,用于处理衬底; 用于保护衬底支撑件的方法; 以及用于制造衬底支撑件和电子器件的方法。 电介质层包括(a)在表面上形成的包含金属氧化物或金属氮化物的底涂层介电层; 和(b)包含在底涂层介电层上形成的金属氧化物的面漆介电层。 面漆介电层的氧化铝含量小于约1重量%。 面漆介电层具有比底涂层电介质层的耐腐蚀性和/或耐等离子体侵蚀性更强的耐腐蚀性和/或等离子体侵蚀性。 底涂层介电层的电阻率可以大于外涂层电介质层的电阻率。 面漆介电层的介电常数可以大于底涂层介电层的介电常数。 底涂层介电层的孔隙率可以大于顶涂层介电层的孔隙率。 本发明在例如半导体器件制造中使用的静电卡盘的制造和保护中是有用的。
    • 6. 发明申请
    • SUBSTRATE SUPPORTS FOR SEMICONDUCTOR APPLICATIONS
    • 用于半导体应用的基板支持
    • US20120141661A1
    • 2012-06-07
    • US13117262
    • 2011-05-27
    • Jaeyong ChoJohn Sirman
    • Jaeyong ChoJohn Sirman
    • H02N13/00B05D5/00B05D5/12
    • H01L21/6833H01L21/6831
    • This invention relates to substrate supports, e.g., coated electrostatic chucks, having a dielectric multilayer formed thereon; dielectric multilayers that provide erosive and corrosive barrier protection in harsh environments such as plasma treating vessels used in semiconductor device manufacture; process chambers, e.g., deposition chambers, for processing substrates; methods for protecting substrate supports; and methods for producing substrate supports and electronic devices. The dielectric multilayer comprises (a) an undercoat dielectric layer comprising a metal oxide or metal nitride formed on a surface; and (b) a topcoat dielectric layer comprising a metal oxide formed on the undercoat dielectric layer. The topcoat dielectric layer has an aluminum oxide content of less than about 1 weight percent. The topcoat dielectric layer has a corrosion resistance and/or plasma erosion resistance greater than the corrosion resistance and/or plasma erosion resistance of the undercoat dielectric layer. The undercoat dielectric layer can have a resistivity greater than the resistivity of the topcoat dielectric layer. The topcoat dielectric layer can have a dielectric constant greater than the dielectric constant of the undercoat dielectric layer. The undercoat dielectric layer can have a porosity greater than the porosity of the topcoat dielectric layer. The invention is useful, for example, in the manufacture and protection of electrostatic chucks used in semiconductor device manufacture.
    • 本发明涉及其上形成有电介质多层的衬底支撑体,例如涂覆的静电吸盘; 在诸如半导体器件制造中使用的等离子体处理容器等恶劣环境中提供腐蚀性和腐蚀性屏障保护的电介质多层膜; 处理室,例如沉积室,用于处理衬底; 用于保护衬底支撑件的方法; 以及用于制造衬底支撑件和电子器件的方法。 电介质层包括(a)在表面上形成的包含金属氧化物或金属氮化物的底涂层介电层; 和(b)包含在底涂层介电层上形成的金属氧化物的面漆介电层。 面漆介电层的氧化铝含量小于约1重量%。 面漆介电层具有比底涂层电介质层的耐腐蚀性和/或耐等离子体侵蚀性更强的耐腐蚀性和/或等离子体侵蚀性。 底涂层介电层的电阻率可以大于外涂层电介质层的电阻率。 面漆介电层的介电常数可以大于底涂层介电层的介电常数。 底涂层介电层的孔隙率可以大于顶涂层介电层的孔隙率。 本发明在例如半导体器件制造中使用的静电卡盘的制造和保护中是有用的。