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1. 发明申请

US20110312174A1 Methods Of Manufacturing Three-Dimensional Semiconductor Devices 有权
标题翻译：制造三维半导体器件的方法
公开(公告)号：US20110312174A1
公开(公告)日：2011-12-22
申请号：US13165256
申请日：2011-06-21
申请人： Jaegoo Lee , Byungkwan You , Youngwoo Park , Kwang Soo Seol
发明人： Jaegoo Lee , Byungkwan You , Youngwoo Park , Kwang Soo Seol
IPC分类号： H01L21/3205 , H01L21/31
CPC分类号： H01L21/3205 , H01L27/11578 , H01L27/11582
摘要： Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer.
摘要翻译：制造三维半导体器件的方法，其可以包括在形成在第一堆叠结构中的第一开口内的侧壁上形成第一间隔物，在间隔物上形成牺牲填充图案以填充第一开口，形成第二堆叠结构，在所述第一堆叠结构上暴露所述牺牲填充图案的第二开口，在所述第二开口内的侧壁上形成第二间隔件，去除所述牺牲填充图案并移除所述第一间隔件和所述第二间隔件。

2. 发明授权

US08741761B2 Methods of manufacturing three-dimensional semiconductor devices 有权
标题翻译：制造三维半导体器件的方法
公开(公告)号：US08741761B2
公开(公告)日：2014-06-03
申请号：US13165256
申请日：2011-06-21
申请人： Jaegoo Lee , Byungkwan You , Youngwoo Park , Kwang Soo Seol
发明人： Jaegoo Lee , Byungkwan You , Youngwoo Park , Kwang Soo Seol
IPC分类号： H01L23/3205 , H01L21/31
CPC分类号： H01L21/3205 , H01L27/11578 , H01L27/11582
摘要： Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer.
摘要翻译：制造三维半导体器件的方法，其可以包括在形成在第一堆叠结构中的第一开口内的侧壁上形成第一间隔物，在间隔物上形成牺牲填充图案以填充第一开口，形成第二堆叠结构，在所述第一堆叠结构上暴露所述牺牲填充图案的第二开口，在所述第二开口内的侧壁上形成第二间隔件，去除所述牺牲填充图案并移除所述第一间隔件和所述第二间隔件。

3. 发明授权

US09183893B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09183893B2
公开(公告)日：2015-11-10
申请号：US14037547
申请日：2013-09-26
申请人： Kohji Kanamori , Youngwoo Park , Jintaek Park , Kwang Soo Seol , Jaeduk Lee
发明人： Kohji Kanamori , Youngwoo Park , Jintaek Park , Kwang Soo Seol , Jaeduk Lee
IPC分类号： G11C5/06 , G11C13/00 , H01L45/00 , H01L27/22 , H01L27/24
CPC分类号： G11C5/06 , G11C5/063 , G11C13/0002 , G11C13/0023 , G11C2213/73 , H01L27/222 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147
摘要： According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines.
摘要翻译：根据本发明构思的示例性实施例，半导体存储器件包括：多个存储器块，每个存储块包括多个堆叠结构，共同连接到多个存储器块的全局位线，被配置为控制全局位线和多个存储器块中的一个以及垂直选择线，其被配置为控制连接在全局位线和多个堆叠结构中的一个之间的电连接。多个堆叠结构中的每一个包括多个局部位线，第一垂直字线和第二垂直字线，其横向于多个堆叠结构的第一侧壁和第二侧壁相交，多个堆叠结构之间的第一可变电阻元件和第一垂直字线和第二可变电阻元件在多个堆叠结构和第二垂直字线之间。

4. 发明授权

US08530959B2 Three-dimensional semiconductor memory device 有权
标题翻译：三维半导体存储器件
公开(公告)号：US08530959B2
公开(公告)日：2013-09-10
申请号：US13198234
申请日：2011-08-04
申请人： Sung-Il Chang , Youngwoo Park , Kwang Soo Seol
发明人： Sung-Il Chang , Youngwoo Park , Kwang Soo Seol
IPC分类号： H01L29/78
CPC分类号： H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate.
摘要翻译：提供三维半导体器件。一种器件包括：电极结构，包括依次层叠在衬底上的导电图案，穿透电极结构的半导体图案，以及包括与导电图案相邻的沟道区域和沟道区域之间的垂直相邻区域;以及从外侧壁延伸的半导体连接层的半导体图案以将半导体图案连接到基板。

5. 发明授权

US09099347B2 Three-dimensional semiconductor memory devices and method of fabricating the same 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US09099347B2
公开(公告)日：2015-08-04
申请号：US13415388
申请日：2012-03-08
申请人： Jang-Gn Yun , Kwang Soo Seol , Youngwoo Park
发明人： Jang-Gn Yun , Kwang Soo Seol , Youngwoo Park
IPC分类号： H01L29/76 , H01L27/115
CPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, and vertical active patterns penetrating the electrode structure. At least an uppermost electrode of the electrodes is divided into a plurality of physically isolated segments arranged in the first direction. The segments of the uppermost electrode are electrically connected to each other.
摘要翻译：提供三维半导体存储器件及其制造方法。该器件可以包括在第一方向上延伸的电极结构，并且包括电极和交替重复堆叠在基板上的绝缘图案，以及穿透电极结构的垂直有源图案。至少电极的最上面的电极被分成沿着第一方向布置的多个物理隔离的部分。最上面的电极的电极彼此电连接。

6. 发明申请

US20120280299A1 Three-Dimensional Semiconductor Memory Devices and Method of Fabricating the Same 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20120280299A1
公开(公告)日：2012-11-08
申请号：US13415388
申请日：2012-03-08
申请人： Jang-Gn Yun , Kwang Soo Seol , Youngwoo Park
发明人： Jang-Gn Yun , Kwang Soo Seol , Youngwoo Park
IPC分类号： H01L29/68
CPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, and vertical active patterns penetrating the electrode structure. At least an uppermost electrode of the electrodes is divided into a plurality of physically isolated segments arranged in the first direction. The segments of the uppermost electrode are electrically connected to each other.
摘要翻译：提供三维半导体存储器件及其制造方法。该器件可以包括在第一方向上延伸的电极结构，并且包括电极和交替重复堆叠在基板上的绝缘图案，以及穿透电极结构的垂直有源图案。至少电极的最上面的电极被分成沿着第一方向布置的多个物理隔离的部分。最上面的电极的电极彼此电连接。

7. 发明申请

US20120043673A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：三维半导体存储器件
公开(公告)号：US20120043673A1
公开(公告)日：2012-02-23
申请号：US13198234
申请日：2011-08-04
申请人： SUNG-IL CHANG , Youngwoo Park , Kwang Soo Seol
发明人： SUNG-IL CHANG , Youngwoo Park , Kwang Soo Seol
IPC分类号： H01L23/52
CPC分类号： H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate.
摘要翻译：提供三维半导体器件。一种器件包括：电极结构，包括依次层叠在衬底上的导电图案，穿透电极结构的半导体图案，以及包括与导电图案相邻的沟道区域和沟道区域之间的垂直相邻区域;以及从外侧壁延伸的半导体连接层的半导体图案以将半导体图案连接到基板。

8. 发明申请

US20120119283A1 METHODS FOR FORMING ETCH STOP LAYERS, SEMICONDUCTOR DEVICES HAVING THE SAME, AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICES 有权
标题翻译：形成止蚀层的方法，具有该阻挡层的半导体器件以及用于制造半导体器件的方法
公开(公告)号：US20120119283A1
公开(公告)日：2012-05-17
申请号：US13238319
申请日：2011-09-21
申请人： Jaegoo Lee , Youngwoo Park
发明人： Jaegoo Lee , Youngwoo Park
IPC分类号： H01L29/78 , H01L29/792 , H01L29/788
CPC分类号： H01L21/76832 , H01L27/11519 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11575 , H01L27/11578 , H01L27/11582
摘要： A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion.
摘要翻译：多个垂直通道的半导体材料形成为沿着垂直方向延伸穿过多个绝缘层和多个导电图案，导电图案和垂直沟道之间的栅极绝缘层将导电图案与垂直沟道绝缘。至少两个导电图案的导电接触区域处于阶梯状结构。蚀刻停止层位于导电接触区域上，其中蚀刻停止层在多个导电图案中的第一个上具有第一部分，并且在多个导电图案中的第二个导电图案上具有第二部分，其中第一部分部分的厚度大于第二部分的厚度。

9. 发明授权

US08822322B2 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08822322B2
公开(公告)日：2014-09-02
申请号：US13214462
申请日：2011-08-22
申请人： Jaegoo Lee , Youngwoo Park , Jungdal Choi
发明人： Jaegoo Lee , Youngwoo Park , Jungdal Choi
IPC分类号： H01L21/8239
CPC分类号： H01L27/11578 , H01L27/11582 , H01L29/4234 , H01L29/7827 , H01L29/7926
摘要： A method of fabricating a semiconductor memory device includes forming a mold stack on a substrate and the mold stack including first sacrificial layers and second sacrificial layers alternately stacked on the substrate. The method also includes forming a plurality of vertical channels that penetrate the mold stack and that contact the substrate, patterning the mold stack to form word line cuts between the vertical channels, the word line cuts exposing the substrate, removing one of the first and second sacrificial layers to form recessed regions in the mold stack, forming a data storage layer, at least a portion of the data storage layer being formed between the vertical channels and the gates, forming gates in the recessed regions, forming air gaps between the gates by removing the other of the first and second sacrificial layers, and forming an insulation layer pattern in the word line cuts.
摘要翻译：一种制造半导体存储器件的方法包括在衬底上形成模具堆叠，并且模具叠层包括交替层叠在衬底上的第一牺牲层和第二牺牲层。该方法还包括形成多个垂直通道，其穿过模具叠层并与衬底接触，图案化模具叠层以形成垂直通道之间的字线切口，字线切割暴露衬底，去除第一和第二牺牲层，以在模具堆叠中形成凹陷区域，形成数据存储层，数据存储层的至少一部分形成在垂直沟道和栅极之间，在凹陷区域中形成栅极，在栅极之间形成气隙，通过去除第一和第二牺牲层中的另一个，并且在字线切割中形成绝缘层图案。

10. 发明授权

US09362226B2 Three-dimensional (3D) semiconductor devices and methods of fabricating 3D semiconductor devices 有权
标题翻译：三维（3D）半导体器件和制造3D半导体器件的方法
公开(公告)号：US09362226B2
公开(公告)日：2016-06-07
申请号：US14637755
申请日：2015-03-04
申请人： Jaegoo Lee , Youngwoo Park
发明人： Jaegoo Lee , Youngwoo Park
IPC分类号： H01L29/06 , H01L29/40 , H01L23/02 , H01L23/528 , H01L23/522 , H01L27/115
CPC分类号： H01L27/11582 , H01L23/5226 , H01L23/528 , H01L27/11548 , H01L27/11556 , H01L27/11575 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional (3D) semiconductor device includes a stack of conductive layers spaced from each other in a vertical direction, the stack having a staircase-shaped section in a connection region, and ends of the conductive layers constituting treads of the staircase-shaped section, respectively. The 3D semiconductor device further includes buffer patterns disposed on and protruding above the respective ends of the conductive layers, an interconnection structure disposed above the stack and including conductive lines, and contact plugs extending vertically between the conductive lines and the buffer patterns and electrically connected to the conductive layers of the stack via the buffer patterns.
摘要翻译：三维（3D）半导体器件包括在垂直方向上彼此间隔开的导电层的堆叠，所述堆叠在连接区域中具有阶梯状部分，并且导电层的端部构成阶梯状的胎面部分。所述3D半导体器件还包括设置在所述导电层的各个端部之上并突出于所述导电层的各个端部上方的缓冲图案，布置在所述堆叠之上并且包括导电线的互连结构以及在所述导电线与所述缓冲图案之间垂直延伸的电连接经由缓冲器图案的堆叠的导电层。

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