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1. 发明授权

US10489294B2 Hot cache line fairness arbitration in distributed modular SMP system 有权
公开(公告)号：US10489294B2
公开(公告)日：2019-11-26
申请号：US15479624
申请日：2017-04-05
申请人： International Business Machines Corporation
发明人： Michael A. Blake , Rebecca M. Gott , Pak-Kin Mak , Vesselina K. Papazova
IPC分类号： G06F12/084 , G06F12/0811 , G06F12/0831 , G06F9/52 , G06F12/0855
CPC分类号： G06F12/0857 , G06F9/52 , G06F12/084 , G06F12/0811 , G06F12/0831 , G06F2212/1024
摘要： Embodiments of the present invention are directed to hot cache line arbitration. An example of a computer-implemented method for hot cache line arbitration includes receiving a request for exclusive access to a cache line from a requestor of a drawer in a processing system. The method further includes bringing the cache line to a local cache of the drawer. The method further includes invalidating copies of the cache line in the processing system. The method further includes loading a remote fetch address register (RFAR) controller on other drawers in the processing system, wherein the RFAR comprises a local pending flag and a remote pending flag.

2. 发明申请

US20160139831A1 DYNAMIC RELOCATION OF STORAGE 有权
标题翻译：动态动态转存
公开(公告)号：US20160139831A1
公开(公告)日：2016-05-19
申请号：US14547663
申请日：2014-11-19
申请人： International Business Machines Corporation
发明人： Timothy C. Bronson , Garrett M. Drapala , Mark S. Farrell , Hieu T. Huynh , William J. Lewis , Pak-Kin Mak , Craig R. Walters
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F3/0617 , G06F3/065 , G06F3/0664 , G06F3/0683 , G06F12/0802 , G06F12/0811 , G06F12/0837 , G06F12/0842 , G06F2212/1041 , G06F2212/283 , G06F2212/608
摘要： A computing device is provided and includes a first physical memory device, a second physical memory device and a hypervisor configured to assign resources of the first and second physical memory devices to a logical partition. The hypervisor configures a dynamic memory relocation (DMR) mechanism to move entire storage increments currently processed by the logical partition between the first and second physical memory devices in a manner that is substantially transparent to the logical partition.
摘要翻译：提供了一种计算设备，并且包括第一物理存储器设备，第二物理存储器设备和管理程序，其被配置为将第一和第二物理存储器设备的资源分配给逻辑分区。管理程序配置动态存储器重定位（DMR）机制以使逻辑分区当前处理的整个存储增量以对逻辑分区基本透明的方式移动在第一和第二物理存储器设备之间。

3. 发明申请

US20140258621A1 NON-DATA INCLUSIVE COHERENT (NIC) DIRECTORY FOR CACHE 有权
标题翻译：非数据包含CACHE的内容（NIC）目录
公开(公告)号：US20140258621A1
公开(公告)日：2014-09-11
申请号：US13784958
申请日：2013-03-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Timothy C. Bronson , Garrett M. Drapala , Rebecca M. Gott , Pak-Kin Mak , Vijayalakshmi Srinivasan , Craig R. Walters
IPC分类号： G06F12/08
CPC分类号： G06F12/0833 , G06F12/0811 , G06F12/0831 , G06F2212/283 , G06F2212/621
摘要： Embodiments relate to a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer. An aspect includes determining a first eviction entry of a highest-level cache in a multilevel caching structure of the first processor node of the SMP. Another aspect includes determining that the NIC directory is not full. Another aspect includes determining that the first eviction entry of the highest-level cache is owned by a lower-level cache in the multilevel caching structure. Another aspect includes, based on the NIC directory not being full and based on the first eviction entry of the highest-level cache being owned by the lower-level cache, installing an address of the first eviction entry of the highest-level cache in a first new entry in the NIC directory. Another aspect includes invalidating the first eviction entry in the highest-level cache.
摘要翻译：实施例涉及用于计算机的对称多处理器（SMP）的非数据包含的一致（NIC）目录。一个方面包括确定SMP的第一处理器节点的多级高速缓存结构中的最高级缓存的第一逐出条目。另一方面包括确定NIC目录未满。另一方面包括确定最高级别高速缓存的第一驱逐条目是由多级缓存结构中的较低级别高速缓存所拥有的。另一方面包括，基于NIC目录不是完整的，并且基于由较低级别高速缓存所拥有的最高级缓存的第一次驱逐条目，将最高级别高速缓存的第一次驱逐条目的地址安装在 NIC目录中的第一个新条目。另一方面包括使最高级缓存中的第一个逐出条目无效。

4. 发明申请

US20180374522A1 PREINSTALL OF PARTIAL STORE CACHE LINES 审中-公开
公开(公告)号：US20180374522A1
公开(公告)日：2018-12-27
申请号：US15629923
申请日：2017-06-22
申请人： International Business Machines Corporation
发明人： Ekaterina M. Ambroladze , Sascha Junghans , Matthias Klein , Pak-Kin Mak , Robert J. Sonnelitter, III , Chad G. Wilson
IPC分类号： G11C8/06 , G06F3/06 , G06F13/16
摘要： A system and method to transfer an ordered partial store of data from a controller to a memory subsystem receives the ordered partial store of data into a buffer of the controller. The method also includes issuing a preinstall command to the memory subsystem, wherein the preinstall command indicates that data from a number of addresses of memory corresponding with a target memory location be obtained in local memory of the memory subsystem along with ownership of the data for subsequent use. A query command is issued to the memory subsystem. The query command requests an indication from the memory subsystem that the memory subsystem is ready to receive and correctly serialize the ordered partial store of data. The ordered partial store of data is transferred from the controller to the memory subsystem.

5. 发明授权

US10529396B2 Preinstall of partial store cache lines 有权
公开(公告)号：US10529396B2
公开(公告)日：2020-01-07
申请号：US15629923
申请日：2017-06-22
申请人： International Business Machines Corporation
发明人： Ekaterina M. Ambroladze , Sascha Junghans , Matthias Klein , Pak-Kin Mak , Robert J. Sonnelitter, III , Chad G. Wilson
IPC分类号： G06F3/06 , G06F13/16 , G11C7/10 , G11C8/06
摘要： A system and method to transfer an ordered partial store of data from a controller to a memory subsystem receives the ordered partial store of data into a buffer of the controller. The method also includes issuing a preinstall command to the memory subsystem, wherein the preinstall command indicates that data from a number of addresses of memory corresponding with a target memory location be obtained in local memory of the memory subsystem along with ownership of the data for subsequent use. A query command is issued to the memory subsystem. The query command requests an indication from the memory subsystem that the memory subsystem is ready to receive and correctly serialize the ordered partial store of data. The ordered partial store of data is transferred from the controller to the memory subsystem.

6. 发明申请

US20180285277A1 HOT CACHE LINE ARBITRATION 审中-公开
公开(公告)号：US20180285277A1
公开(公告)日：2018-10-04
申请号：US15472610
申请日：2017-03-29
申请人： International Business Machines Corporation
发明人： Michael A. Blake , Timothy C. Bronson , Jason D. Kohl , Pak-Kin Mak , Vesselina K. Papazova
IPC分类号： G06F12/0877
CPC分类号： G06F12/0877 , G06F12/084 , G06F13/18 , G06F2212/1016 , G06F2212/502
摘要： Embodiments of the present invention are directed to hot cache line arbitration. An example of a computer-implemented method for hot cache line arbitration includes detecting, by a processing device, a hot cache line scenario. The computer-implemented method further includes tracking, by the processing device, hot cache line requests from requesters to determine subsequent satisfaction of the requests. The computer-implemented method further includes facilitating, by the processing device, servicing of the requests according to hierarchy of the requestors.

7. 发明授权

US09003127B2 Storing data in a system memory for a subsequent cache flush 有权
标题翻译：将数据存储在系统内存中以进行后续高速缓存清理
公开(公告)号：US09003127B2
公开(公告)日：2015-04-07
申请号：US14086308
申请日：2013-11-21
申请人： International Business Machines Corporation
发明人： Michael A. Blake , Timothy C. Bronson , Hieu T. Huynh , Kenneth D. Klapproth , Pak-Kin Mak , Vesselina K. Papazova
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0895 , G06F12/0804 , G06F12/0817 , G06F12/0891 , G06F12/128
摘要： Embodiments relate to storing data to a system memory. An aspect includes accessing successive entries of a cache directory having a plurality of directory entries by a stepper engine, where access to the cache directory is given a lower priority than other cache operations. It is determined that a specific directory entry in the cache directory has a change line state that indicates it is modified. A store operation is performed to send a copy of the specific corresponding cache entry to the system memory as part of a cache management function. The specific directory entry is updated to indicate that the change line state is unmodified.
摘要翻译：实施例涉及将数据存储到系统存储器。一个方面包括通过步进引擎访问具有多个目录条目的高速缓存目录的连续条目，其中对高速缓存目录的访问被给予比其他高速缓存操作更低的优先级。确定高速缓存目录中的特定目录条目具有指示其被修改的改变行状态。执行存储操作以将特定对应的高速缓存条目的副本作为高速缓存管理功能的一部分发送到系统存储器。特定目录条目被更新以指示改变线状态是未修改的。

8. 发明授权

US08972664B2 Multilevel cache hierarchy for finding a cache line on a remote node 有权
标题翻译：用于在远程节点上查找缓存行的多级缓存层次结构
公开(公告)号：US08972664B2
公开(公告)日：2015-03-03
申请号：US13793708
申请日：2013-03-11
申请人： International Business Machines Corporation
发明人： Timothy C. Bronson , Garrett M. Drapala , Michael A. Blake , Craig R. Walters , Pak-Kin Mak
IPC分类号： G06F12/06 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0884 , G06F12/123
摘要： Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request is initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes.
摘要翻译：实施例涉及在具有系统存储器的多级缓存系统上访问高速缓存行。基于本地节点对特定高速缓存线的独占所有权的请求，请求被本地节点同时发送到用于特定高速缓存行的多个节点的系统内存和远程节点。在特定的远程节点中找到特定的高速缓存行。特定的远程节点是远程节点之一。从特定的远程节点中删除特定的高速缓存行以供另一个节点独占所有。基于具有指定缓存行在幽灵状态的指定节点，任何后续的提取请求将针对具体的缓存行启动，特定的缓存行遇到幽灵状态。当遇到鬼状态时，后续的提取请求仅被引导到多个节点的节点。

9. 发明申请

US20130339609A1 MULTILEVEL CACHE HIERARCHY FOR FINDING A CACHE LINE ON A REMOTE NODE 有权
标题翻译：用于在远程节点上查找缓存行的多个缓存高速缓存
公开(公告)号：US20130339609A1
公开(公告)日：2013-12-19
申请号：US13793708
申请日：2013-03-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Timothy C. Bronson , Garrett M. Drapala , Michael A. Blake , Craig R. Walters , Pak-Kin Mak
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0884 , G06F12/123
摘要： Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request is initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes.
摘要翻译：实施例涉及在具有系统存储器的多级缓存系统上访问高速缓存行。基于本地节点对特定高速缓存线的独占所有权的请求，请求被本地节点同时发送到用于特定高速缓存行的多个节点的系统内存和远程节点。在特定的远程节点中找到特定的高速缓存行。特定的远程节点是远程节点之一。从特定的远程节点中删除特定的高速缓存行以供另一个节点独占所有。基于具有指定缓存行在幽灵状态的指定节点，任何后续的提取请求将针对具体的缓存行启动，特定的缓存行遇到幽灵状态。当遇到鬼状态时，后续的提取请求仅被引导到多个节点的节点。

10. 发明授权

US10572385B2 Granting exclusive cache access using locality cache coherency state 有权
公开(公告)号：US10572385B2
公开(公告)日：2020-02-25
申请号：US15836154
申请日：2017-12-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Timothy C. Bronson , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Hanno Ulrich
IPC分类号： G06F12/0815 , G06F12/14 , G06F12/0813 , G06F12/0831
摘要： A cache coherency management facility to reduce latency in granting exclusive access to a cache in certain situations. A node requests exclusive access to a cache line of the cache. The node is in one region of nodes of a plurality of regions of nodes. The one region of nodes includes the node requesting exclusive access and another node of the computing environment, in which the node and the another node are local to one another as defined by a predetermined criteria. The node requesting exclusive access checks a locality cache coherency state of the another node, the locality cache coherency state being specific to the another node and indicating whether the another node has access to the cache line. Based on the checking indicating that the another node has access to the cache line, a determination is made that the node requesting exclusive access is to be granted exclusive access to the cache line. The determining being independent of transmission of information relating to the cache line from one or more other nodes of the one or more other regions of nodes.

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