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    • 3. 发明申请
    • METHOD TO PROTECT SENSITIVE DEVICES FROM ELECTROSTATIC DISCHARGE DAMAGE
    • 从静电放电损伤中保护敏感器件的方法
    • US20160261109A1
    • 2016-09-08
    • US14635005
    • 2015-03-02
    • International Business Machines Corporation
    • Ephrem G. GebreselasieIcko E. T. IbenAlain Loiseau
    • H02H9/04
    • H02H9/041
    • ESD protection circuitry that includes one, or more, of the following features, characteristics and/or advantages: (i) use of different “diode types” (for example, Schottky type, PN type, p-type diode-connected field-effect transistor (FET) type, NFET type)) in a series-connected diode set (connected in series with respect to a device-under-protection) and a parallel-connected diode set (connected in parallel with respect to a device-under-protection and the series-connected diode set); (ii) a FET is connected in series with a target device such that the FET's gate can be turned on during normal operation and the FET's gate is resistively coupled to the FET's source; and/or (iii) two FETs are connected in series with a target device such both FETs gates can be turned on during normal operation, one FET's gate is resistively coupled to its source, and the other FET's gate is electrically coupled to its drain.
    • ESD保护电路包括以下特征中的一个或多个特性和/或优点:(i)使用不同的“二极管类型”(例如,肖特基型,PN型,p型二极管连接的场效应 晶体管(FET)型,NFET型))串联连接的二极管组(相对于器件不足保护而串联连接)和并联连接的二极管组(相对于器件不足的并联连接) 保护和串联二极管组); (ii)FET与目标器件串联连接,使得在正常工作期间FET的栅极可以导通,并且FET的栅极电阻耦合到FET的源极; 和/或(iii)两个FET与目标器件串联连接,这两个FET门在正常工作期间可以导通,一个FET的栅极电阻耦合到其源极,而另一个FET的栅极电耦合到其漏极。