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1. 发明申请

US20170163270A1 MULTI-STANDARD PERFORMANCE RECONFIGURABLE I/Q ORTHOGONAL CARRIER GENERATOR 有权
公开(公告)号：US20170163270A1
公开(公告)日：2017-06-08
申请号：US15321292
申请日：2014-06-24
申请人： Institute of Semiconductors, Chinese Academy of Sciences
发明人： Xiaodong Liu , Nanjian Wu , Haiyong Wang , Wenfeng Lou , Jingjing Chen , Zhao Zhang
IPC分类号： H03L7/099 , H03L7/093 , H02M3/07 , H04B1/40
CPC分类号： H03L7/099 , H02M3/07 , H03L7/0898 , H03L7/093 , H03L7/193 , H03L2207/06 , H04B1/40
摘要： The present disclosure discloses a multi-standard performance reconfigurable I/Q orthogonal carrier generator. The generator may implement a continuously covered I/Q carrier output of 0.1-5 GHz and continuously covered differential signal outputs of 5-10 GHz and 1.5-3 GHz by means of reasonable frequency assignment; also, carrier signals under various frequencies with different loop bandwidths, different phase noises, different power consumption levels and different locking times can be generated by configuring a programmable charge pump (102), a loop filter (103) parameter, a multi-path voltage-controlled oscillator (104) and a first multiplexer (105) corresponding thereto, a five-stage-division-by-two frequency division link (109) and a corresponding second multiplexer (110) and third multiplexer (112), so as to implement generation of a multi-standard performance reconfigurable I/Q orthogonal carrier.

2. 发明授权

US09991895B2 Wireless radio-frequency transmission apparatus 有权
公开(公告)号：US09991895B2
公开(公告)日：2018-06-05
申请号：US15321991
申请日：2014-06-26
申请人： INSTITUTE OF SEMICONDUCTORS, CHINESE ACADEMY OF SCIENCES
发明人： Jingjing Chen , Nanjian Wu , Haiyong Wang , Weiyang Liu , Peng Feng
IPC分类号： H03L7/089 , H04B1/04 , H04B1/403 , H04L27/12 , H04L27/152 , H03L7/099 , H04L7/033
CPC分类号： H03L7/0891 , H03L7/099 , H03L7/193 , H04B1/04 , H04B1/403 , H04L7/033 , H04L27/12 , H04L27/152
摘要： A wireless radio-frequency transmission apparatus includes a phase frequency detector, a charge pump, a loop filter and a twin voltage-controlled oscillator. The twin voltage-controlled oscillator includes a first oscillator and a second oscillator. When the twin voltage-controlled oscillator is in a reception mode, the first and the second oscillators are coupled to each other to form a quadrature voltage-controlled oscillator, and the quadrature voltage-controlled oscillator, the phase frequency detector, the charge pump and the loop filter constitute a phase-locked loop to generate quadrature carriers. When the twin voltage-controlled oscillator is in a transmission mode, the first oscillator, the phase frequency detector, the charge pump and the loop filter constitute a phase-locked loop, and the second oscillator performs frequency modulation on transmitted data. The present disclosure can maintain a carrier frequency to be stable during high data rate transmission, and have a relatively short locking time of frequency hopping.

3. 发明授权

US09930284B2 Analog readout preprocessing circuit for CMOS image sensor and control method thereof 有权
公开(公告)号：US09930284B2
公开(公告)日：2018-03-27
申请号：US15538514
申请日：2014-12-29
申请人： INSTITUTE OF SEMICONDUCTORS, CHINESE ACADEMY OF SCIENCES
发明人： Liyuan Liu , Nanjian Wu , Zhiqiang Guo
IPC分类号： H03M1/06 , H04N5/378 , H03M1/10 , H03M1/80 , H03M1/02 , H03M1/46
CPC分类号： H04N5/378 , H03M1/02 , H03M1/1047 , H03M1/468 , H03M1/804
摘要： The present disclosure provides an analog readout preprocessing circuit for a CMOS image sensor and a control method thereof. The analog readout preprocessing circuit comprises an extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion capacitor network 1 configured to achieve readout and analog-to-digital conversion of signals output from the CMOS image sensor; an operational amplifier configured to utilize “virtual short” of two input terminals of the operational amplifier and the charge conservation principle, to achieve a function of extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion, where the extended count-type integration can effectively reduce a thermal noise and a flicker noise within the image sensor; a comparator configured to compare voltages at two terminals to achieve a function of quantization of signals; and a control signal generator configured to provide control signals.

4. 发明授权

US09449257B2 Dynamically reconstructable multistage parallel single instruction multiple data array processing system 有权
标题翻译：动态可重构多级并行单指令多数据阵列处理系统
公开(公告)号：US09449257B2
公开(公告)日：2016-09-20
申请号：US14649859
申请日：2012-12-04
申请人： INSTITUTE OF SEMICONDUCTORS, CHINESE ACADEMY OF SCIENCES
发明人： Cong Shi , Nanjian Wu , Xitian Long , Jie Yang , Qi Qin
IPC分类号： G06K9/62 , G06F15/80 , G06T1/20 , G06N3/04 , G06N3/063
CPC分类号： G06K9/6251 , G06F15/8023 , G06K9/00986 , G06N3/0454 , G06N3/063 , G06T1/20
摘要： The present invention proposes a dynamically reconfigurable multi-level parallel single instruction multiple data array processing system which has a pixel level parallel image processing element array and a row-parallel array processor. The PE array mainly implements a linear operation which is adapted to be executed in parallel in the low and middle levels of image processing and the RP array implements an operation which is adapted to execute in row-parallel in the low and middle levels of image processing or more complex nonlinear operations. In particularly, such a system can be dynamically reconfigured as an SOM neural network at a low cost of area, and the neural network supports high level of image processing such as a high speed online neural network training and image feature recognition, and completely overcomes a defect that a high level of image processing can't be done by pixel-level parallel processing array in the existing programmable vision chips and parallel vision processors, and facilitates an intelligent and portable real time on-chip vision image system with a complete function at low device cost and low power consumption.
摘要翻译：本发明提出一种具有像素级并行图像处理元件阵列和行并行阵列处理器的动态可重构多级并行单指令多数据阵列处理系统。 PE阵列主要实现一种线性操作，适用于在低级和中级图像处理中并行执行，并且RP阵列实现了适用于在低级和中级级别的图像处理中并行执行的操作或更复杂的非线性运算。特别地，这样的系统可以以低成本的区域动态地重新配置为SOM神经网络，并且神经网络支持诸如高速在线神经网络训练和图像特征识别的高级图像处理，并且完全克服了缺点是现有可编程视觉芯片和并行视觉处理器中的像素级并行处理阵列无法进行高水平的图像处理，便于具有完整功能的智能便携式实时片上视觉图像系统设备成本低，功耗低。

5. 发明授权

US09941892B2 Multi-standard performance reconfigurable I/Q orthogonal carrier generator 有权
公开(公告)号：US09941892B2
公开(公告)日：2018-04-10
申请号：US15321292
申请日：2014-06-24
申请人： Institute of Semiconductors, Chinese Academy of Sciences
发明人： Xiaodong Liu , Nanjian Wu , Haiyong Wang , Wenfeng Lou , Jingjing Chen , Zhao Zhang
IPC分类号： H03L7/093 , H03L7/099 , H04B1/40 , H02M3/07 , H03L7/089 , H03L7/193
CPC分类号： H03L7/099 , H02M3/07 , H03L7/0898 , H03L7/093 , H03L7/193 , H03L2207/06 , H04B1/40
摘要： The present disclosure discloses a multi-standard performance reconfigurable I/Q orthogonal carrier generator. The generator may implement a continuously covered I/Q carrier output of 0.1-5 GHz and continuously covered differential signal outputs of 5-10 GHz and 1.5-3 GHz by means of reasonable frequency assignment; also, carrier signals under various frequencies with different loop bandwidths, different phase noises, different power consumption levels and different locking times can be generated by configuring a programmable charge pump (102), a loop filter (103) parameter, a multi-path voltage-controlled oscillator (104) and a first multiplexer (105) corresponding thereto, a five-stage-division-by-two frequency division link (109) and a corresponding second multiplexer (110) and third multiplexer (112), so as to implement generation of a multi-standard performance reconfigurable I/Q orthogonal carrier.

6. 发明申请

US20170353685A1 ANALOG READOUT PREPROCESSING CIRCUIT FOR CMOS IMAGE SENSOR AND CONTROL METHOD THEREOF 有权
公开(公告)号：US20170353685A1
公开(公告)日：2017-12-07
申请号：US15538514
申请日：2014-12-29
申请人： INSTITUTE OF SEMICONDUCTORS, CHINESE ACADEMY OF SCIENCES
发明人： Liyuan Liu , Nanjian Wu , Zhiqiang Guo
IPC分类号： H04N5/378 , H03M1/46 , H03M1/10 , H03M1/80 , H03M1/02
CPC分类号： H04N5/378 , H03M1/02 , H03M1/1047 , H03M1/468 , H03M1/804
摘要： The present disclosure provides an analog readout preprocessing circuit for a CMOS image sensor and a control method thereof. The analog readout preprocessing circuit comprises an extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion capacitor network 1 configured to achieve readout and analog-to-digital conversion of signals output from the CMOS image sensor; an operational amplifier configured to utilize “virtual short” of two input terminals of the operational amplifier and the charge conservation principle, to achieve a function of extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion, where the extended count-type integration can effectively reduce a thermal noise and a flicker noise within the image sensor; a comparator configured to compare voltages at two terminals to achieve a function of quantization of signals; and a control signal generator configured to provide control signals.

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