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1. 发明申请

US20140235021A1 JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE WITH P-TYPE SILICON GERMANIUM OR SILICON GERMANIUM CARBIDE GATE(S) AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：具有P型硅锗锗或碳化硅碳化硅栅的结型场效应晶体管结构及形成结构的方法
公开(公告)号：US20140235021A1
公开(公告)日：2014-08-21
申请号：US14264125
申请日：2014-04-29
申请人： International Business Machines Corporation
发明人： Xuefeng Liu , Richard A. Phelps , Robert M. Rassel , Xiaowei Tian
IPC分类号： H01L29/66
CPC分类号： H01L29/66916 , H01L27/14679 , H01L29/0649 , H01L29/16 , H01L29/42316 , H01L29/66462 , H01L29/808 , H01L29/8086
摘要： Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.
摘要翻译：公开了具有一个或多个P型硅锗（SiGe）或硅碳化硅（SiGeC）栅极（即，SiGe或SiGeC基异质结JFET）的结型场效应晶体管（JFET）结构的实施例。 P型SiGe或SiGeC栅极允许较低的截止电压（即，较低的Voff），而不增加导通电阻（Ron）。具体来说，P型栅极中的SiGe或SiGeC材料限制了P型掺杂物的扩散，从而确保了P型栅极与N型沟道区域结的关系更明确（即，与分级相反的突发性）。通过明确定义该结，N型沟道区中的耗尽层延伸。延伸耗尽层依次允许更快的夹断（即，需要更低的Voff）。 P型SiGe或SiGeC栅极可以结合到常规的横向JFET结构和/或垂直JFET结构中。本文还公开了形成这种JFET结构的方法的实施例。

2. 发明申请

US20140131800A1 COMPENSATION FOR A CHARGE IN A SILICON SUBSTRATE 有权
公开(公告)号：US20140131800A1
公开(公告)日：2014-05-15
申请号：US13676817
申请日：2012-11-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Alan B. Botula , Mark D. Jaffe , Alvin J. Joseph , Richard A. Phelps , James Slinkman , Randy L. Wolf
IPC分类号： H01L21/66 , H01L29/16
CPC分类号： H01L29/0603 , H01L21/26513 , H01L21/7624 , H01L21/84 , H01L22/14 , H01L22/20 , H01L27/1203 , H01L29/16 , H01L2924/0002 , H01L2924/00
摘要： A silicon device includes an active silicon layer, a buried oxide (BOX) layer beneath the active silicon layer and a high-resistivity silicon layer beneath the BOX layer. The device also includes a harmonic suppression layer at a boundary of the BOX layer and the high-resistivity silicon layer.

3. 发明申请

US20130313607A1 Silicon Controlled Rectifier With Stress-Enhanced Adjustable Trigger Voltage 有权
标题翻译：具有应力增强可调触发电压的硅控整流器
公开(公告)号：US20130313607A1
公开(公告)日：2013-11-28
申请号：US13956795
申请日：2013-08-01
申请人： International Business Machines Corporation
发明人： Renata Camillo-Castillo , Erik M. Dahlstrom , Robert J. Gauthier, JR. , Ephrem G. Gebreselasie , Richard A. Phelps , Yun Shi , Andreas D. Stricker
IPC分类号： H01L29/73
CPC分类号： H01L29/7315 , G06F17/5063 , H01L27/0262 , H01L29/66393 , H01L29/7436
摘要： Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.
摘要翻译：可控硅整流器的器件结构，制造方法，操作方法和设计结构。该方法包括以足以调节SCR的触发电流的水平对可控硅整流器（SCR）的区域施加机械应力。装置和设计结构包括具有阳极的SCR，阴极，第一区域和与第一区域相反的导电类型的第二区域。 SCR的第一和第二区域设置在SCR的阳极和阴极之间的通电路径中。层相对于第一区域定位在半导体衬底的顶表面上，并且被配置为在SCR的第一区域中产生一个足以调节SCR的触发电流的电平的机械应力。

4. 发明授权

US09059276B2 High voltage laterally diffused metal oxide semiconductor 有权
标题翻译：高电压横向扩散金属氧化物半导体
公开(公告)号：US09059276B2
公开(公告)日：2015-06-16
申请号：US13912781
申请日：2013-06-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Natalie B. Feilchenfeld , Theodore J. Letavic , Richard A. Phelps , Santosh Sharma , Yun Shi , Michael J. Zierak
IPC分类号： H01L21/76 , H01L21/335 , H01L21/8232 , H01L21/336 , H01L29/66 , H01L29/78
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/1083 , H01L29/402 , H01L29/404 , H01L29/42368 , H01L29/66681
摘要： High-voltage LDMOS devices with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming an insulator layer of varying depth over a drift region and a body of a substrate. The method further includes forming a control gate and a split gate region by patterning a layer of material on the insulator layer. The split gate region is formed on a first portion of the insulator layer and the control gate is formed on a second portion of the insulator layer, which is thinner than the first portion.
摘要翻译：公开了具有电压线性化场板的高压LDMOS器件和制造方法。该方法包括在漂移区域和基底体上形成不同深度的绝缘体层。该方法还包括通过在绝缘体层上图案化一层材料来形成控制栅极和分裂栅极区域。分离栅极区域形成在绝缘体层的第一部分上，并且控制栅极形成在绝缘体层的比第一部分更薄的第二部分上。

5. 发明授权

US09034712B2 Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage 有权
标题翻译：应力增强LDMOS晶体管，以最小化导通电阻并保持高击穿电压
公开(公告)号：US09034712B2
公开(公告)日：2015-05-19
申请号：US14044163
申请日：2013-10-02
申请人： International Business Machines Corporation
发明人： Renata Camillo-Castillo , Erik M. Dahlstrom , Robert J. Gauthier, Jr. , Ephrem G. Gebreselasie , Richard A. Phelps , Jed H. Rankin , Yun Shi
IPC分类号： H01L21/02 , H01L29/66 , H01L29/78 , H01L29/06 , H01L29/10
CPC分类号： H01L29/66492 , H01L29/0653 , H01L29/1045 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7835 , H01L29/7843
摘要： A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.
摘要翻译：横向扩散金属氧化物半导体场效应晶体管（LDMOS晶体管）采用增强载流子迁移率（即导通电流）的应力层，同时还保持器件的高击穿电压。由于漂移区域的掺杂浓度的增加被最小化，因此保持高的击穿电压。在相邻的衬底中形成阱区和漂移区。第一浅沟槽隔离（STI）区域形成在阱区域上并与阱区域相邻，并且第二STI区域形成在漂移区域上并与漂移区域相邻。应力层沉积在LDMOS晶体管和第二STI区域中，第二STI区域根据应力层的极性将压缩或拉伸应力传播到漂移区域。应力层的一部分可以在栅极上去除以改变栅极下方的反转区域中的应力极性。

6. 发明申请

US20140346597A1 HIGH VOLTAGE LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR 有权
标题翻译：高压侧向扩散金属氧化物半导体
公开(公告)号：US20140346597A1
公开(公告)日：2014-11-27
申请号：US13912781
申请日：2013-06-07
申请人： International Business Machines Corporation
发明人： Natalie B. Feilchenfeld , Theodore J. Letavic , Richard A. Phelps , Santosh Sharma , Yun Shi , Michael J. Zierak
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/1083 , H01L29/402 , H01L29/404 , H01L29/42368 , H01L29/66681
摘要： High-voltage LDMOS devices with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming an insulator layer of varying depth over a drift region and a body of a substrate. The method further includes forming a control gate and a split gate region by patterning a layer of material on the insulator layer. The split gate region is formed on a first portion of the insulator layer and the control gate is formed on a second portion of the insulator layer, which is thinner than the first portion.
摘要翻译：公开了具有电压线性化场板的高压LDMOS器件和制造方法。该方法包括在漂移区域和基底体上形成不同深度的绝缘体层。该方法还包括通过在绝缘体层上图案化一层材料来形成控制栅极和分裂栅极区域。分离栅极区域形成在绝缘体层的第一部分上，并且控制栅极形成在绝缘体层的比第一部分更薄的第二部分上。

7. 发明授权

US08796108B2 Isolated zener diode, an integrated circuit incorporating multiple instances of the zener diode, a method of forming the zener diode and a design structure for the zener diode 有权
标题翻译：隔离齐纳二极管，集成了齐纳二极管多个实例的集成电路，形成齐纳二极管的方法和齐纳二极管的设计结构
公开(公告)号：US08796108B2
公开(公告)日：2014-08-05
申请号：US13945967
申请日：2013-07-19
申请人： International Business Machines Corporation
发明人： Frederick G. Anderson , Natalie B. Feilchenfeld , David L. Harmon , Richard A. Phelps , Yun Shi , Michael J. Zierak
IPC分类号： H01L21/76 , H01L29/866 , H01L29/66 , H01L27/02
CPC分类号： H01L29/866 , H01L21/76 , H01L21/76283 , H01L27/0255 , H01L29/66106
摘要： Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.
摘要翻译：公开了一种齐纳二极管，其具有作为阴极接触区域相对于相邻阴极和阳极阱区域之间的界面的位置的函数的可缩放反向偏压击穿电压（Vb）。具体地，阴极和阳极接触区域被定位成与相应的阴极和阳极阱区域相邻，并进一步被隔离区域分离。然而，当阳极接触区域完全包含在阳极阱区域内时，阴极接触区域的一端横向延伸到阳极阱区域中。为了选择性地调节二极管的Vb（例如，增加长度减小二极管的Vb，反之亦然），可以预定该端的长度。还公开了一种集成电路，其结合具有不同反向偏压击穿电压的二极管的多个实例，形成二极管的方法和二极管的设计结构。

8. 发明授权

US08564067B2 Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure 有权
标题翻译：配置为减少谐波的绝缘体上硅（SOI）结构和形成结构的方法
公开(公告)号：US08564067B2
公开(公告)日：2013-10-22
申请号：US13772402
申请日：2013-02-21
申请人： International Business Machines Corporation
发明人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
IPC分类号： H01L21/70
CPC分类号： H01L21/02488 , H01L21/2652 , H01L21/7624 , H01L21/84 , H01L27/1203 , H01L29/78603
摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.
摘要翻译：公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。本文还公开了用于形成这种半导体结构的方法的实施例。

9. 发明授权

US09383404B2 High resistivity substrate final resistance test structure 有权
标题翻译：高电阻衬底最终电阻测试结构
公开(公告)号：US09383404B2
公开(公告)日：2016-07-05
申请号：US14561830
申请日：2014-12-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jeffrey P. Gambino , Eric D. Johnson , Ian A. McCallum-Cook , Richard A. Phelps , Anthony K. Stamper , Michael J. Zierak
IPC分类号： H01L23/58 , H01L31/04 , G01R31/26 , H01L29/06 , H01L29/10
CPC分类号： G01R31/2601 , H01L21/26513 , H01L22/34 , H01L29/0626
摘要： A high resistivity substrate final resistance test structure, methods of manufacture and testing processes are disclosed. The test structure includes spaced apart implants extending into a high resistivity wafer in at least one kerf region of the wafer. The test structure further includes contacts in direct electrical contact to each of the spaced apart implants.
摘要翻译：公开了一种高电阻率基板最终电阻测试结构，制造和测试方法。测试结构包括在晶片的至少一个切痕区域中延伸到高电阻率晶片的间隔开的植入物。测试结构还包括与每个间隔开的植入物直接电接触的触点。

10. 发明授权

US08946799B2 Silicon controlled rectifier with stress-enhanced adjustable trigger voltage 有权
标题翻译：可控硅整流器，具有应力增强可调触发电压
公开(公告)号：US08946799B2
公开(公告)日：2015-02-03
申请号：US13956795
申请日：2013-08-01
申请人： International Business Machines Corporation
发明人： Renata Camillo-Castillo , Erik M. Dahlstrom , Robert J. Gauthier, Jr. , Ephrem G. Gebreselasie , Richard A. Phelps , Yun Shi , Andreas D. Stricker
IPC分类号： H01L21/84 , H01L29/73 , H01L29/66 , H01L29/74 , H01L27/02 , G06F17/50
CPC分类号： H01L29/7315 , G06F17/5063 , H01L27/0262 , H01L29/66393 , H01L29/7436
摘要： Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.
摘要翻译：可控硅整流器的器件结构，制造方法，操作方法和设计结构。该方法包括以足以调节SCR的触发电流的水平对可控硅整流器（SCR）的区域施加机械应力。装置和设计结构包括具有阳极的SCR，阴极，第一区域和与第一区域相反的导电类型的第二区域。 SCR的第一和第二区域设置在SCR的阳极和阴极之间的通电路径中。层相对于第一区域定位在半导体衬底的顶表面上，并且被配置为在SCR的第一区域中产生一个足以调制SCR的触发电流的电平的机械应力。

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