专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09934975B2 N-type MOSFET and method for manufacturing the same 有权
公开(公告)号：US09934975B2
公开(公告)日：2018-04-03
申请号：US14494447
申请日：2014-09-23
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huilong Zhu , Qiuxia Xu , Yanbo Zhang , Hong Yang
IPC分类号： H01L21/28 , H01L29/66 , H01L29/49 , H01L29/51
CPC分类号： H01L21/28105 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6653 , H01L29/66537 , H01L29/66545
摘要： An N-type MOSFET and a method for manufacturing the same are disclosed. In one aspect, the method comprises forming source/drain regions in a semiconductor substrate. The method also includes forming an interfacial oxide layer on the semiconductor substrate. The method also includes forming a high-k gate dielectric layer on the interfacial oxide layer. The method also includes forming a first metal gate layer on the high-k gate dielectric layer. The method also includes implanting dopants into the first metal gate layer through conformal doping. The method also includes annealing a gate stack to change an effective work function of the gate stack which includes the first metal gate layer, the high-k gate dielectric, and the interfacial oxide layer.

2. 发明授权

US09373622B2 CMOS device with improved accuracy of threshold voltage adjustment and method for manufacturing the same 有权
标题翻译：具有提高阈值电压调整精度的CMOS器件及其制造方法
公开(公告)号：US09373622B2
公开(公告)日：2016-06-21
申请号：US14721386
申请日：2015-05-26
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huaxiang Yin , Hong Yang , Qingzhu Zhang , Qiuxia Xu
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L27/092 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L27/0924
摘要： An CMOS device comprises a plurality of NMOS transistors and a plurality of PMOS transistors, each of which comprises a gate stack constituted of a gate insulating layer and a gate metal layer on a substrate, a source/drain region in the substrate on both sides of the gate stack and a channel region below the gate stack, wherein the gate metal layer of each NMOS transistor comprising a first barrier layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the gate metal layer of each PMOS transistor comprising a first barrier layer, a PMOS work function adjusting layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the first barrier layer in the gate metal layer of the NMOS transistor and the first barrier layer in the gate metal layer of the PMOS transistor contain a doping ion to finely adjust the work function. The semiconductor device and the method for manufacturing the same according to the present disclosure utilize the sacrificial layer to diffuse impurity to the barrier layer so that the adjusting accuracy of the threshold voltage may be effectively improved, thereby facilitating in improving the whole performance of the device.
摘要翻译： CMOS器件包括多个NMOS晶体管和多个PMOS晶体管，每个PMOS晶体管包括由衬底上的栅极绝缘层和栅极金属层构成的栅极堆叠，在衬底的两侧的衬底中的源极/漏极区域栅极堆叠和栅极堆叠下方的沟道区，其中每个NMOS晶体管的栅极金属层包括第一势垒层，NMOS功函数调节层，第二势垒层和填充层，并且其中栅极金属层每个PMOS晶体管包括第一阻挡层，PMOS功函数调整层，NMOS功函数调整层，第二势垒层和填充层，并且其中NMOS晶体管的栅极金属层中的第一势垒层和 PMOS晶体管的栅极金属层中的第一势垒层含有掺杂离子以微调功函数。根据本公开的半导体器件及其制造方法利用牺牲层将杂质扩散到阻挡层，从而可以有效地提高阈值电压的调整精度，从而有助于提高器件的整体性能。

3. 发明申请

US20150048458A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150048458A1
公开(公告)日：2015-02-19
申请号：US14387305
申请日：2012-12-07
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Huilong Zhu , Qiuxia Xu , Yanbo Zhang , Hong Yang
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/265 , H01L21/324
CPC分类号： H01L27/0922 , H01L21/265 , H01L21/28088 , H01L21/28185 , H01L21/324 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L29/4966 , H01L29/517 , H01L29/7833
摘要： Provided are a semiconductor device and a method for manufacturing the same. The method may include: forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high K gate dielectric layer; implanting dopant to the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack comprising the first metal gate layer, the high K gate dielectric layer, and the interfacial oxide layer.
摘要翻译：提供半导体器件及其制造方法。该方法可以包括：在半导体衬底中形成源/漏区; 在所述半导体衬底上形成界面氧化物层; 在界面氧化物层上形成高K栅介电层; 在所述高K栅极电介质层上形成第一金属栅极层; 通过共形掺杂将掺杂剂注入到第一金属栅极层; 以及执行退火以改变包括第一金属栅极层，高K栅介质层和界面氧化物层的栅极堆叠的有效功函数。

4. 发明授权

US09899270B2 Methods for manufacturing semiconductor devices 有权
公开(公告)号：US09899270B2
公开(公告)日：2018-02-20
申请号：US14233320
申请日：2012-12-07
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Qiuxia Xu , Huilong Zhu , Gaobo Xu , Huajie Zhou , Qingqing Liang , Dapeng Chen , Chao Zhao
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/8238 , H01L21/28 , H01L29/49 , H01L29/51 , H01L29/78 , H01L29/66
CPC分类号： H01L21/823828 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/7833
摘要： There is disclosed a method for manufacturing a semiconductor device comprising two opposite types of MOSFETs formed on one semiconductor substrate, the method comprising: forming a portion of the MOSFET on the semiconductor substrate, said portion of said MOSFET comprising source/drains regions located in the semiconductor substrate, a dummy gate stack located between the source/drain region and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack; removing the dummy gate stack of said MOSFET to form a gate opening which exposes the surface of the semiconductor substrate; forming an interfacial oxide layer on the exposed surface of the semiconductor structure; forming a high-K gate dielectric on the interfacial oxide layer within the gate opening; forming a first metal gate layer on the high-K gate dielectric; implanting doping ions in the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill up the gate opening; and annealing to diffuse and accumulate the doping ions at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide, and generating an electric dipole at the lower interface between the high-K gate dielectric and the interfacial oxide by interfacial reaction.

5. 发明授权

US09252059B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09252059B2
公开(公告)日：2016-02-02
申请号：US14233280
申请日：2012-12-07
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Qiuxia Xu , Gaobo Xu , Huajie Zhou , Huilong Zhu , Dapeng Chen
IPC分类号： H01L21/8238 , H01L29/49 , H01L21/28 , H01L21/285 , H01L21/265 , H01L21/268 , H01L21/3213 , H01L21/324 , H01L29/423 , H01L29/10 , H01L29/66 , H01L21/02 , H01L29/51
CPC分类号： H01L21/823857 , H01L21/0206 , H01L21/02301 , H01L21/02304 , H01L21/265 , H01L21/268 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/28194 , H01L21/28568 , H01L21/32139 , H01L21/324 , H01L21/823814 , H01L21/823842 , H01L29/1066 , H01L29/42364 , H01L29/4916 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66477 , H01L29/665 , H01L29/66575
摘要： A method for manufacturing a semiconductor device that comprises two opposite types of MOSFETs formed on one semiconductor substrate, comprising: defining an active region for each of the MOSFETs on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interfacial oxide layer; forming a metal gate layer on the high-K gate dielectric layer; implanting dopant ions in the metal gate layer; forming a Poly-Si layer on the metal gate layer; patterning the Poly-Si layer, the metal gate layer, the high-K gate dielectric layer and the interfacial oxide layer to form a plurality of gate stack structures; forming a plurality of gate spacer surrounding each of the plurality of gate stack structures; and forming a plurality of S/D regions. During activation annealing for forming the S/D regions, the dopant ions implanted in the metal gate layer diffuse and accumulate at an upper interface of the high-K gate dielectric layer to change the characteristics of the metal gates, and at a lower interface of the high-K gate dielectric layer to form electric dipoles with appropriate polarities by interfacial reaction, so as to realize adjusting of the effective work functions of the metal gates of the opposite types of MOSFETs, respectively.
摘要翻译：一种制造半导体器件的方法，包括形成在一个半导体衬底上的两种相反类型的MOSFET，包括：为半导体衬底上的每个MOSFET限定有源区; 在所述半导体衬底的表面上形成界面氧化物层; 在界面氧化物层上形成高K栅介电层; 在高K栅极电介质层上形成金属栅极层; 在所述金属栅极层中注入掺杂离子; 在所述金属栅极层上形成多晶硅层; 图案化多晶硅层，金属栅极层，高K栅极介电层和界面氧化物层以形成多个栅极堆叠结构; 形成围绕所述多个栅极堆叠结构中的每一个的多个栅极间隔; 以及形成多个S / D区域。在用于形成S / D区域的激活退火期间，注入金属栅极层的掺杂剂离子在高K栅极电介质层的上界面处扩散并积聚以改变金属栅极的特性，并且在高K栅极电介质层通过界面反应形成具有适当极性的电偶极子，以分别实现相反类型MOSFET的金属栅极的有效功函数的调整。

6. 发明申请

US20150255557A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150255557A1
公开(公告)日：2015-09-10
申请号：US14722684
申请日：2015-05-27
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huilong Zhu , Qiuxia Xu , Yanbo Zhang , Hong Yang
IPC分类号： H01L29/423 , H01L21/8238 , H01L21/265 , H01L29/45 , H01L27/092 , H01L29/10 , H01L29/78 , H01L29/66 , H01L21/28
CPC分类号： H01L29/42372 , H01L21/2652 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/823821 , H01L21/823842 , H01L27/0924 , H01L29/1083 , H01L29/45 , H01L29/4966 , H01L29/517 , H01L29/66537 , H01L29/66545 , H01L29/66795 , H01L29/6681 , H01L29/78 , H01L29/785 , H01L29/7851
摘要： A semiconductor device and a method of manufacturing the same are disclosed. The method includes forming a semiconductor fin on a semiconductor substrate. The method further includes forming an interfacial oxide layer on a top surface and sidewalls of the semiconductor fin. The method further includes forming a high K gate dielectric layer on the interfacial oxide layer. The method further includes forming a first metal gate layer on the high K gate dielectric layer. The method further includes implanting dopant to the first metal gate layer through conformal doping. The method further includes performing annealing so that the dopants are diffused and accumulated at an upper interface between the high K gate dielectric layer and the first metal gate layer, as well as at a lower interface between the high K gate dielectric layer and the interfacial oxide layer, generating electrical dipoles at the lower interface through interfacial reaction.
摘要翻译：公开了一种半导体器件及其制造方法。该方法包括在半导体衬底上形成半导体鳍片。该方法还包括在半导体鳍片的顶表面和侧壁上形成界面氧化物层。该方法还包括在界面氧化物层上形成高K栅极电介质层。该方法还包括在高K栅介质层上形成第一金属栅极层。该方法还包括通过共形掺杂将掺杂剂注入第一金属栅极层。该方法还包括执行退火，使得掺杂剂在高K栅极介电层和第一金属栅极层之间以及在高K栅极介电层和界面氧化物之间的较低界面处扩散和积聚层，通过界面反应在下界面产生电偶极子。

7. 发明授权

US09029225B2 Method for manufacturing N-type MOSFET 有权
标题翻译：制造N型MOSFET的方法
公开(公告)号：US09029225B2
公开(公告)日：2015-05-12
申请号：US13878046
申请日：2012-12-07
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Qiuxia Xu , Huilong Zhu , Huajie Zhou , Gaobo Xu
IPC分类号： H01L21/336 , H01L21/28 , H01L29/51 , H01L29/49 , H01L29/66
CPC分类号： H01L21/28176 , H01L21/28088 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： The present disclosure discloses a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.
摘要翻译：本公开公开了一种用于制造N型MOSFET的方法，包括：在半导体衬底上形成MOSFET的一部分，所述MOSFET的部分包括半导体衬底中的源极/漏极区，源/ 在半导体衬底之上的漏极区域和围绕替换栅极堆叠的栅极间隔; 去除MOSFET的替换栅极堆叠以形成暴露半导体衬底的表面的栅极开口; 在所述半导体的暴露表面上形成界面氧化物层; 在栅极开口中的界面氧化物层上形成高K栅极电介质层; 在高K栅极电介质层上形成第一金属栅极层; 将掺杂剂离子注入第一金属栅极层; 并且进行退火以使掺杂剂离子在高K栅极介电层和第一金属栅极层之间的上部界面以及高K栅极介电层和界面氧化物层之间的下部界面处扩散和积聚，并且还通过界面反应在高K栅极介电层和界面氧化物层之间的下界面产生电偶极子。

8. 发明申请

US20150041925A1 P TYPE MOSFET AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译： P型MOSFET及其制造方法
公开(公告)号：US20150041925A1
公开(公告)日：2015-02-12
申请号：US14385101
申请日：2012-12-07
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Huilong Zhu , Qiuxia Xu , Yanbo Zhang , Hong Yang
IPC分类号： H01L21/28 , H01L29/78 , H01L29/49 , H01L29/51 , H01L29/66 , H01L21/266
CPC分类号： H01L21/28008 , H01L21/265 , H01L21/26513 , H01L21/266 , H01L21/268 , H01L21/28088 , H01L21/28167 , H01L29/495 , H01L29/4966 , H01L29/4983 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/78 , H01L29/7833
摘要： Provided are P type MOSFETs and methods for manufacturing the same. The method may include forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high K gate dielectric layer; implanting dopants into the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack including the first metal gate layer, the high K gate dielectric, and the interfacial oxide layer.
摘要翻译：提供P型MOSFET及其制造方法。该方法可以包括在半导体衬底中形成源极/漏极区域; 在所述半导体衬底上形成界面氧化物层; 在界面氧化物层上形成高K栅介电层; 在所述高K栅极电介质层上形成第一金属栅极层; 通过共形掺杂将掺杂剂注入第一金属栅极层; 并执行退火以改变包括第一金属栅极层，高K栅极电介质和界面氧化物层的栅极堆叠的有效功函数。

9. 发明申请

US20150325684A1 MANUFACTURING METHOD OF N-TYPE MOSFET 审中-公开
标题翻译： N型MOSFET的制造方法
公开(公告)号：US20150325684A1
公开(公告)日：2015-11-12
申请号：US14375738
申请日：2012-12-07
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Qiuxia Xu , Gaobo Xu , Huajie Zhou , Huilong Zhu
IPC分类号： H01L29/66 , H01L21/324 , H01L21/225 , H01L29/167 , H01L21/02 , H01L21/28 , H01L29/423 , H01L29/51 , H01L21/265
CPC分类号： H01L29/66568 , H01L21/02057 , H01L21/0206 , H01L21/02266 , H01L21/02271 , H01L21/0228 , H01L21/2254 , H01L21/265 , H01L21/268 , H01L21/28176 , H01L21/28185 , H01L21/28211 , H01L21/324 , H01L29/167 , H01L29/42364 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66575 , H01L29/78
摘要： A method for manufacturing an NMOSFET may comprise: defining an active region for the NMOSFET on a semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interfacial oxide layer; forming a metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the metal gate layer; forming a Poly-Si layer on the metal gate layer; patterning the Poly-Si layer, the metal gate layer, the high-K gate dielectric layer and the interfacial oxide layer to form a gate stack; forming a gate spacer surrounding the gate stack; and forming source and drain regions. During annealing for the S/D activation to form the S/D regions, the dopant ions implanted in the metal gate layer may accumulate at both interfaces of the upper interface and the bottom interface of High K dielectric, and electric dipoles with appropriate polarities are generated by interface reaction at the bottom interface, so that the metal gate of the NMOSFET may have its effective work function adjusted.
摘要翻译：一种用于制造NMOSFET的方法可以包括：在半导体衬底上限定NMOSFET的有源区; 在所述半导体衬底的表面上形成界面氧化物层; 在界面氧化物层上形成高K栅介电层; 在高K栅极电介质层上形成金属栅极层; 将掺杂剂离子注入到金属栅极层中; 在所述金属栅极层上形成多晶硅层; 图案化多晶硅层，金属栅极层，高K栅介质层和界面氧化物层以形成栅叠层; 形成围绕所述栅极堆叠的栅极间隔; 并形成源区和漏区。在S / D激活退火以形成S / D区域期间，注入金属栅极层的掺杂剂离子可以在高K电介质的上界面和底界面的两个界面处积聚，并且具有适当极性的电偶极子通过在底部界面处的界面反应产生，使得NMOSFET的金属栅极可以调节其有效的功函数。

10. 发明申请

US20150262887A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20150262887A1
公开(公告)日：2015-09-17
申请号：US14233280
申请日：2012-12-07
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Qiuxia Xu , Gaobo Xu , Huajie Zhou , Huilong Zhu , Dapeng Chen
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/285 , H01L21/265 , H01L21/268 , H01L21/3213 , H01L21/324 , H01L29/423 , H01L29/10 , H01L29/66 , H01L21/02 , H01L29/49
CPC分类号： H01L21/823857 , H01L21/0206 , H01L21/02301 , H01L21/02304 , H01L21/265 , H01L21/268 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/28194 , H01L21/28568 , H01L21/32139 , H01L21/324 , H01L21/823814 , H01L21/823842 , H01L29/1066 , H01L29/42364 , H01L29/4916 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66477 , H01L29/665 , H01L29/66575
摘要： A method for manufacturing a semiconductor device that comprises two opposite types of MOSFETs formed on one semiconductor substrate, comprising: defining an active region for each of the MOSFETs on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interfacial oxide layer; forming a metal gate layer on the high-K gate dielectric layer; implanting dopant ions in the metal gate layer; forming a Poly-Si layer on the metal gate layer; patterning the Poly-Si layer, the metal gate layer, the high-K gate dielectric layer and the interfacial oxide layer to form a plurality of gate stack structures; forming a plurality of gate spacer surrounding each of the plurality of gate stack structures; and forming a plurality of S/D regions. During activation annealing for forming the S/D regions, the dopant ions implanted in the metal gate layer diffuse and accumulate at an upper interface of the high-K gate dielectric layer to change the characteristics of the metal gates, and at a lower interface of the high-K gate dielectric layer to form electric dipoles with appropriate polarities by interfacial reaction, so as to realize adjusting of the effective work functions of the metal gates of the opposite types of MOSFETs, respectively.
摘要翻译：一种制造半导体器件的方法，包括形成在一个半导体衬底上的两种相反类型的MOSFET，包括：为半导体衬底上的每个MOSFET限定有源区; 在所述半导体衬底的表面上形成界面氧化物层; 在界面氧化物层上形成高K栅介电层; 在高K栅极电介质层上形成金属栅极层; 在所述金属栅极层中注入掺杂离子; 在所述金属栅极层上形成多晶硅层; 图案化多晶硅层，金属栅极层，高K栅极介电层和界面氧化物层以形成多个栅极堆叠结构; 形成围绕所述多个栅极堆叠结构中的每一个的多个栅极间隔; 以及形成多个S / D区域。在用于形成S / D区域的激活退火期间，注入金属栅极层的掺杂剂离子在高K栅极电介质层的上界面处扩散并积聚以改变金属栅极的特性，并且在高K栅极电介质层通过界面反应形成具有适当极性的电偶极子，以分别实现相反类型MOSFET的金属栅极的有效功函数的调整。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式