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1. 发明申请

US20150086221A1 SELF BIASED DUAL MODE DIFFERENTIAL CMOS TIA FOR 400G FIBER OPTIC LINKS 有权
标题翻译：自偏双模差分CMOS TIA用于400G光纤链路
公开(公告)号：US20150086221A1
公开(公告)日：2015-03-26
申请号：US14340388
申请日：2014-07-24
申请人： INPHI CORPORATION
发明人： Rahul SHRINGARPURE , Tom Peter Edward BROEKAERT , Gaurav MAHAJAN
IPC分类号： H03F3/45 , H04B10/61 , H03F3/08
CPC分类号： H03F3/082 , H03F1/0205 , H03F3/087 , H03F3/45179 , H03F3/45475 , H03F2200/555 , H04B10/616 , H04B10/693
摘要： A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.
摘要翻译：跨阻放大器（TIA）器件。该器件包括耦合到具有第一和第二TIA的差分TIA的光电二极管，其后面是电平移位/差分放大器（LS / DA）。光电二极管分别耦合在第一和第二TIA的第一和第二输入端之间。 LS / DA可以分别耦合到第一和第二TIA的第一和第二输出端。 TIA器件包括包括多个CMOS电池的半导体衬底，其可以使用28nm工艺技术配置到第一和第二TIA。每个CMOS单元可以包括深n型阱区。可以使用多个CMOS单元来构造第二TIA，使得第二输入端子可以相对于多个第二CMOS单元中的每一个的深n阱的施加电压以任何正电压电平工作。

2. 发明申请

US20180006617A1 SELF BIASED DUAL MODE DIFFERENTIAL CMOS TIA FOR 400G FIBER OPTIC LINKS 审中-公开
公开(公告)号：US20180006617A1
公开(公告)日：2018-01-04
申请号：US15708930
申请日：2017-09-19
申请人： INPHI CORPORATION
发明人： Rahul SHRINGARPURE , Tom Peter Edward BROEKAERT , Gaurav MAHAJAN
IPC分类号： H03F3/08 , H03F1/02 , H03F3/45 , H04B10/69 , H04B10/61
CPC分类号： H03F3/082 , H03F1/0205 , H03F3/087 , H03F3/45179 , H03F3/45475 , H03F2200/555 , H04B10/616 , H04B10/693
摘要： A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.

3. 发明申请

US20190207568A1 SELF BIASED DUAL MODE DIFFERENTIAL CMOS TIA FOR 400G FIBER OPTIC LINKS 审中-公开
公开(公告)号：US20190207568A1
公开(公告)日：2019-07-04
申请号：US16298880
申请日：2019-03-11
申请人： INPHI CORPORATION
发明人： Rahul SHRINGARPURE , Tom Peter Edward BROEKAERT , Gaurav MAHAJAN
IPC分类号： H03F3/08 , H04B10/69 , H03F3/45 , H03F1/02 , H04B10/61
CPC分类号： H03F3/082 , H03F1/0205 , H03F3/087 , H03F3/45179 , H03F3/45475 , H03F2200/555 , H04B10/616 , H04B10/693
摘要： A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.

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