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1. 发明申请

US20120315760A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120315760A1
公开(公告)日：2012-12-13
申请号：US13461088
申请日：2012-05-01
申请人： Hyun-kwan YU , Dong-suk SHIN , Pan-kwi PARK , Ki-eun KIM
发明人： Hyun-kwan YU , Dong-suk SHIN , Pan-kwi PARK , Ki-eun KIM
IPC分类号： H01L21/283 , H01L21/31
CPC分类号： H01L21/823807 , H01L21/28518 , H01L21/76829 , H01L21/76832 , H01L29/665 , H01L29/7843
摘要： A method of manufacturing a semiconductor device includes providing a substrate having a gate structure, a source region, and a drain region formed thereon, and the gate structure includes a gate insulating layer and a gate electrode. The method also includes forming a first stress layer on the substrate, removing the first stress layer, and forming a second stress layer on the substrate.
摘要翻译：制造半导体器件的方法包括提供具有形成在其上的栅极结构，源极区和漏极区的衬底，并且栅极结构包括栅极绝缘层和栅电极。该方法还包括在衬底上形成第一应力层，去除第一应力层，以及在衬底上形成第二应力层。

2. 发明申请

US20120223802A1 ELECTRICAL FUSE DEVICE 失效
标题翻译：电保险装置
公开(公告)号：US20120223802A1
公开(公告)日：2012-09-06
申请号：US13471508
申请日：2012-05-15
申请人： Dong-suk SHIN , Andrew-tae KIM , Hong-jae SHIN
发明人： Dong-suk SHIN , Andrew-tae KIM , Hong-jae SHIN
IPC分类号： H01H85/08
CPC分类号： H01L23/5256 , H01L23/5258 , H01L27/112 , H01L2924/0002 , H01L2924/00
摘要： The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.
摘要翻译：本发明一般涉及半导体器件的熔丝器件，更具体地，涉及一种半导体器件的电熔丝器件。本发明的实施例提供一种能够减少由熔丝链中的不均匀电流密度引起的编程误差的熔丝装置。在一方面，提供一种电熔丝装置，其包括：阳极; 熔丝链路，其在所述熔丝连接件的第一侧上耦合到所述阳极; 连接到所述熔丝链的第二侧上的所述熔断体的阴极; 耦合到阴极的第一阴极接触; 以及耦合到所述阳极的第一阳极触点，所述第一阴极触点和所述第一阳极触点中的至少一个跨越所述熔断体的虚拟延伸表面设置。

3. 发明申请

US20090057819A1 ELECTRICAL FUSE DEVICE 失效
标题翻译：电保险装置
公开(公告)号：US20090057819A1
公开(公告)日：2009-03-05
申请号：US12203256
申请日：2008-09-03
申请人： Dong-suk SHIN , Andrew-tae KIM , Hong-jae SHIN
发明人： Dong-suk SHIN , Andrew-tae KIM , Hong-jae SHIN
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L23/5258 , H01L27/112 , H01L2924/0002 , H01L2924/00
摘要： The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.
摘要翻译：本发明一般涉及半导体器件的熔丝器件，更具体地，涉及一种半导体器件的电熔丝器件。本发明的实施例提供一种能够减少由熔丝链中的不均匀电流密度引起的编程误差的熔丝装置。在一方面，提供一种电熔丝装置，其包括：阳极; 熔丝链路，其在所述熔丝连接件的第一侧上耦合到所述阳极; 连接到所述熔丝链的第二侧上的所述熔断体的阴极; 耦合到阴极的第一阴极接触; 以及耦合到所述阳极的第一阳极触点，所述第一阴极触点和所述第一阳极触点中的至少一个跨越所述熔断体的虚拟延伸表面设置。

4. 发明申请

US20130161751A1 SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS 有权
标题翻译：包括晶体管的半导体器件
公开(公告)号：US20130161751A1
公开(公告)日：2013-06-27
申请号：US13600375
申请日：2012-08-31
申请人： Hoi-sung CHUNG , Dong-hyuk KIM , Myung-sun KIM , Dong-suk SHIN
发明人： Hoi-sung CHUNG , Dong-hyuk KIM , Myung-sun KIM , Dong-suk SHIN
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823418 , H01L29/165 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device includes a substrate having a channel region, a gate insulation layer on the channel region, a gate electrode on the gate insulation layer, and source and drain regions in recesses in the substrate on both sides of the channel region, respectively. The source and drain regions include a lower main layer whose bottom surface is located at level above the bottom of a recess and lower than that of the bottom surface of the gate insulation layer, and a top surface no higher than the level of the bottom surface of the gate insulation layer, and an upper main layer contacting the lower main layer and whose top surface extends to a level higher than that of the bottom surface of the gate insulation layer, and in which the lower layer has a Ge content higher than that of the upper layer.
摘要翻译：半导体器件包括具有沟道区的衬底，沟道区上的栅极绝缘层，栅极绝缘层上的栅电极，以及沟道区两侧的衬底中的凹槽中的源极和漏极区。源极和漏极区域包括下表面位于凹槽底部的平面以上并且低于栅极绝缘层的底表面的下主层，以及不高于底表面的高度的顶表面的栅极绝缘层的上部主层和与下部主层接触的上部主层，其上表面延伸到比栅极绝缘层的底面高的水平，并且其中下层的Ge含量高于栅极绝缘层的底面。的上层。

5. 发明申请

US20080132011A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080132011A1
公开(公告)日：2008-06-05
申请号：US12015646
申请日：2008-01-17
申请人： Sung-young LEE , Dong-suk SHIN
发明人： Sung-young LEE , Dong-suk SHIN
IPC分类号： H01L21/335
CPC分类号： H01L29/78639 , H01L29/66772 , H01L29/78621 , H01L29/78654 , H01L29/78687
摘要： A semiconductor device and related method of manufacture are disclosed. The semiconductor device comprises a gate electrode formed on a semiconductor substrate, an active region containing spaces formed below the gate electrode, a channel region formed between the gate electrode and the spaces, and source and drain regions formed on opposite sides of the gate electrode within the active region. The spaces are formed by etching a semiconductor layer formed below the gate electrode in the active region.
摘要翻译：公开了一种半导体器件及其制造方法。半导体器件包括形成在半导体衬底上的栅电极，形成在栅电极下方的空间的有源区，形成在栅电极和空间之间的沟道区，以及形成在栅电极的相对侧上的源极和漏极区活跃区域。通过在活性区域中蚀刻形成在栅电极下方的半导体层来形成空间。

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