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1. 发明申请

US20050167708A1 Optimized photodiode process for improved transfer gate leakage 有权
标题翻译：优化光电二极管工艺，改善传输门漏电
公开(公告)号：US20050167708A1
公开(公告)日：2005-08-04
申请号：US11094363
申请日：2005-03-31
申请人： Howard Rhodes , Richard Mauritzson , Inna Patrick
发明人： Howard Rhodes , Richard Mauritzson , Inna Patrick
IPC分类号： H01L21/00 , H01L27/146 , H01L31/0352 , H01L31/062 , H01L31/103
CPC分类号： H01L27/14643 , H01L27/14601 , H01L31/03529 , H01L31/103 , Y02E10/50
摘要： An image sensing circuit and method is disclosed, wherein a photodiode is formed in a substrate through a series of angled implants. The photodiode is formed by a first, second and third implant, wherein at least one of the implants are angled so as to allow the resulting photodiode to extend out beneath an adjoining gate. Under an alternate embodiment, a fourth implant is added, under an increased implant angle, in the region of the second implant. The resulting photodiode structure substantially reduces or eliminates transfer gate subthreshold leakage.
摘要翻译：公开了一种图像感测电路和方法，其中通过一系列成角度的植入物在基板中形成光电二极管。光电二极管由第一，第二和第三植入物形成，其中植入物中的至少一个是成角度的，以便使得到的光电二极管延伸出邻近的栅极之下。在替代实施例中，在第二植入物的区域内以增加的植入角度添加第四植入物。所得到的光电二极管结构基本上减少或消除传输门极阈值泄漏。

2. 发明申请

US20050179059A1 Well for CMOS imager and method of formation 有权
标题翻译：好的CMOS成像器和形成方法
公开(公告)号：US20050179059A1
公开(公告)日：2005-08-18
申请号：US11105419
申请日：2005-04-14
申请人： Howard Rhodes , Inna Patrick , Richard Mauritzson
发明人： Howard Rhodes , Inna Patrick , Richard Mauritzson
IPC分类号： H01L21/00 , H01L27/10 , H01L27/146
CPC分类号： H01L27/1463 , H01L27/14601 , H01L27/14689
摘要： A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode.
摘要翻译：公开了位于第一导电类型的衬底中并且低于晶体管栅极的电活性部分的沟道长度的约一半的第一导电类型的阱区。阱区域从第二导电类型的钉扎光电二极管的电荷收集区域横向移位。

3. 发明申请

US20070080424A1 Well for CMOS imager and method of formation 有权
标题翻译：好的CMOS成像器和形成方法
公开(公告)号：US20070080424A1
公开(公告)日：2007-04-12
申请号：US11636658
申请日：2006-12-11
申请人： Howard Rhodes , Inna Patrick , Richard Mauritzson
发明人： Howard Rhodes , Inna Patrick , Richard Mauritzson
IPC分类号： H01L29/00
CPC分类号： H01L27/1463 , H01L27/14601 , H01L27/14689
摘要： A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode.
摘要翻译：公开了位于第一导电类型的衬底中并且低于晶体管栅极的电活性部分的沟道长度的约一半的第一导电类型的阱区。阱区域从第二导电类型的钉扎光电二极管的电荷收集区域横向移位。

4. 发明申请

US20050112789A1 Well for CMOS imager and method of formation 有权
公开(公告)号：US20050112789A1
公开(公告)日：2005-05-26
申请号：US11025960
申请日：2005-01-03
申请人： Howard Rhodes , Inna Patrick , Richard Mauritzson
发明人： Howard Rhodes , Inna Patrick , Richard Mauritzson
IPC分类号： H01L21/00 , H01L27/10 , H01L27/146
CPC分类号： H01L27/1463 , H01L27/14601 , H01L27/14689
摘要： A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode.

5. 发明申请

US20050087782A1 Optimized photodiode process for improved transfer gate leakage 有权
公开(公告)号：US20050087782A1
公开(公告)日：2005-04-28
申请号：US10689712
申请日：2003-10-22
申请人： Howard Rhodes , Richard Mauritzson , Inna Patrick
发明人： Howard Rhodes , Richard Mauritzson , Inna Patrick
IPC分类号： H01L21/00 , H01L27/146 , H01L31/0352 , H01L31/062 , H01L31/103
CPC分类号： H01L27/14643 , H01L27/14601 , H01L31/03529 , H01L31/103 , Y02E10/50
摘要： An image sensing circuit and method is disclosed, wherein a photodiode is formed in a substrate through a series of angled implants. The photodiode is formed by a first, second and third implant, wherein at least one of the implants are angled so as to allow the resulting photodiode to extend out beneath an adjoining gate. Under an alternate embodiment, a fourth implant is added, under an increased implant angle, in the region of the second implant. The resulting photodiode structure substantially reduces or eliminates transfer gate subthreshold leakage.

6. 发明申请

US20070246788A1 N-well barrier pixels for improved protection of dark reference columns and rows from blooming and crosstalk 审中-公开
标题翻译： N阱势垒像素，用于改善暗参考柱和行的防范和串扰的保护
公开(公告)号：US20070246788A1
公开(公告)日：2007-10-25
申请号：US11408194
申请日：2006-04-21
申请人： Richard Mauritzson , Inna Patrick
发明人： Richard Mauritzson , Inna Patrick
IPC分类号： H01L27/14 , H01L21/00
CPC分类号： H01L27/14654 , H01L27/1463 , H01L27/14689
摘要： The barrier region for isolating one or more dark regions of the pixel array of an image sensor from the active array or from the peripheral circuitry includes N-well pixel isolation region. The N-well pixel isolation region includes at least one N-well implant or at least one N-well stripe. The N-well pixel isolation region is adjacent the pixel cells which comprise the dark region. The addition of the N-well in the barrier region improves the isolation properties of the barrier region by reducing or eliminating the neutral P− EPI region in the barrier pixel area below the N-well isolation region.
摘要翻译：用于将图像传感器的像素阵列的一个或多个暗区域与有源阵列或外围电路隔离的势垒区域包括N阱像素隔离区域。 N阱像素隔离区域包括至少一个N阱注入或至少一个N阱条纹。 N阱像素隔离区域与包括暗区域的像素单元相邻。通过减少或消除N阱隔离区域之下的势垒像素区域中的中性P- EPI区域，在屏障区域中添加N-阱提高了屏障区域的隔离性能。

7. 发明授权

US07829368B2 Methods of forming double pinned photodiodes 有权
标题翻译：形成双针光电二极管的方法
公开(公告)号：US07829368B2
公开(公告)日：2010-11-09
申请号：US12389973
申请日：2009-02-20
申请人： Inna Patrick
发明人： Inna Patrick
IPC分类号： H01L21/00
CPC分类号： H01L27/14609 , H01L27/14603 , H01L27/14643 , H01L27/14689 , H01L31/03529 , Y02E10/50
摘要： A pinned photodiode, which is a double pinned photodiode having increased electron capacitance, and a method for forming the same are disclosed. The invention provides a pinned photodiode structure comprising a substrate base over which is a first layer of semiconductor material. There is a base layer of a first conductivity type, wherein the base layer of a first conductivity type is the substrate base or is a doped layer over the substrate base. At least one doped region of a second conductivity type is below the surface of said first layer, and extends to form a first junction with the base layer. A doped surface layer of a first conductivity type is over the at least one region of a second conductivity type and forms a second junction with said at least one region of a second conductivity type.
摘要翻译：公开了一种钉扎光电二极管，其是具有增加的电子电容的双引脚光电二极管及其形成方法。本发明提供了一种钉扎光电二极管结构，其包括基底，第一半导体材料层。存在第一导电类型的基底层，其中第一导电类型的基底层是衬底基底，或者是衬底基底上的掺杂层。至少一个第二导电类型的掺杂区域位于所述第一层的表面之下，并延伸以与基底层形成第一结。第一导电类型的掺杂表面层在第二导电类型的至少一个区域之上，并且与所述至少一个第二导电类型的区域形成第二结。

8. 发明申请

US20090026511A1 Isolation process and structure for CMOS imagers 审中-公开
标题翻译： CMOS成像器的隔离过程和结构
公开(公告)号：US20090026511A1
公开(公告)日：2009-01-29
申请号：US12230070
申请日：2008-08-22
申请人： Frederick Brady , Inna Patrick
发明人： Frederick Brady , Inna Patrick
IPC分类号： H01L31/112 , H01L31/103 , H01L21/265 , H01L21/761 , H01L23/58
CPC分类号： H01L27/14603 , H01L27/1463 , H01L27/14643 , H01L27/14683 , H01L27/14689
摘要： A barrier implanted region of a first conductivity type formed in lieu of an isolation region of a pixel sensor cell that provides physical and electrical isolation of photosensitive elements of adjacent pixel sensor cells of a CMOS imager. The barrier implanted region comprises a first region having a first width and a second region having a second width greater than the first width, the second region being located below the first region. The first region is laterally spaced from doped regions of a second conductivity type of adjacent photodiodes of pixel sensor cells of a CMOS imager.
摘要翻译：形成第一导电类型的势垒注入区域代替像素传感器单元的隔离区域，其提供CMOS成像器的相邻像素传感器单元的感光元件的物理和电隔离。势垒注入区域包括具有第一宽度的第一区域和具有大于第一宽度的第二宽度的第二区域，第二区域位于第一区域下方。第一区域与CMOS成像器的像素传感器单元的第二导电类型的相邻光电二极管的掺杂区域横向间隔开。

9. 发明授权

US07432121B2 Isolation process and structure for CMOS imagers 有权
标题翻译： CMOS成像器的隔离过程和结构
公开(公告)号：US07432121B2
公开(公告)日：2008-10-07
申请号：US11135517
申请日：2005-05-24
申请人： Frederick Brady , Inna Patrick
发明人： Frederick Brady , Inna Patrick
IPC分类号： H01L21/00
CPC分类号： H01L27/14603 , H01L27/1463 , H01L27/14643 , H01L27/14683 , H01L27/14689
摘要： A barrier implanted region of a first conductivity type formed in lieu of an isolation region of a pixel sensor cell that provides physical and electrical isolation of photosensitive elements of adjacent pixel sensor cells of a CMOS imager. The barrier implanted region comprises a first region having a first width and a second region having a second width greater than the first width, the second region being located below the first region. The first region is laterally spaced from doped regions of a second conductivity type of adjacent photodiodes of pixel sensor cells of a CMOS imager.
摘要翻译：形成第一导电类型的势垒注入区域代替像素传感器单元的隔离区域，其提供CMOS成像器的相邻像素传感器单元的感光元件的物理和电隔离。势垒注入区域包括具有第一宽度的第一区域和具有大于第一宽度的第二宽度的第二区域，第二区域位于第一区域下方。第一区域与CMOS成像器的像素传感器单元的第二导电类型的相邻光电二极管的掺杂区域横向间隔开。

10. 发明申请

US20060046338A1 Method of fabricating a storage gate pixel design 有权
公开(公告)号：US20060046338A1
公开(公告)日：2006-03-02
申请号：US10923692
申请日：2004-08-24
申请人： Inna Patrick , Sungkwon Hong
发明人： Inna Patrick , Sungkwon Hong
IPC分类号： H01L21/00
CPC分类号： H01L27/14609 , H01L27/14643 , H01L27/14689
摘要： A method of fabricating a pixel cell having a shutter gate structure. First and second charge barriers are respectively created between a photodiode and a first charge storage region and between the first storage region and a floating diffusion region. A global shutter gate is formed to control the charge barrier and transfer charges from the photodiode to the first charge storage region by effectively lowering the first charge barrier. A transfer transistor acts to transfer charges from the first storage region to the floating diffusion region by reducing the second charge barrier.

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