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1. 发明申请

US20120112829A1 SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME 失效
标题翻译：半导体器件及其控制方法
公开(公告)号：US20120112829A1
公开(公告)日：2012-05-10
申请号：US13283882
申请日：2011-10-28
申请人： Hitoshi TANAKA , Kazutaka MIYANO
发明人： Hitoshi TANAKA , Kazutaka MIYANO
IPC分类号： H01L25/00
CPC分类号： H03K3/012 , H01L25/00 , H01L2924/0002 , H02M3/155 , H02M2001/0029 , H01L2924/00
摘要： A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V2 from a first voltage V1; and a control circuit that generates the current control signal OVDR, makes a current that is flowed by the current mirror increase by a first transition of the current control signal OVDR, and makes the current that is flowed by the current mirror decrease by a second transition of the current control signal OVDR. The control circuit includes a slew-rate processing unit that makes a second slew rate of the current control signal OVDR related to the second transition be smaller than a first slew rate of the current control signal OVDR related to the first transition.
摘要翻译：一种半导体器件包括：调节器，包括由电流镜配置的运算放大器，并从第一电压V1产生第二电压V2; 以及产生电流控制信号OVDR的控制电路，使由电流镜流动的电流增加电流控制信号OVDR的第一跃迁，并且使由电流镜流动的电流减小第二跃迁的电流控制信号OVDR。该控制电路包括使与第二转变相关的电流控制信号OVDR的第二转换速率小于与第一转换相关的电流控制信号OVDR的第一转换速率的转换速率处理单元。

2. 发明申请

US20100156489A1 DLL CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM 失效
标题翻译： DLL电路，包括其的半导体器件和数据处理系统
公开(公告)号：US20100156489A1
公开(公告)日：2010-06-24
申请号：US12646548
申请日：2009-12-23
申请人： Kazutaka MIYANO
发明人： Kazutaka MIYANO
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0814
摘要： To provide a DLL circuit including: a first phase determination circuit that compares phases of rising edges of an external clock and a first internal clock; a second phase determination circuit that compares phases of falling edges of the external clock and the first internal clock; an adjusting unit that adjusts positions of active edges of internal clocks based on determination results; and a control circuit that sets one of adjustment amounts of the second and third internal clocks to a larger value than the other, in response to a fact that adjustment directions of the active edges of the second and third internal clocks are mutually the same. With this arrangement, a duty can be set nearer to 50% while performing phase adjustment. Accordingly, the time required to lock the DLL circuit can be shortened.
摘要翻译：提供一种DLL电路，包括：第一相位确定电路，其比较外部时钟的上升沿和第一内部时钟的相位; 第二相位确定电路，其比较所述外部时钟的下降沿和所述第一内部时钟的相位; 调整单元，其基于确定结果调整内部时钟的有效边沿的位置; 以及控制电路，其响应于第二和第三内部时钟的有效边缘的调整方向相互相同的事实，将第二和第三内部时钟的调整量中的一个设置为比另一个更大的值。通过这种安排，在执行相位调整时可以将任务设定为接近50％。因此，可以缩短锁定DLL电路所需的时间。

3. 发明申请

US20120134223A1 CLOCK GENERATING CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND DATA PROCESSING SYSTEM 有权
标题翻译：时钟发生电路，包括其的半导体器件和数据处理系统
公开(公告)号：US20120134223A1
公开(公告)日：2012-05-31
申请号：US13360576
申请日：2012-01-27
申请人： Kazutaka MIYANO
发明人： Kazutaka MIYANO
IPC分类号： G11C7/22 , H03L7/091
CPC分类号： H03L7/0816 , H03L7/0814 , H03L2207/14
摘要： A semiconductor device includes a delay circuit supplied with a first clock signal and a first phase determination signal and producing a second clock signal, the delay circuit controlling the second clock signal such that a delay in phase of the second clock signal to the first clock signal is increased when the first phase determination signal takes a first logic level and decreased when the first phase determination signal takes a second logic level, and a phase determining circuit supplied with the first clock signal and a third clock signal, which is produced in response to the second clock signal, and producing a second phase determination signal in response to a difference in phase between the first clock signal and the third clock signal.
摘要翻译：半导体器件包括提供有第一时钟信号和第一相位确定信号并产生第二时钟信号的延迟电路，所述延迟电路控制第二时钟信号，使得第二时钟信号的相位延迟与第一时钟信号当第一相位确定信号获取第一逻辑电平并且当第一相位确定信号取第二逻辑电平时减小，并且相位确定电路被提供有第一时钟信号和第三时钟信号，第三时钟信号响应于第二时钟信号，并且响应于第一时钟信号和第三时钟信号之间的相位差而产生第二相位确定信号。

4. 发明申请

US20120124409A1 SEMICONDUCTOR DEVICE HAVING DLL CIRCUIT 有权
标题翻译：具有DLL电路的半导体器件
公开(公告)号：US20120124409A1
公开(公告)日：2012-05-17
申请号：US13291733
申请日：2011-11-08
申请人： Kazutaka MIYANO
发明人： Kazutaka MIYANO
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , G11C7/222 , H03K5/1506 , H03L7/0814 , H03L7/0816
摘要： A semiconductor device with a clock control circuit that outputs an internal clock signal configured by delaying external clock signals based on at least a feedback clock signal; a plurality of output buffers that output data in synchronization with the internal clock signal; an output replica that is a replica of the output buffers and that generates the feedback clock signal in synchronization with the internal clock signal and supplies the feedback clock signal to the clock control circuit; and a clock tree that receives the internal clock signal from the clock control circuit and transmits the internal clock signal to the plurality of output buffers and the output replica such that signal line are substantially equal to one another.
摘要翻译：一种具有时钟控制电路的半导体器件，其输出通过至少基于反馈时钟信号延迟外部时钟信号而配置的内部时钟信号; 多个输出缓冲器，其与内部时钟信号同步地输出数据; 输出副本，其是输出缓冲器的副本，并且与内部时钟信号同步地产生反馈时钟信号，并将反馈时钟信号提供给时钟控制电路; 以及时钟树，其从时钟控制电路接收内部时钟信号，并将内部时钟信号发送到多个输出缓冲器和输出副本，使得信号线基本上彼此相等。

5. 发明申请

US20090289680A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090289680A1
公开(公告)日：2009-11-26
申请号：US12468608
申请日：2009-05-19
申请人： Kazutaka MIYANO
发明人： Kazutaka MIYANO
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03L7/0814
摘要： A semiconductor device includes a first duty determining circuit (20) and a second duty determining circuit (30). The first duty determining circuit (20) determines a duty correction condition for an input signal in a first predetermined cycle longer than a cycle of the input signal to obtain a first determination result and updates the duty correction condition for the input signal on the basis of the first determination result. The second duty determining circuit (30) determines the duty correction condition for the input signal in a second predetermined cycle shorter than first predetermined cycle to obtain a second determination result and updates the duty correction condition for the input signal only when the second determination result is fixed during a predetermined period.
摘要翻译：半导体器件包括第一占空比确定电路（20）和第二占空比确定电路（30）。第一占空比确定电路（20）在比输入信号的周期长的第一预定周期中确定输入信号的占空比校正条件以获得第一确定结果，并且基于以下方式更新输入信号的占空比校正条件第一个确定结果。第二占空比确定电路（30）在比第一预定周期短的第二预定周期中确定输入信号的占空比校正条件，以获得第二确定结果，并且仅当第二确定结果为在预定时段内固定。

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