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1. 发明授权

US07161830B2 Clock synchronized nonvolatile memory device 有权
公开(公告)号：US07161830B2
公开(公告)日：2007-01-09
申请号：US11024643
申请日：2004-12-30
申请人： Hitoshi Miwa , Hiroaki Kotani
发明人： Hitoshi Miwa , Hiroaki Kotani
IPC分类号： G11C11/34
CPC分类号： G11C16/32 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643 , G11C2211/5647 , G11C2211/565
摘要： A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.

2. 发明授权

US06747941B2 Clock synchronized non-volatile memory device 有权
标题翻译：时钟同步非易失性存储器件
公开(公告)号：US06747941B2
公开(公告)日：2004-06-08
申请号：US10373751
申请日：2003-02-27
申请人： Hitoshi Miwa , Hiroaki Kotani
发明人： Hitoshi Miwa , Hiroaki Kotani
IPC分类号： G11C1134
CPC分类号： G11C16/32 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643 , G11C2211/5647 , G11C2211/565
摘要： A non volatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, plural nonvolatile memory cells, and first and second volatile memories. The clock and command terminals respectively receive a first clock signal and commands including read and program commands. In response to the read command, the control circuit controls reading data from the memory cells, stores read data to the second volatile memory, transfers data to first volatile memory, and outputs data via the other terminal except the command terminal in response to the first clock signal. In response to the program command, the control circuit controls receiving data via the other terminal except the command terminal in response to the first clock signal, stores received data to the first volatile memory, transfers data to the second volatile memory, and writes data to the memory cells.
摘要翻译：一种非易失性存储装置，包括控制电路，具有时钟，命令和其他终端的多个终端，多个非易失性存储单元以及第一和第二易失性存储器。时钟和命令终端分别接收第一时钟信号和包括读取和编程命令的命令。响应于读取命令，控制电路控制从存储器单元读取数据，将读取的数据存储到第二易失性存储器，将数据传送到第一易失性存储器，并且响应于第一可变存储器，经由除命令终端之外的另一终端输出数据时钟信号。响应于程序命令，控制电路响应于第一时钟信号控制除了命令终端之外的另一终端的接收数据，将接收的数据存储到第一易失性存储器，将数据传送到第二易失性存储器，并将数据写入记忆细胞。

3. 发明授权

US06366495B2 Nonvolatile memory device and refreshing method 有权
标题翻译：非易失性存储器件和刷新方法
公开(公告)号：US06366495B2
公开(公告)日：2002-04-02
申请号：US09817021
申请日：2001-03-27
申请人： Hitoshi Miwa , Hiroaki Kotani
发明人： Hitoshi Miwa , Hiroaki Kotani
IPC分类号： G11C1134
CPC分类号： G11C16/32 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643 , G11C2211/5647 , G11C2211/565
摘要： At the data programming, plural data bit is transformed by a data transforming logic circuit into multi-value data according to the combination of bits, and the transformed data are sequentially transferred to a latch circuit connected to bit lines of a memory array. A program pulse is generated according to the latched data and is applied to a memory element at a state corresponding to the multi-value data. During data reading, the states of the memory elements are read out by changing the read voltage to intermediate values of individual threshold values and latched in a register. The original data may be restored by a data inverse transforming logic circuit based on the multi-value data stored in the register.
摘要翻译：在数据编程中，根据比特的组合，将数据变换逻辑电路将多个数据位变换为多值数据，并将变换后的数据依次传送到与存储器阵列的位线连接的锁存电路。根据锁存的数据产生编程脉冲，并以对应于多值数据的状态将其应用于存储元件。在数据读取期间，通过将读取的电压改变为各个阈值的中间值并将其锁存在寄存器中来读出存储器元件的状态。可以通过基于存储在寄存器中的多值数据的数据逆变换逻辑电路来恢复原始数据。

4. 发明授权

US08804431B2 Clock synchronized non-volatile memory device 有权
标题翻译：时钟同步非易失性存储器件
公开(公告)号：US08804431B2
公开(公告)日：2014-08-12
申请号：US13453079
申请日：2012-04-23
申请人： Hitoshi Miwa , Hiroaki Kotani
发明人： Hitoshi Miwa , Hiroaki Kotani
IPC分类号： G11C11/34
CPC分类号： G11C16/32 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643 , G11C2211/5647 , G11C2211/565
摘要： A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.
摘要翻译：一种非易失性存储装置，包括控制电路，具有时钟，命令和其他端子的多个端子，数据和命令寄存器以及多个非易失性存储单元。时钟终端接收时钟信号，命令终端接收包括读取和编程命令的命令。数据寄存器从外部接收数据并输出数据。控制电路从用于控制设备的存储器读取操作步骤。控制电路响应于读取命令控制从存储器单元读取数据，将读取的数据存储到数据寄存器，并且经由另一终端而不是命令终端基于时钟信号输出读取数据。控制电路响应于程序命令，控制基于时钟信号经由另一终端而不是命令终端接收数据，将接收的数据存储到数据寄存器，并将接收的数据写入存储单元。

5. 发明授权

US07542339B2 Clock synchronized non-volatile memory device 有权
标题翻译：时钟同步非易失性存储器件
公开(公告)号：US07542339B2
公开(公告)日：2009-06-02
申请号：US11892041
申请日：2007-08-20
申请人： Hitoshi Miwa , Hiroaki Kotani
发明人： Hitoshi Miwa , Hiroaki Kotani
IPC分类号： G11C11/34
CPC分类号： G11C16/32 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643 , G11C2211/5647 , G11C2211/565
摘要： A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.
摘要翻译：一种非易失性存储装置，包括控制电路，具有时钟，命令和其他端子的多个端子，数据和命令寄存器以及多个非易失性存储单元。时钟终端接收时钟信号，命令终端接收包括读取和编程命令的命令。数据寄存器从外部接收数据并输出数据。控制电路从用于控制设备的存储器读取操作步骤。控制电路响应于读取命令控制从存储器单元读取数据，将读取的数据存储到数据寄存器，并且经由另一终端而不是命令终端基于时钟信号输出读取数据。控制电路响应于程序命令，控制基于时钟信号经由另一终端而不是命令终端接收数据，将接收的数据存储到数据寄存器，并将接收的数据写入存储单元。

6. 发明授权

US07193894B2 Clock synchronized nonvolatile memory device 有权
公开(公告)号：US07193894B2
公开(公告)日：2007-03-20
申请号：US10810613
申请日：2004-03-29
申请人： Hitoshi Miwa , Hiroaki Kotani
发明人： Hitoshi Miwa , Hiroaki Kotani
IPC分类号： G11C11/34
CPC分类号： G11C16/32 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643 , G11C2211/5647 , G11C2211/565
摘要： A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.

7. 发明申请

US20060198201A1 Multi-bits storage memory 有权
标题翻译：多位存储存储器
公开(公告)号：US20060198201A1
公开(公告)日：2006-09-07
申请号：US11429318
申请日：2006-05-08
申请人： Hitoshi Miwa , Hiroaki Kotani
发明人： Hitoshi Miwa , Hiroaki Kotani
IPC分类号： G11C16/04
CPC分类号： G11C16/32 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643 , G11C2211/5647 , G11C2211/565
摘要： A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.
摘要翻译：一种非易失性存储装置，包括控制电路，具有时钟，命令和其他端子的多个端子，数据和命令寄存器以及多个非易失性存储单元。时钟终端接收时钟信号，命令终端接收包括读取和编程命令的命令。数据寄存器从外部接收数据并输出数据。控制电路从用于控制设备的存储器读取操作步骤。控制电路响应于读取命令控制从存储器单元读取数据，将读取的数据存储到数据寄存器，并且经由另一终端而不是命令终端基于时钟信号输出读取数据。控制电路响应于程序命令，控制基于时钟信号经由另一终端而不是命令终端接收数据，将接收的数据存储到数据寄存器，并将接收的数据写入存储单元。

8. 发明申请

US20050146941A1 Clock synchronized nonvolatile memory device 有权
公开(公告)号：US20050146941A1
公开(公告)日：2005-07-07
申请号：US11024643
申请日：2004-12-30
申请人： Hitoshi Miwa , Hiroaki Kotani
发明人： Hitoshi Miwa , Hiroaki Kotani
IPC分类号： G11C11/56 , G11C5/00
CPC分类号： G11C16/32 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643 , G11C2211/5647 , G11C2211/565
摘要： A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.

9. 发明授权

US06868006B2 Clock synchronized non-volatile memory device 失效
标题翻译：时钟同步非易失性存储器件
公开(公告)号：US06868006B2
公开(公告)日：2005-03-15
申请号：US10373737
申请日：2003-02-27
申请人： Hitoshi Miwa , Hiroaki Kotani
发明人： Hitoshi Miwa , Hiroaki Kotani
IPC分类号： G11C11/56 , G11C11/34
CPC分类号： G11C16/32 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643 , G11C2211/5647 , G11C2211/565
摘要： A nonvolatile memory apparatus including a control circuit, plural terminals including clock, command and other terminals, a clock generator, and plural nonvolatile memory cells. The clock and command terminals respectively receives a first clock signal and commands including read and program commands. The clock generator generates a second clock signal. In response to the read command, the control circuit controls reading data from the memory cells, and outputting data via the other terminal not the command terminal in response to the first clock signal. In response to the program command, the control circuit controls receiving data via the other terminal not the command terminal in response to the first clock signal, and writing data to the memory cells. The data writing to ones of said nonvolatile memory cells is performed using the second clock signal.
摘要翻译：一种包括控制电路的非易失性存储装置，包括时钟，命令和其他终端的多个终端，时钟发生器和多个非易失性存储单元。时钟和命令终端分别接收第一时钟信号和包括读取和编程命令的命令。时钟发生器产生第二个时钟信号。响应于读取命令，控制电路控制来自存储单元的读取数据，并且响应于第一时钟信号，经由另一终端而不是命令终端输出数据。响应于程序命令，控制电路响应于第一时钟信号控制经由另一终端而不是命令终端的接收数据，并将数据写入存储单元。使用第二时钟信号来执行对所述非易失性存储器单元的数据写入。

10. 发明授权

US06804147B2 Clock synchronized non-volatile memory device 失效
标题翻译：时钟同步非易失性存储器件
公开(公告)号：US06804147B2
公开(公告)日：2004-10-12
申请号：US10223370
申请日：2002-08-20
申请人： Hitoshi Miwa , Hiroaki Kotani
发明人： Hitoshi Miwa , Hiroaki Kotani
IPC分类号： G11C1134
CPC分类号： G11C16/32 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643 , G11C2211/5647 , G11C2211/565
摘要： A nonvolatile memory apparatus which includes a plurality of terminals including a clock terminal, a command terminal and other terminal, a converter circuit, end a plurality of nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands which include a read command and a program command. In an operation in response to the read command received from the command terminal, the nonvolatile memory apparatus is capable of reading data in parallel from ones of the nonvolatile memory cells, converts parallel type data to serial type data by the converter circuit and serially outputs data via the other terminal not the command terminal in response to the clock signal. Also in an operation in response to the program command, the nonvolatile memory apparatus serially receives data via the other terminal not the command terminal in response to the clock signal, converts serial type data to parallel type data by the converter circuit and is capable of writing data in parallel to ones of the nonvolatile memory cells.
摘要翻译：一种非易失性存储装置，包括包括时钟端子，命令端子和其他端子的多个端子，转换器电路，结束多个非易失性存储单元。时钟终端接收时钟信号，并且命令终端接收包括读取命令和程序命令的命令。在响应于从命令终端接收到的读取命令的操作中，非易失性存储装置能够从非易失性存储单元中并行读取数据，并且通过转换器电路将并行类型数据转换为串行数据，并且串行地输出数据通过其他终端不是响应于时钟信号的命令终端。另外，在响应于程序命令的操作中，非易失性存储装置响应于时钟信号而经由另一终端而不是命令终端串行地接收数据，通过转换器电路将串行类型数据转换成并行型数据，并且能够写入与非易失性存储单元中的数据并行的数据。

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