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1. 发明授权

US06375784B1 Method of manufacturing reversible heat-sensitive recording medium and reversible heat-sensitive recording medium manufactured thereby 失效
标题翻译：制造可逆热敏记录介质的方法和由此制造的可逆热敏记录介质
公开(公告)号：US06375784B1
公开(公告)日：2002-04-23
申请号：US09534333
申请日：2000-03-24
申请人： Haruhiko Ohsawa , Makibi Nakanishi , Hiroyuki Morinaka , Junpei Nakagawa , Koh Fujii
发明人： Haruhiko Ohsawa , Makibi Nakanishi , Hiroyuki Morinaka , Junpei Nakagawa , Koh Fujii
IPC分类号： B41M540
CPC分类号： B41M5/42 , B41M5/305 , B41M5/48
摘要： A method of manufacturing a reversible heat-sensitive recording medium capable of manufacturing a reversible heat-sensitive recording medium invulnerable toward scratches, etc. even when printing/erasing is repeated under situation where dirt and dust tend to attach to the reversible heat-sensitive recording medium, thus providing increase durability of the reversible heat-sensitive recording medium against repeated printing/erasing. In the method of manufacturing the reversible heat-sensitive recording medium containing a reversible heat-sensitive recording layer and a substrate sheet, a reversible heat-sensitive recording sheet or a reversible heat-sensitive recording transfer sheet having the reversible heat-sensitive recording layer applied to the substrate sheet through welding, after which a protective layer is formed on the reversible heat-sensitive recording layer.
摘要翻译：制造可逆热敏记录介质的方法，即使在污物和灰尘倾向于附着到可逆热敏记录的情况下，即使在打印/擦除时也能够制造不易于划痕等的可逆热敏记录介质从而提供可逆热敏记录介质的耐久性，从而反复打印/擦除。在制造包含可逆热敏记录层和基片的可逆热敏记录介质的方法中，可逆的热敏记录片或可逆的热敏记录转印片具有可逆的热敏记录层通过焊接到基板上，之后在可逆热敏记录层上形成保护层。

2. 发明授权

US5891765A Method of fabricating a gate array semiconductor integrated circuit device 失效
标题翻译：制造栅阵列半导体集成电路器件的方法
公开(公告)号：US5891765A
公开(公告)日：1999-04-06
申请号：US782944
申请日：1997-01-13
申请人： Kimio Ueda , Hiroyuki Morinaka , Koichiro Mashiko
发明人： Kimio Ueda , Hiroyuki Morinaka , Koichiro Mashiko
IPC分类号： H01L21/82 , H01L21/84 , H01L27/118 , H01L27/12 , H01L29/786 , H01L27/01 , H01L27/10 , H01L29/76
CPC分类号： H01L21/84 , H01L27/118 , H01L27/11807 , H01L27/1203
摘要： In order to improve a withstand voltage and implement a gate array SOI semiconductor integrated circuit device having a large gate width, a region consisting of end cells (49) is provided on each end of a region formed by repeatedly arranging basic cells (BC) consisting of both transistor regions (32, 33) in a first direction and while symmetrically arranging the same to be folded in a second direction. Both ends of a channel region of a PMOS transistor (42) are drawn out in the second direction to provide a P-type semiconductor layer just under a field shielding gate electrode (FG), and this semiconductor layer is drawn also in the first direction to be connected with a P-type semiconductor layer of the end cell (49). A first source potential is applied to a region (PBD) which is bonded with one of the P-type semiconductor layers. Also as to an NMOS transistor (41) which is adjacent through a field oxide film (FO), on the other hand, an N-type semiconductor layer is similarly provided so that this N-type semiconductor layer is also connected with that of the end cell (49). A second source potential is applied to a region (NBD).
摘要翻译：为了提高耐压并实现具有较大栅极宽度的栅阵列SOI半导体集成电路器件，在通过重复布置基本单元（BC）形成的区域的每个端部上设置由端单元（49）组成的区域，所述基本单元（BC）的两个晶体管区域（32,33）在第一方向上并且同时对称地布置在第二方向上被折叠。 PMOS晶体管（42）的沟道区域的两端在第二方向上被拉出以提供刚好在场屏蔽栅极（FG）下面的P型半导体层，并且该半导体层也沿第一方向与端电池（49）的P型半导体层连接。将第一源极电位施加到与一个P型半导体层接合的区域（PBD）。另一方面，与通过场氧化膜（FO）相邻的NMOS晶体管（41）也类似地设置N型半导体层，使得该N型半导体层也与端单元（49）。第二源电位被应用于区域（NBD）。

3. 发明申请

US20050108698A1 Assembler capable of reducing size of object code, and processor for executing the object code 审中-公开
标题翻译：能够减少对象代码大小的汇编器和用于执行目标代码的处理器
公开(公告)号：US20050108698A1
公开(公告)日：2005-05-19
申请号：US10841467
申请日：2004-05-10
申请人： Junko Kobara , Hiroyuki Kawai , Hiroyuki Morinaka , Yoshitsugu Inoue
发明人： Junko Kobara , Hiroyuki Kawai , Hiroyuki Morinaka , Yoshitsugu Inoue
IPC分类号： G06F9/45
CPC分类号： G06F8/4434
摘要： An instruction analyzing unit sequentially analyzes instructions of a program which is inputted to a program inputting unit. A NOP instruction analyzing part encodes continuous NOP instructions as one continuous NOP instruction. An instruction code outputting unit outputs the instruction encoded by the instruction analyzing unit as an object code. Therefore, the size of the object code can be reduced.
摘要翻译：指令分析单元顺序地分析输入到程序输入单元的程序的指令。 NOP指令分析部分将连续的NOP指令编码为一个连续的NOP指令。指令代码输出单元将由指令分析单元编码的指令作为目标代码输出。因此，可以减少目标代码的大小。

4. 发明授权

US6148318A Square root extraction circuit and floating-point square root extraction device 失效
标题翻译：平方根提取电路和浮点平方根提取装置
公开(公告)号：US6148318A
公开(公告)日：2000-11-14
申请号：US964888
申请日：1997-11-05
申请人： Hiroyuki Kawai , Robert Streitenberger , Yoshitsugu Inoue , Hiroyuki Morinaka
发明人： Hiroyuki Kawai , Robert Streitenberger , Yoshitsugu Inoue , Hiroyuki Morinaka
IPC分类号： G06F7/552 , G06F7/38
CPC分类号： G06F7/5525 , G06F7/483
摘要： A square root extraction circuit and a floating-point square root extraction device which simplify a circuit structure and improve an operation speed are provided. Portions for generating square root partial data (q3 to q8) include carry output prediction circuits (3 to 8), respectively. The carry output prediction circuit (i) (i equals any one of 3 to 8) receives condition flags (AHin, ALin), the most significant addition result (SUM), and square root partial data (q(i-1)) from the preceding square root partial data generating portion, and also receives a carry input (Cin) to output condition flags (AHout, ALout) for the next square root partial data generating portion, and square root partial data (q(i)). The condition flags (AHout, ALout) serve as the condition flags (AHin, ALin) for the carry output prediction circuit (i+1), respectively.
摘要翻译：提供了简化电路结构并提高操作速度的平方根提取电路和浮点平方根提取装置。用于产生平方根部分数据（q3至q8）的部分分别包括进位输出预测电路（3至8）。进位输出预测电路（i）（i等于3至8中的任何一个）从第一个输入预测电路（i）中接收条件标志（AHin，ALin），最高有效相加结果（SUM）和平方根部分数据（q（i-1）前一平方根部分数据生成部分，并且还接收用于下一个平方根部分数据生成部分的输出条件标志（AHout，ALout）的进位输入（Cin）和平方根部分数据（q（i））。条件标志（AHout，ALout）分别用作进位输出预测电路（i + 1）的条件标志（AHin，ALin）。

5. 发明授权

US06820107B1 Square root extraction circuit and floating-point square root extraction device 失效
标题翻译：平方根提取电路和浮点平方根提取装置
公开(公告)号：US06820107B1
公开(公告)日：2004-11-16
申请号：US09667783
申请日：2000-09-22
申请人： Hiroyuki Kawai , Robert Streitenberger , Yoshitsugu Inoue , Hiroyuki Morinaka
发明人： Hiroyuki Kawai , Robert Streitenberger , Yoshitsugu Inoue , Hiroyuki Morinaka
IPC分类号： G06F738
CPC分类号： G06F7/5525 , G06F7/483
摘要： A square root extraction circuit and a floating-point square root extraction device which simplify a circuit structure and improve an operation speed are provided. Portions for generating square root partial data (q3 to q8) include carry output prediction circuits (3 to 8), respectively. The carry output prediction circuit (i) (i equals any one of 3 to 8) receives condition flags (AHin, ALin), the most significant addition result (SUM), and square root partial data (q(i−1)) from the preceding square root partial data generating portion, and also receives a carry input (Cin) to output condition flags (AHout, ALout) for the next square root partial data generating portion, and square root partial data (q(i)). The condition flags (AHout, ALout) serve as the condition flags (AHin, ALin) for the carry output prediction circuit (i+1), respectively.
摘要翻译：提供了简化电路结构并提高操作速度的平方根提取电路和浮点平方根提取装置。用于产生平方根部分数据（q3至q8）的部分分别包括进位输出预测电路（3至8）。进位输出预测电路（i）（i等于3至8中的任何一个）从第一个输入预测电路（i）中接收条件标志（AHin，ALin），最高有效相加结果（SUM）和平方根部分数据（q（i-1）前一平方根部分数据生成部分，并且还接收用于下一个平方根部分数据生成部分的输出条件标志（AHout，ALout）的进位输入（Cin）和平方根部分数据（q（i））。条件标志（AHout，ALout）分别用作进位输出预测电路（i + 1）的条件标志（AHin，ALin）。

6. 发明授权

US6001518A Reversible heat-sensitive recording material with high color development and image stabilization capabilities 失效
标题翻译：可逆热敏记录材料，具有高显色和图像稳定功能
公开(公告)号：US6001518A
公开(公告)日：1999-12-14
申请号：US57575
申请日：1998-04-09
申请人： Haruhiko Ohsawa , Shin-ichi Koizumi , Hiroyuki Morinaka , Minoru Fujita
发明人： Haruhiko Ohsawa , Shin-ichi Koizumi , Hiroyuki Morinaka , Minoru Fujita
IPC分类号： B41M5/337 , B41M5/30 , B41M5/333 , G03C1/73 , G03C5/56
CPC分类号： B41M5/305 , B41M5/3335 , B41M5/3336 , Y10S430/163 , Y10S430/165
摘要： A reversible heat-sensitive recording medium has a substrate where a reversible heat-sensitive recording layer and a protective layer are successively formed on top of it. The reversible heat-sensitive recording layer is formed by a reversible heat-sensitive recording material including a leuco dye and a color developing/reducing agent. The color developing/reducing agent is a combination of two kinds of color developing/reducing agents, one with a high color developing ability and the other with high image preservation and stabilization capabilities. The two agents are combined at a ratio between 1:4 to 4:1. Thus a reversible heat-sensitive recording material with a fine color developing ability and high image preservation and stabilization capabilities can be obtained.
摘要翻译：可逆热敏记录介质具有在其顶部依次形成可逆热敏记录层和保护层的基板。可逆热敏记录层由包括无色染料和显色/还原剂的可逆热敏记录材料形成。彩色显影/还原剂是两种彩色显影/还原剂的组合，一种具有高显色能力，另一种具有高图像保存和稳定能力。两种试剂以1：4至4：1的比例组合。因此，可以获得具有良好显色能力和高图像保存和稳定能力的可逆热敏记录材料。

7. 发明授权

US5781062A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5781062A
公开(公告)日：1998-07-14
申请号：US582416
申请日：1996-01-03
申请人： Koichiro Mashiko , Kimio Ueda , Hiroaki Suzuki , Hiroyuki Morinaka
发明人： Koichiro Mashiko , Kimio Ueda , Hiroaki Suzuki , Hiroyuki Morinaka
IPC分类号： G11C5/14 , G11C11/407 , H03K19/00 , H03K19/0948 , G05F1/10
CPC分类号： H03K19/0016 , G11C5/14 , G11C5/147 , H01L2924/0002
摘要： A logic circuit (L.sub.i) is connected between a virtual power supply line (VDDV) connected to an actual power supply (VDD) through a PMOS transistor (Q1) and a virtual grounding line (GNDV) connected to an actual ground (GND) through an NMOS transistor (Q2). During an active period, the transistors (Q1, Q2) are constantly conducting, and the virtual power supply line (VDDV) and virtual grounding line (GNDV) are at the power supply potential (VDD) and ground potential (GND), respectively. During a standby period, the transistors (Q1, Q2) periodically repeat conduction/non-conduction to charge and discharge the virtual power supply line (VDDV) and virtual grounding line (GNDV), suppressing power consumption while preventing loss of information held by the logic circuit (L.sub.i).
摘要翻译：逻辑电路（Li）通过PMOS晶体管（Q1）连接到与实际电源（VDD）连接的虚拟电源线（VDDV）和连接到实际地线（GND）的虚拟接地线（GNDV）之间通过一个NMOS晶体管（Q2）。在激活期间，晶体管（Q1，Q2）恒定导通，虚拟电源线（VDDV）和虚拟接地线（GNDV）分别处于电源电位（VDD）和接地电位（GND）。在待机期间，晶体管（Q1，Q2）周期性地重复导通/非导通，对虚拟电源线（VDDV）和虚拟接地线（GNDV）进行充电和放电，从而抑制功耗，同时防止由逻辑电路（Li）。

8. 发明授权

US5747847A Semiconductor integrated circuit device, method for manufacturing the same, and logical circuit 失效
标题翻译：半导体集成电路器件及其制造方法以及逻辑电路
公开(公告)号：US5747847A
公开(公告)日：1998-05-05
申请号：US708269
申请日：1996-09-06
申请人： Hiroyuki Morinaka , Kimio Ueda , Koichiro Mashiko
发明人： Hiroyuki Morinaka , Kimio Ueda , Koichiro Mashiko
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/06 , H01L29/49 , H01L29/786 , H01L29/788
CPC分类号： H01L29/66651 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/0653 , H01L29/4908 , H01L29/66772 , H01L29/78612 , H01L29/78645 , H01L29/78648
摘要： A semiconductor integrated circuit device having a SOI structure which can prevent a deterioration in the breakdown voltage of a transistor without damaging integration, and a method for manufacturing the semiconductor integrated circuit device are obtained. An embedded oxide film is not formed over the whole face of a P type silicon layer but has an opening in a region which is placed below a gate electrode. The opening is filled in to form a penetration P layer. Accordingly, a SOI layer is electrically connected to the P type silicon layer through the penetration P layer. The plane position and shape of the gate electrode conform to those of the penetration P layer.
摘要翻译：具有能够防止晶体管的击穿电压劣化而不损害集成度的SOI结构的半导体集成电路器件，以及半导体集成电路器件的制造方法。在P型硅层的整个表面上不形成嵌入的氧化物膜，但在位于栅电极下方的区域中具有开口。填充开口以形成穿透P层。因此，SOI层通过穿透P层与P型硅层电连接。栅电极的平面位置和形状与穿透层P的平面位置和形状一致。

9. 发明授权

US5633524A Gate array semiconductor integrated circuit device 失效
标题翻译：门阵列半导体集成电路器件
公开(公告)号：US5633524A
公开(公告)日：1997-05-27
申请号：US580609
申请日：1995-12-29
申请人： Kimio Ueda , Hiroyuki Morinaka , Koichiro Mashiko
发明人： Kimio Ueda , Hiroyuki Morinaka , Koichiro Mashiko
IPC分类号： H01L21/82 , H01L21/84 , H01L27/118 , H01L27/12 , H01L29/786 , H01L27/10 , H01L27/01 , H01L29/76
CPC分类号： H01L21/84 , H01L27/118 , H01L27/11807 , H01L27/1203
摘要： In order to improve a withstand voltage and implement a gate array SOI semiconductor integrated circuit device having a large gate width, a region consisting of end cells (49) is provided on each end of a region formed by repeatedly arranging basic cells (BC) consisting of both transistor regions (32, 33) in a first direction and while symmetrically arranging the same to be folded in a second direction. Both ends of a channel region of a PMOS transistor (42) are drawn out in the second direction to provide a P-type semiconductor layer just under a field shielding gate electrode (FG), and this semiconductor layer is drawn also in the first direction to be connected with a P-type semiconductor layer of the end cell (49). A first source potential is applied to a region (PBD) which is bonded with one of the P-type semiconductor layers. Also as to an NMOS transistor (41) which is adjacent through a field oxide film (FO), on the other hand, an N-type semiconductor layer is similarly provided so that this N-type semiconductor layer is also connected with that of the end cell (49). A second source potential is applied to a region (NBD).
摘要翻译：为了提高耐压并实现具有较大栅极宽度的栅阵列SOI半导体集成电路器件，在通过重复布置基本单元（BC）形成的区域的每个端部上设置由端单元（49）组成的区域，所述基本单元（BC）的两个晶体管区域（32,33）在第一方向上并且同时对称地布置在第二方向上被折叠。 PMOS晶体管（42）的沟道区域的两端在第二方向上被拉出以提供刚好在场屏蔽栅极（FG）下面的P型半导体层，并且该半导体层也沿第一方向与端电池（49）的P型半导体层连接。将第一源极电位施加到与一个P型半导体层接合的区域（PBD）。另一方面，与通过场氧化膜（FO）相邻的NMOS晶体管（41）也类似地设置N型半导体层，使得该N型半导体层也与端单元（49）。第二源电位被应用于区域（NBD）。

10. 发明授权

US6005422A Semiconductor integrated circuit and consumed power reducing method 失效
标题翻译：半导体集成电路和消耗功率降低方法
公开(公告)号：US6005422A
公开(公告)日：1999-12-21
申请号：US773313
申请日：1996-12-24
申请人： Hiroyuki Morinaka , Hiroshi Makino , Kimio Ueda , Koichiro Mashiko
发明人： Hiroyuki Morinaka , Hiroshi Makino , Kimio Ueda , Koichiro Mashiko
IPC分类号： G06F13/38 , G06F1/32 , G06F5/00 , H03K19/00 , H04L25/02 , H03K1/04 , G06F1/08
CPC分类号： G06F7/523 , G06F1/32 , G06F5/00 , H03K19/0008
摘要： A semiconductor integrated circuit and a method for reducing the consumed power are provided. A comparator outputs bits having the same level, which correspond to each other, of a last input stored in a register and a current input that acts as an input signal. A zero counter counts the number of the bits having the same level output from the comparator. If the number of the bits having the same level is smaller than a predetermined number, the current input is not similar to the last input. Consequently, an instruction is given to a flip-flop to invert the current input. The inverted current input becomes similar to the last input. Thus, the consumed power of a logic can be reduced.
摘要翻译：提供半导体集成电路和降低功耗的方法。比较器输出存储在寄存器中的最后一个输入和作为输入信号的当前输入的具有相同电平的位。零计数器对比较器具有相同电平输出的位数进行计数。如果具有相同电平的位的数量小于预定数量，则当前输入与最后一个输入不相似。因此，给触发器指示反转当前输入。反相电流输入变得与最后一个输入相似。因此，可以减少逻辑的消耗功率。

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