专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060117219A1 Control device 审中-公开
标题翻译：控制装置
公开(公告)号：US20060117219A1
公开(公告)日：2006-06-01
申请号：US11094693
申请日：2005-03-31
申请人： Hirotoshi Inoue , Makoto Takamatsu , Michisada Sugimoto , Terumasa Haneda , Toshiyuki Yoshida , Yuichi Ogawa
发明人： Hirotoshi Inoue , Makoto Takamatsu , Michisada Sugimoto , Terumasa Haneda , Toshiyuki Yoshida , Yuichi Ogawa
IPC分类号： G06F11/00
CPC分类号： G06F11/1016
摘要： Arbitrary data is read out from a main storage device, based on a permanent fault detection address that is used to detect a permanent fault on an address line. A bit error in the permanent fault detection address is detected and corrected, based on an error correcting code included in the arbitrary data read out. A permanent fault on the address line is determined, based on results of the error detection/correction.
摘要翻译：根据用于检测地址线上的永久故障的永久故障检测地址，从主存储装置读出任意数据。基于读出的任意数据中包含的纠错码，检测并校正永久故障检测地址中的位错误。基于错误检测/校正的结果确定地址线上的永久性故障。

2. 发明授权

US07774513B2 DMA circuit and computer system 有权
标题翻译： DMA电路和计算机系统
公开(公告)号：US07774513B2
公开(公告)日：2010-08-10
申请号：US11220617
申请日：2005-09-08
申请人： Terumasa Haneda , Yuichi Ogawa , Toshiyuki Yoshida , Yuji Hanaoka
发明人： Terumasa Haneda , Yuichi Ogawa , Toshiyuki Yoshida , Yuji Hanaoka
IPC分类号： G06F13/28 , G06F15/167
CPC分类号： G06F13/28
摘要： A DMA circuit operates a plurality of DMA channels in parallel, enabling reduction of the circuit scale and fewer development processes. A channel manager circuit reads in sequence the control information for each DMA channel from control memory, performs analysis, and according to the divided DMA control sequence, performs state processing (DMA control). Further, the channel manager circuit updates the control information, writes back the control information to the control memory, and executes time-division control of the plurality of DMA channels. Hence the circuit scale can be reduced, contributing to decreased costs, and the number of development processes can be reduced.
摘要翻译： DMA电路并行操作多个DMA通道，能够减少电路规模和减少开发过程。频道管理电路依次读取来自控制存储器的每个DMA通道的控制信息，执行分析，并根据划分的DMA控制序列执行状态处理（DMA控制）。此外，信道管理电路更新控制信息，将控制信息写回控制存储器，并执行多个DMA信道的时分控制。因此，可以减小电路规模，有助于降低成本，并且可以减少开发过程的数量。

3. 发明申请

US20060159115A1 Method of controlling information processing system, information processing system, direct memory access control device and program 有权
标题翻译：控制信息处理系统，信息处理系统，直接存储器访问控制装置和程序的方法
公开(公告)号：US20060159115A1
公开(公告)日：2006-07-20
申请号：US11237767
申请日：2005-09-29
申请人： Terumasa Haneda , Yuichi Ogawa , Yuuji Hanaoka , Toshiyuki Yoshida , Hidenori Takahashi
发明人： Terumasa Haneda , Yuichi Ogawa , Yuuji Hanaoka , Toshiyuki Yoshida , Hidenori Takahashi
IPC分类号： H04L12/56 , H04L12/28 , H04J3/22 , H04J3/16
CPC分类号： G06F11/0793 , G06F11/0745 , H04L49/3009 , H04L49/602
摘要： In a method of controlling an information processing system in which an information processing device is connected to each of a plurality of input/output ports provided in a routing device and having a first property or a second property, for conducting data transmission among the information processing devices via the routing device, a step of causing all of the information processing devices to halt data transmission, a step of resetting properties and identification information of the input/output ports with the second properties other than the input/output port with the first property which cannot be used, in the routing device, and a step of causing the information processing devices to restart the data transmission after the reset of the identification information are executed.
摘要翻译：在控制信息处理系统的方法中，其中信息处理设备连接到设置在路由设备中并具有第一属性或第二属性的多个输入/输出端口中的每一个，用于在信息处理之间进行数据传输通过路由设备的设备，使所有信息处理设备停止数据传输的步骤，具有除了具有第一属性的输入/输出端口之外的第二特性的输入/输出端口的属性重置和识别信息的步骤在路由装置中不能使用，并且在执行了识别信息的复位之后使信息处理装置重启数据传输的步骤。

4. 发明申请

US20060190772A1 File control system and file control device 有权
标题翻译：文件控制系统和文件控制装置
公开(公告)号：US20060190772A1
公开(公告)日：2006-08-24
申请号：US11237655
申请日：2005-09-29
申请人： Yuuji Hanaoka , Toshiyuki Yoshida , Yuichi Ogawa , Terumasa Haneda , Kazunori Masuyama
发明人： Yuuji Hanaoka , Toshiyuki Yoshida , Yuichi Ogawa , Terumasa Haneda , Kazunori Masuyama
IPC分类号： G06F11/00
CPC分类号： H04L1/0082
摘要： A file control system of the present invention is a file control system performing DMA transfer and comprising a plurality of file control devices, each of which is provided between a host computer and an external storage device, a first file control device among the plurality of file control devices, checks the consistency between the data read from a memory and the first error detection code given in advance to the data, changes the error detection code added to the read data from the first error detection code to a second error detection code, when the inconsistency is detected by the check, changes at least a part of the data comprising the second error detection code and the data associated with the second error detection code, and executes DMA-transfer of the data which is changed or is not changed to a second file control device of the transfer destination.
摘要翻译：本发明的文件控制系统是执行DMA传输的文件控制系统，包括多个文件控制装置，每个文件控制装置设置在主计算机和外部存储装置之间，多个文件中的第一文件控制装置控制装置检查从存储器读取的数据与预先给出的数据之间的第一错误检测码的一致性，将从第一错误检测码添加到读取数据的错误检测码改变为第二错误检测码，当通过检查检测到不一致，改变包括第二错误检测码的数据的至少一部分和与第二错误检测码相关联的数据，并且执行被改变或不被改变的数据的DMA传送传送目的地的第二文件控制装置。

5. 发明授权

US08032793B2 Method of controlling information processing system, information processing system, direct memory access control device and program 有权
标题翻译：控制信息处理系统，信息处理系统，直接存储器访问控制装置和程序的方法
公开(公告)号：US08032793B2
公开(公告)日：2011-10-04
申请号：US11237767
申请日：2005-09-29
申请人： Terumasa Haneda , Yuichi Ogawa , Yuuji Hanaoka , Toshiyuki Yoshida , Hidenori Takahashi
发明人： Terumasa Haneda , Yuichi Ogawa , Yuuji Hanaoka , Toshiyuki Yoshida , Hidenori Takahashi
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0745 , H04L49/3009 , H04L49/602
摘要： In a method of controlling an information processing system in which an information processing device is connected to each of a plurality of input/output ports provided in a routing device and having a first property or a second property, for conducting data transmission among the information processing devices via the routing device, a step of causing all of the information processing devices to halt data transmission, a step of resetting properties and identification information of the input/output ports with the second properties other than the input/output port with the first property which cannot be used, in the routing device, and a step of causing the information processing devices to restart the data transmission after the reset of the identification information are executed.
摘要翻译：在控制信息处理系统的方法中，其中信息处理设备连接到设置在路由设备中并具有第一属性或第二属性的多个输入/输出端口中的每一个，用于在信息处理之间进行数据传输通过路由设备的设备，使所有信息处理设备停止数据传输的步骤，具有除了具有第一属性的输入/输出端口之外的第二特性的输入/输出端口的属性重置和识别信息的步骤在路由装置中不能使用，并且在执行了识别信息的复位之后使信息处理装置重启数据传输的步骤。

6. 发明授权

US07640374B2 Data transfer apparatus by direct memory access controller 有权
标题翻译：数据传输设备由直接存储器访问控制器
公开(公告)号：US07640374B2
公开(公告)日：2009-12-29
申请号：US11196469
申请日：2005-08-04
申请人： Toshihiro Tomozaki , Toshiyuki Yoshida , Yuichi Ogawa , Terumasa Haneda , Yuuji Hanaoka
发明人： Toshihiro Tomozaki , Toshiyuki Yoshida , Yuichi Ogawa , Terumasa Haneda , Yuuji Hanaoka
IPC分类号： G06F3/00 , G06F12/00
CPC分类号： G06F13/28
摘要： A DMA apparatus which reads data corresponding to a descriptor from memory, and a dividing unit in a descriptor management device divides one descriptor into a plurality of sub-descriptors. A plurality of DMA controllers produce a plurality of reading requests for reading data corresponding to the plurality of sub-descriptors from the memory. A memory controller reads the corresponding data from the memory according to the plurality of reading requests.
摘要翻译：从存储器读取对应于描述符的数据的DMA装置以及描述符管理装置中的分割单元将一个描述符分成多个子描述符。多个DMA控制器产生用于从存储器读取对应于多个子描述符的数据的多个读取请求。存储器控制器根据多个读取请求从存储器读取相应的数据。

7. 发明授权

US07624324B2 File control system and file control device 有权
标题翻译：文件控制系统和文件控制装置
公开(公告)号：US07624324B2
公开(公告)日：2009-11-24
申请号：US11237655
申请日：2005-09-29
申请人： Yuuji Hanaoka , Toshiyuki Yoshida , Yuichi Ogawa , Terumasa Haneda , Kazunori Masuyama
发明人： Yuuji Hanaoka , Toshiyuki Yoshida , Yuichi Ogawa , Terumasa Haneda , Kazunori Masuyama
IPC分类号： G06F11/00
CPC分类号： H04L1/0082
摘要： A file control system performing DMA (direct memory access) transfer is provided. The file control system includes file control devices, and each of the file control devices is provided between a host computer and an external storage device. A first file control device among the file control devices checks for errors in the data read from a memory, changes the error detection code added to the read data from a first error detection code to a second error detection code, changes at least a part of the data when an error is detected, and executes DMA-transfer of the data, which is changed or is not changed, to a second file control device of the transfer destination.
摘要翻译：提供执行DMA（直接存储器访问）传送的文件控制系统。文件控制系统包括文件控制装置，并且每个文件控制装置设置在主计算机和外部存储装置之间。文件控制装置中的第一文件控制装置检查从存储器读取的数据中的错误，将从第一错误检测码添加到读取数据的错误检测码改变为第二错误检测码，改变至少一部分当检测到错误时的数据，并且将改变或不改变的数据的DMA传送执行到传送目的地的第二文件控制装置。

8. 发明申请

US20060161694A1 DMA apparatus 有权
标题翻译： DMA设备
公开(公告)号：US20060161694A1
公开(公告)日：2006-07-20
申请号：US11196469
申请日：2005-08-04
申请人： Toshihiro Tomozaki , Toshiyuki Yoshida , Yuichi Ogawa , Terumasa Haneda , Yuuji Hanaoka
发明人： Toshihiro Tomozaki , Toshiyuki Yoshida , Yuichi Ogawa , Terumasa Haneda , Yuuji Hanaoka
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA apparatus which reads data corresponding to a descriptor from memory, and a dividing unit in a descriptor management device divides one descriptor into a plurality of sub-descriptors. A plurality of DMA controllers produce a plurality of reading requests for reading data corresponding to the plurality of sub-descriptors from the memory. A memory controller reads the corresponding data from the memory according to the plurality of reading requests.
摘要翻译：从存储器读取对应于描述符的数据的DMA装置以及描述符管理装置中的分割单元将一个描述符分成多个子描述符。多个DMA控制器产生用于从存储器读取对应于多个子描述符的数据的多个读取请求。存储器控制器根据多个读取请求从存储器读取相应的数据。

9. 发明申请

US20060218313A1 DMA circuit and computer system 有权
标题翻译： DMA电路和计算机系统
公开(公告)号：US20060218313A1
公开(公告)日：2006-09-28
申请号：US11220617
申请日：2005-09-08
申请人： Terumasa Haneda , Yuichi Ogawa , Toshiyuki Yoshida , Yuji Hanaoka
发明人： Terumasa Haneda , Yuichi Ogawa , Toshiyuki Yoshida , Yuji Hanaoka
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA circuit operates a plurality of DMA channels in parallel, enabling reduction of the circuit scale and fewer development processes. A channel manager circuit reads in sequence the control information for each DMA channel from control memory, performs analysis, and according to the divided DMA control sequence, performs state processing (DMA control). Further, the channel manager circuit updates the control information, writes back the control information to the control memory, and executes time-division control of the plurality of DMA channels. Hence the circuit scale can be reduced, contributing to decreased costs, and the number of development processes can be reduced.
摘要翻译： DMA电路并行操作多个DMA通道，能够减少电路规模和减少开发过程。频道管理电路顺序读取来自控制存储器的每个DMA通道的控制信息，执行分析，并根据划分的DMA控制序列执行状态处理（DMA控制）。此外，信道管理电路更新控制信息，将控制信息写回控制存储器，并执行多个DMA信道的时分控制。因此，可以减小电路规模，有助于降低成本，并且可以减少开发过程的数量。

10. 发明授权

US06957273B2 Packet transmitting/receiving method and apparatus for computer system 失效
标题翻译：计算机系统的分组发送/接收方法和装置
公开(公告)号：US06957273B2
公开(公告)日：2005-10-18
申请号：US09725672
申请日：2000-11-30
申请人： Terumasa Haneda , Hiroshi Matsushita , Makoto Takamatsu , Yuji Hanaoka
发明人： Terumasa Haneda , Hiroshi Matsushita , Makoto Takamatsu , Yuji Hanaoka
IPC分类号： G06F13/40 , G06F15/173 , G06F15/16 , H04J3/16 , H04J3/22
CPC分类号： G06F13/4045
摘要： Priorities are set in order of an internal register access packet, a response system packet, and a command system packet which are transmitted/received by a packet transmitting/receiving unit. In a transfer waiting state of the command system packet of the low priority to a certain transmission destination, in the case where the response system packet or internal register access packet of the high priority to another transmission destination is received from an external module, the packet transmitting/receiving unit withdraws the transfer waiting state and transmits the packet of the high priority.
摘要翻译：优先级按照由分组发送/接收单元发送/接收的内部寄存器访问分组，响应系统分组和命令系统分组的顺序设置。在某个传输目的地的低优先级的命令系统分组的转移等待状态中，在从外部模块接收到对另一发送目的地的高优先级的响应系统分组或内部寄存器访问分组的情况下，发送/接收单元撤回传送等待状态并发送高优先级的数据包。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式