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1. 发明授权

US5768195A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5768195A
公开(公告)日：1998-06-16
申请号：US857586
申请日：1997-05-16
申请人： Hiroshi Nakamura , Masaki Momodomi , Yoshihisa Iwata , Ryouhei Kirisawa
发明人： Hiroshi Nakamura , Masaki Momodomi , Yoshihisa Iwata , Ryouhei Kirisawa
IPC分类号： H01L21/66 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/30 , G11C17/00 , G11C29/00 , G11C29/04 , G11C29/34 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/105 , G11C16/30
摘要： A semiconductor memory device according to he present invention comprises a first conductivity-type semiconductor substrate in which a second conductivity-type well is formed, a memory cell array composed of a plurality of memory cells arranged in a matrix in the second conductivity-type well, and a substrate voltage control circuit selectively outputting an output voltage to the substrate according to an external input signal.
摘要翻译：根据本发明的半导体存储器件包括形成有第二导电型阱的第一导电型半导体衬底，由在第二导电型阱中以矩阵排列的多个存储单元组成的存储单元阵列以及基板电压控制电路，根据外部输入信号选择性地将输出电压输出到基板。

2. 发明授权

US5528547A Electrically erasable programmable read-only memory with electric field decreasing controller 失效
公开(公告)号：US5528547A
公开(公告)日：1996-06-18
申请号：US332391
申请日：1994-10-31
申请人： Seiichi Aritome , Riichiro Shirota , Ryouhei Kirisawa , Yoshihisa Iwata , Masaki Momodomi
发明人： Seiichi Aritome , Riichiro Shirota , Ryouhei Kirisawa , Yoshihisa Iwata , Masaki Momodomi
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00 , G11C11/34
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/0483
摘要： A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.

3. 发明授权

US5293337A Electrically erasable programmable read-only memory with electric field decreasing controller 失效
标题翻译：电可擦除可编程只读存储器，具有电场降低控制器
公开(公告)号：US5293337A
公开(公告)日：1994-03-08
申请号：US683733
申请日：1991-04-11
申请人： Seiichi Aritome , Riichiro Shirota , Ryouhei Kirisawa , Yoshihisa Iwata , Masaki Momodomi
发明人： Seiichi Aritome , Riichiro Shirota , Ryouhei Kirisawa , Yoshihisa Iwata , Masaki Momodomi
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/0483
摘要： A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.
摘要翻译： NAND单元型EEPROM具有位线，其各自与包括四个存储单元晶体管的串联阵列的NAND单元单元相关联。每个晶体管是具有控制栅极和用于数据存储的浮动栅极的MOSFET。存储单元晶体管分别在其控制栅极处连接到字线。 NAND单元单元的一端通过第一选择晶体管连接到相应的位线; 其另一端经由第二选择晶体管连接到源极电压。存储单元晶体管和选择晶体管布置在形成在衬底中的阱区中。在擦除模式中，位线电压，衬底电压和阱电压保持在高电压，而字线为零伏。选择晶体管的栅极电位被保持在高电压，由此这些选择晶体管的内部电场被削弱以改善其绝缘击穿特性。

4. 发明授权

US5050125A Electrically erasable programmable read-only memory with NAND cellstructure 失效
标题翻译：具有NAND单元结构的电可擦除可编程只读存储器
公开(公告)号：US5050125A
公开(公告)日：1991-09-17
申请号：US272404
申请日：1988-11-17
申请人： Masaki Momodomi , Koichi Toita , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba , Tetsuo Endo , Riichiro Shirota , Ryouhei Kirisawa
发明人： Masaki Momodomi , Koichi Toita , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba , Tetsuo Endo , Riichiro Shirota , Ryouhei Kirisawa
IPC分类号： G11C16/04 , G11C16/08 , G11C16/30 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/08 , G11C16/30
摘要： An erasable programmable read-only memory with a NAND cell structure including NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected is series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an "L" Level voltage (approximately O V) to a word line connected to the selected cell, applying an "H" level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the "H" and "L" level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic "0" data, the intermediate voltage is applied also to the specific bit line.
摘要翻译：具有包括NAND单元块的NAND单元结构的可擦除可编程只读存储器，每个NAND单元块具有连接到相应位线的选择晶体管和连接的存储单元晶体管。字线连接到单元晶体管的控制栅极。在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通以将单元块连接到对应的位线。提供控制电路，用于向连接到所选择的单元的字线施加“L”电平电压（大约为0V），对位于所选择的单元之间的字线或字线施加“H”电平电压（大约20V）字线和连接单元块和与其相关联的特定位线的接触节点，施加与要写入特定位线的数据相对应的电压，以及将“H”和“L”电平电压之间的中间电压施加到未选择的位线，从而通过隧道将数据写入所选择的单元。如果数据是逻辑“0”数据，则中间电压也被施加到特定位线。

5. 发明授权

US5402373A Electrically erasable programmable read-only memory with electric field decreasing controller 失效
标题翻译：电可擦除可编程只读存储器，具有电场降低控制器
公开(公告)号：US5402373A
公开(公告)日：1995-03-28
申请号：US201036
申请日：1994-02-24
申请人： Seiichi Aritome , Riichiro Shirota , Ryouhei Kirisawa , Yoshihisa Iwata , Masaki Momodomi
发明人： Seiichi Aritome , Riichiro Shirota , Ryouhei Kirisawa , Yoshihisa Iwata , Masaki Momodomi
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/0483
摘要： A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.
摘要翻译： NAND单元型EEPROM具有位线，其各自与包括四个存储单元晶体管的串联阵列的NAND单元单元相关联。每个晶体管是具有控制栅极和用于数据存储的浮动栅极的MOSFET。存储单元晶体管分别在其控制栅极处连接到字线。 NAND单元单元的一端通过第一选择晶体管连接到相应的位线; 其另一端经由第二选择晶体管连接到源极电压。存储单元晶体管和选择晶体管布置在形成在衬底中的阱区中。在擦除模式中，位线电压，衬底电压和阱电压保持在高电压，而字线为零伏。选择晶体管的栅极电位被保持在高电压，由此这些选择晶体管的内部电场被削弱以改善其绝缘击穿特性。

6. 发明授权

US5508957A Non-volatile semiconductor memory with NAND cell structure and switching transistors with different channel lengths to reduce punch-through 失效
标题翻译：具有NAND单元结构的非易失性半导体存储器和具有不同通道长度的开关晶体管以减少穿通
公开(公告)号：US5508957A
公开(公告)日：1996-04-16
申请号：US312072
申请日：1994-09-26
申请人： Masaki Momodomi , Fujio Masuoka , Yasuo Itoh , Hiroshi Iwahashi , Yoshihisa Iwata , Masahiko Chiba , Satoshi Inoue , Riichiro Shirota , Ryozo Nakayama , Kazunori Ohuchi , Shigeyoshi Watanabe , Ryouhei Kirisawa
发明人： Masaki Momodomi , Fujio Masuoka , Yasuo Itoh , Hiroshi Iwahashi , Yoshihisa Iwata , Masahiko Chiba , Satoshi Inoue , Riichiro Shirota , Ryozo Nakayama , Kazunori Ohuchi , Shigeyoshi Watanabe , Ryouhei Kirisawa
IPC分类号： G11C16/04 , G11C16/10 , G11C16/16 , G11C16/30 , H01L27/115 , G11C16/06 , H01L29/788
CPC分类号： G11C16/30 , G11C16/0483 , G11C16/10 , G11C16/16 , H01L27/115
摘要： An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.) in the selected cell, by applying an "H" level voltage to the bit line, applying an "L" level voltage to a word line connected to the selected cell, applying the "H" level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the "L" level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.
摘要翻译：具有NAND单元结构的可擦除可编程只读存储器包括NAND单元块，每个单元块具有连接到对应位线的选择晶体管和存储单元晶体管的串联阵列，以及连接在串联阵列存储单元之间的开关晶体管晶体管和地。每个单元晶体管具有浮置栅极和控制栅极。字线连接到单元晶体管的控制栅极。在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通，使得该单元块连接到对应的位线。在这种情况下，解码器电路通过向位线施加“H”电平电压，将所需数据（例如逻辑“1”）存储在所选择的单元中，对连接的字线施加“L”电平电压将“H”电平施加到位于所选择的单元和位线之间的存储单元或单元，并将“L”电平施加到位于所选单元和地之间的存储单元或单元。用于存储单元晶体管的相应串联阵列的选择晶体管和开关晶体管具有不同的沟道长度以减少穿通。

7. 发明授权

US5440509A Electrically erasable programmable read-only memory with NAND cell structure and intermediate level voltages initially applied to bit lines 失效
标题翻译：电可擦除可编程只读存储器，NAND单元结构和中间电平电压最初应用于位线
公开(公告)号：US5440509A
公开(公告)日：1995-08-08
申请号：US22392
申请日：1993-02-24
申请人： Masaki Momodomi , Koichi Toita , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba , Tetsuo Endo , Riichiro Shirota , Ryouhei Kirisawa
发明人： Masaki Momodomi , Koichi Toita , Yasuo Itoh , Yoshihisa Iwata , Fujio Masuoka , Masahiko Chiba , Tetsuo Endo , Riichiro Shirota , Ryouhei Kirisawa
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/30 , H01L27/115
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/30 , H01L27/115
摘要： An erasable programmable read-only memory (EPROM) with a NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected in series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an "L" level voltage (approximately 0 V) to a word line connected to the selected cell, applying an "H" level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the "H" and "L" level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic "0" data, the intermediate voltage is applied also to the specific bit line.
摘要翻译：具有NAND单元结构的可擦除可编程只读存储器（EPROM）包括NAND单元块，每个单元块具有连接到相应位线的选择晶体管和串联连接的存储单元晶体管。字线连接到单元晶体管的控制栅极。在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通以将单元块连接到对应的位线。提供一种控制电路，用于向连接到所选择的单元的字线施加“L”电平电压（大约0V），对位于第一个单元之间的字线或字线施加“H”电平电压（大约20V）选择字线和连接单元块和与其相关联的特定位线的接触节点，施加与要写入到特定位线的数据相对应的电压，以及在“H”和“L”电平电压之间施加中间电压到未选择的位线，从而通过隧道将数据写入所选择的单元。如果数据是逻辑“0”数据，则中间电压也被施加到特定位线。

8. 发明授权

US5179427A Non-volatile semiconductor memory device with voltage stabilizing electrode 失效
标题翻译：具有稳压电极的非易失性半导体存储器件
公开(公告)号：US5179427A
公开(公告)日：1993-01-12
申请号：US869123
申请日：1992-04-15
申请人： Ryozo Nakayama , Riichiro Shirota , Yasuo Itoh , Ryouhei Kirisawa , Hideko Odaira , Masaki Momodomi , Yoshihisa Iwata , Tomoharu Tanaka , Seiichi Aritome , Tetsuo Endoh , Fujio Masuoka
发明人： Ryozo Nakayama , Riichiro Shirota , Yasuo Itoh , Ryouhei Kirisawa , Hideko Odaira , Masaki Momodomi , Yoshihisa Iwata , Tomoharu Tanaka , Seiichi Aritome , Tetsuo Endoh , Fujio Masuoka
IPC分类号： G11C16/04 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0483
摘要： A NAND cell type EEPROM has parallel data transmission lines formed above a substrate, and a memory cell section including a plurality of NAND type cell units containing a NAND type cell unit that is associated with a certain bit line of the bit lines. This NAND type cell unit has a series-circuit of a preselected number of data storage transistors with control gates, and a selection transistor. A substrate voltage-stabilizing layer is insulatively provided above the substrate and positioned in the field area in adjacent to the certain bit line. The conductive layer is connected to the substrate by a contact portion so that the substrate voltage can be constantly set to a preselected voltage potential of a fixed value during the NAND type cell unit is being subjected to the write and erase modes.
摘要翻译： NAND单元型EEPROM具有形成在衬底上的并行数据传输线，以及存储单元部分，其包括与位线的某个位线相关联的NAND型单元单元的多个NAND型单元单元。该NAND型单元单元具有预选数量的具有控制栅极的数据存储晶体管和选择晶体管的串联电路。衬底电压稳定层被绝缘地设置在衬底之上并且位于与某一位线相邻的场区中。导电层通过接触部分连接到基板，使得在对NAND型单元单元进行写入和擦除模式期间，基板电压可以恒定地设定为固定值的预选电压电位。

9. 发明申请

US20060114729A1 Non-volatile semiconductor memory device and memory system using the same 失效
公开(公告)号：US20060114729A1
公开(公告)日：2006-06-01
申请号：US11243985
申请日：2005-10-06
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G11C7/10 , G11C11/34
CPC分类号： G11C29/785 , G06F11/1008 , G06F11/1068 , G06F2201/81 , G06F2212/2022 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/34 , G11C29/52
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

10. 发明授权

US06967892B2 Non-volatile semiconductor memory device and memory system using the same 失效
标题翻译：非易失性半导体存储器件和使用其的存储器系统
公开(公告)号：US06967892B2
公开(公告)日：2005-11-22
申请号：US10804094
申请日：2004-03-19
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G06F11/10 , G11C16/10 , G11C16/12 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/52 , G11C16/04
CPC分类号： G11C29/785 , G06F11/1008 , G06F11/1068 , G06F2201/81 , G06F2212/2022 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/34 , G11C29/52
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写过程中，通过改变数据寄存器中的数据，对数据一次正确写入的存储单元不会影响重写操作。

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