专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4888774A Error detection system 失效
标题翻译：错误检测系统
公开(公告)号：US4888774A
公开(公告)日：1989-12-19
申请号：US132993
申请日：1987-12-15
申请人： Hiroshi Kosuge , Yoshio Kiriu
发明人： Hiroshi Kosuge , Yoshio Kiriu
IPC分类号： G06F11/10 , G06F12/16 , H03M13/19
CPC分类号： G06F11/1028 , H03M13/19
摘要： An error detecting apparatus in which an error within an arbitrary and continuous (b-1) bit block is detected using a SEC-DED-SbED code. The (b-1) bit block is any continuous (b-1) bit block within an information consisting of several b bit blocks. The data are encoded by using a power of a matrix C, defined as: ##EQU1## and a matrix B. Matrix B is comprised by arbitrarily replacing the rows and columns of the power of C matrix with row vectors from a set of (b+1) vectors: ##EQU2## The partial matrices obtained from matrices B and C are used to construct a parity matrix. Syndromes are computed from the information and the party matrix to detect errors.
摘要翻译：一种错误检测装置，其中使用SEC-DED-SbED代码检测任意和连续（b-1）比特块内的错误。（b-1）位块是由几个b位块组成的信息内的任何连续（b-1）位块。通过使用定义为：和矩阵B的矩阵C的幂来对数据进行编码。矩阵B包括通过以下方式任意替换C矩阵的幂的行和列：（b +1）向量：从矩阵B和C获得的部分矩阵用于构造奇偶校验矩阵。根据信息和方矩阵计算综合征，以检测错误。

2. 发明授权

US4692922A Method for correcting and detecting errors 失效
标题翻译：纠正和检测错误的方法
公开(公告)号：US4692922A
公开(公告)日：1987-09-08
申请号：US807682
申请日：1985-12-11
申请人： Yoshio Kiriu , Shigeru Kaneko , Hiroshi Kosuge
发明人： Yoshio Kiriu , Shigeru Kaneko , Hiroshi Kosuge
IPC分类号： H03M13/00 , G06F11/10 , G06F12/16 , H03M13/19
CPC分类号： G06F11/1028 , H03M13/19
摘要： A method for correcting and detecting errors using the SEC-DED-SbED code is provided, wherein the information consisting of several blocks of b bits is encoded based on the parity matrix including any of b.times.b matrix X q (q=1 to b) in which each row of b.times.b matrix ##EQU1## is cyclically displaced along the column direction by a desired number (q) of bits in each partial matrix corresponding to the above block.
摘要翻译：提供了一种使用SEC-DED-SbED代码校正和检测错误的方法，其中基于包括bxb矩阵X q（q = 1至b）中任一个的奇偶校验矩阵来编码由几个b位组成的信息，其中每行bxb矩阵沿着列方向循环移位相应于上述块的每个部分矩阵中所需的位数（q）。

3. 发明授权

US5563894A Error detecting and correcting method and system 失效
标题翻译：错误检测和纠正方法和系统
公开(公告)号：US5563894A
公开(公告)日：1996-10-08
申请号：US986478
申请日：1992-12-07
申请人： Eiji Fujiwara , Hiroshi Kosuge , Yoshio Kiriu
发明人： Eiji Fujiwara , Hiroshi Kosuge , Yoshio Kiriu
IPC分类号： G06F11/10 , G06F12/16 , H03M13/15 , H03M13/00
CPC分类号： G06F11/1028 , H03M13/151
摘要： An error detecting and correcting apparatus includes a unit for receiving an encoded word including a plurality of b-bit bytes (b is an integer not less than two) and generating syndrome from the encoded word according to a first parity check matrix H.sub.1, and a unit for correcting errors in the received encoded word based on the syndrome.
摘要翻译：误差检测和校正装置包括用于接收包括多个b位字节（b为不小于2的整数）的编码字并根据第一奇偶校验矩阵H1从编码字产生校正子的单元，以及用于基于所述综合征校正所接收的编码字中的错误的单元。

4. 发明授权

US5450423A Data error correcting/detecting system and apparatus compatible with different data bit memory packages 失效
标题翻译：与不同数据位存储器封装兼容的数据纠错/检测系统和设备
公开(公告)号：US5450423A
公开(公告)日：1995-09-12
申请号：US852954
申请日：1992-03-17
申请人： Kazuya Iwasaki , Hiroshi Kosuge , Yoshio Kiriu , Ryoichi Kurihara
发明人： Kazuya Iwasaki , Hiroshi Kosuge , Yoshio Kiriu , Ryoichi Kurihara
IPC分类号： G06F11/10 , G06F12/06 , G06F12/16
CPC分类号： G06F11/1028
摘要： Memory expansion using memory packages of different generations is performed without unnecessarily increasing the minimum memory capacity of a memory device and while obtaining a high error detecting ability and high reliability. In expanding the capacity of a memory device by using first generation 1M.times.1 bit IC memory packages, second generation 4M.times.4 bits IC memory packages, or third generation 16M.times.8 bits IC memory packages, the total code length is set to 40 bits, a 4's multiple, within a range longer than the total code length necessary for S4ED and shorter than the total code length necessary for S8ED, and a reduced code is used for enhancing the S8ED function. In this manner, wasteful first generation IC memory packages can be reduced in number, and the error detecting ability of a memory device using third generation memory packages can be retained substantially the same as that of a memory device using first generation memory packages.
摘要翻译：执行使用不同代的存储器包的存储器扩展，而不必不必要地增加存储器件的最小存储容量，同时获得高错误检测能力和高可靠性。通过使用第一代1Mx1位IC存储器封装，第二代4Mx4位IC存储器封装或第三代16Mx8位IC存储器封装扩展存储器件的容量，总代码长度设置为40位，4位数倍比S4ED所需的总代码长度要长于S8ED所需的总代码长度的范围，并且使用减少的代码来增强S8ED功能。以这种方式，可以减少浪费的第一代IC存储器封装，并且使用第三代存储器封装的存储器件的错误检测能力可以保持与使用第一代存储器封装的存储器件的错误检测能力基本相同。

5. 发明授权

US4719563A Data transmission control device for controlling transfer of large amounts of data between two memory units 失效
标题翻译：用于控制在两个存储单元之间传送大量数据的数据传输控制装置
公开(公告)号：US4719563A
公开(公告)日：1988-01-12
申请号：US684293
申请日：1984-12-20
申请人： Hiroshi Kosuge , Yoshio Kiriu , Junichi Taguri
发明人： Hiroshi Kosuge , Yoshio Kiriu , Junichi Taguri
IPC分类号： G06F13/38 , G06F13/16 , G06F13/28 , G06F13/36 , G06F15/16 , G06F13/00 , G06F12/06
CPC分类号： G06F13/1668 , G06F13/28
摘要： A data transmission control device for controlling the data transfer between two memory means on the basis of an instruction from a processor is disclosed in which the instruction from the processor is decoded, a transfer request is issued to each memory means a plurality of times, depending upon a transfer unit indicated by the decoded instruction and an access unit of each memory means, a data buffer is provided between the memory means to temporarily store data whichis transferred from one of the memory means to the other memory means, and the issue of a transfer request to each memory means is allowed or stopped in accordance with the quantity of data stored in the data buffer.
摘要翻译：公开了一种用于基于来自处理器的指令来控制两个存储器装置之间的数据传输的数据传输控制装置，其中来自处理器的指令被解码，传送请求被多次发布到每个存储装置，这取决于在由解码指令指示的传送单元和每个存储装置的访问单元之后，在存储装置之间提供数据缓冲器，以临时存储从存储装置之一传送到另一存储装置的数据，根据存储在数据缓冲器中的数据量，允许或停止对每个存储器装置的传送请求。

6. 发明授权

US4821172A Apparatus for controlling data transfer between storages 失效
标题翻译：用于控制存储器之间的数据传输的装置
公开(公告)号：US4821172A
公开(公告)日：1989-04-11
申请号：US83662
申请日：1987-08-10
申请人： Sigeru Kaneko , Yoshio Kiriu
发明人： Sigeru Kaneko , Yoshio Kiriu
IPC分类号： G06F12/00 , G06F13/38 , G06F13/42 , G06F13/00
CPC分类号： G06F13/4234
摘要： An apparatus for controlling a data transfer between storages in an information processing system having a main storage, an extended storage, and a processor in which data is transferred between the main storage and the extended storage by use of a synchronous instruction and an asynchronous instruction. The apparatus includes a unit to hold data transfer control information specified by the asynchronous instruction and a unit to hold data transfer control information specified by the synchronous instruction. Depending on a synchronous instruction or an asynchronous instruction, the data transfer is controlled to be achieved according to data transfer control information held in the unit associated with the instruction. The content of the unit is updated depending on the amount of data to be transferred. When a request of a data transfer is made by a synchronous instruction during a data transfer caused by an asynchronous instruction, the data transfer of the asynchronous instruction is interrupted to control the data transfer of the synchronous instruction to be executed. When the data transfer is completed, based on the content of the unit to hold data transfer control information of the asynchronous instruction, the data transfer of the asynchronous instruction interrupted is resumed.
摘要翻译：一种用于控制具有主存储器，扩展存储器和处理器的信息处理系统中的存储器之间的数据传输的装置，其中通过使用同步指令和异步指令在主存储器和扩展存储器之间传送数据。该装置包括用于保存由异步指令指定的数据传送控制信息的单元和用于保持由同步指令指定的数据传送控制信息的单元。根据同步指令或异步指令，根据与指令相关联的单元中保存的数据传输控制信息，控制数据传输。根据要传送的数据量更新本机的内容。当在由异步指令引起的数据传送期间通过同步指令进行数据传送的请求时，异步指令的数据传送被中断，以控制要执行的同步指令的数据传送。当数据传输完成时，基于保存异步指令的数据传输控制信息的单元的内容，恢复中断的异步指令的数据传输。

7. 发明授权

US5471582A Multiple rank hierarchical data storage system with data coherence 失效
标题翻译：具有数据一致性的多级分层数据存储系统
公开(公告)号：US5471582A
公开(公告)日：1995-11-28
申请号：US175285
申请日：1993-12-29
申请人： Yoshio Kiriu
发明人： Yoshio Kiriu
IPC分类号： G06F12/00 , G06F12/08 , G06F13/00
CPC分类号： G06F12/08
摘要： An extended, hierarchical storage system includes a main storage, an extended storage, and a work storage having a speed and capacity intermediate therebetween. Additionally, a relatively small, high-speed buffer storage is provided as an adjunct to a processor. The work storage implements a store-in mode and incorporates a flag representative of validity of data therein, which, in turn, impacts upon whether an update to lower ranking memory is necessary upon removal of data stored therein.
摘要翻译：扩展的分级存储系统包括主存储器，扩展存储器和在其间具有速度和容量的工作存储器。此外，作为处理器的附件提供了相对较小的高速缓冲存储器。工作存储器实现存储模式并且包含表示其中的数据的有效性的标志，这进而影响在删除存储在其中的数据时是否需要对较低等级的存储器的更新。

8. 发明授权

US5353404A Information processing system 失效
标题翻译：信息处理系统
公开(公告)号：US5353404A
公开(公告)日：1994-10-04
申请号：US468271
申请日：1990-01-22
申请人： Hitoshi Abe , Toshimitsu Ando , Shigeko Yazawa , Yoshio Kiriu , Yasuhiko Hatakeyama
发明人： Hitoshi Abe , Toshimitsu Ando , Shigeko Yazawa , Yoshio Kiriu , Yasuhiko Hatakeyama
IPC分类号： H04N5/262 , G06T1/60 , G06T13/20 , G06F15/62
CPC分类号： G06T1/60
摘要： Frames of digital data each representing a single picture of a video motion picture display are handled in a computer system with an extended memory operating in parallel with a computer system instruction processor and main memory to bypass the computer system input/output processor for continuously outputting the video information on a real time basis. The outputted data may be recorded continuously at a constant data rate for an entire motion picture worth of information or actually displayed on the video display on a real time basis. The extended storage has a memory larger than the main memory, where all of the frame data is stored and read out in high speed bursts to a buffer that continuously reads the data out of the buffer for outputting. At least a start command and a starting address in the extended memory are contained within the main memory to be read out and decoded by the instruction processor and computer system memory storage control, for transfer to the extended memory, where they are used to start the program, which includes extended memory control words stored in the main memory, which control words are decoded and executed in the extended memory in parallel with the computer system instruction processor. Addresses of succeeding frames are generated and decoded and used for fetching entirely within the extended memory, for memory areas according to indirect addressing. The extended memory has external data transfer and internal data transfer registers that hold command words for respective transferring programs that may be operated in parallel, with conflict between external transfer and internal transfer being decided in favor of external transfer to assure continuous data outputting.
摘要翻译：在计算机系统中处理每个表示视频运动图像显示的单个图像的数字数据帧，其中扩展存储器与计算机系统指令处理器和主存储器并行操作，以绕过计算机系统输入/输出处理器，以连续输出视频信息实时基础。输出的数据可以以恒定的数据速率连续地记录整个运动画面的信息，或实时显示在视频显示器上。扩展存储器具有大于主存储器的存储器，其中所有帧数据以高速脉冲串存储和读出到缓冲器，该缓冲器从缓冲器中连续读取数据以供输出。扩展存储器中的起始命令和起始地址至少包含在主存储器内，以由指令处理器和计算机系统存储器存储控制进行读出和解码，以传送到扩展存储器，在那里它们被用于启动程序，其包括存储在主存储器中的扩展存储器控制字，该控制字与计算机系统指令处理器并行地在扩展存储器中被解码和执行。生成并解码后续帧的地址，并将其用于根据间接寻址完全在扩展存储器内获取存储区域。扩展存储器具有外部数据传输和内部数据传输寄存器，其保存可以并行操作的相应传送程序的命令字，外部传输和内部传输之间的冲突被决定有利于外部传输以确保连续的数据输出。

9. 发明授权

US5307461A Multiple rank hierarchical data storage system with data coherence 失效
标题翻译：具有数据一致性的多级分层数据存储系统
公开(公告)号：US5307461A
公开(公告)日：1994-04-26
申请号：US950745
申请日：1992-09-24
申请人： Yoshio Kiriu
发明人： Yoshio Kiriu
IPC分类号： G06F12/00 , G06F12/08 , G06F13/00
CPC分类号： G06F12/08
摘要： An extended, hierarchical storage system includes a main storage, an extended storage, and a work storage having a speed and capacity intermediate therebetween, Additionally, a relatively small, high-speed buffer storage is provided as an adjunct to a processor. The work storage implements a store-in mode and incorporates a flag representative of validity of data therein, which, in turn, impacts upon whether an update to lower ranking memory is necessary upon removal of data stored therein.
摘要翻译：扩展的分级存储系统包括主存储器，扩展存储器和在其间具有中间速度和容量的工作存储器。此外，提供了相对较小的高速缓冲存储器作为处理器的附件。工作存储器实现存储模式并且包含代表其中数据有效性的标志，这进而影响在删除其中存储的数据时是否需要对较低等级的存储器的更新。

10. 发明授权

US4459688A Access request selecting circuit 失效
标题翻译：访问请求选择电路
公开(公告)号：US4459688A
公开(公告)日：1984-07-10
申请号：US210172
申请日：1980-11-25
申请人： Yoshio Kiriu
发明人： Yoshio Kiriu
IPC分类号： G06F12/00 , G06F13/16 , G11C8/00
CPC分类号： G06F13/1605
摘要： An access request selecting circuit for selectively accepting access request signals produced from a plurality of access request sources. Different series of recurrent time intervals are assigned to the access request sources. When a memory request signal is supplied from an access request source in a series of recurrent time intervals which are assigned to the access request source such a memory request signal is accepted. At this time, if an attendant signal produced in association with the memory request signal is supplied, this attendant signal is also accepted.
摘要翻译：访问请求选择电路，用于选择性地接受从多个访问请求源产生的访问请求信号。不同系列的经常时间间隔被分配给访问请求源。当存储器请求信号以分配给访问请求源的一系列复现时间间隔从访问请求源提供时，这样的存储器请求信号被接受。此时，如果提供与存储器请求信号相关联的伴随信号，则该接受信号也被接受。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式