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1. 发明授权

US06341335B1 Information processing system for read ahead buffer memory equipped with register and memory controller 有权
标题翻译：具有寄存器和存储器控制器的预读缓冲存储器的信息处理系统
公开(公告)号：US06341335B1
公开(公告)日：2002-01-22
申请号：US09181676
申请日：1998-10-29
申请人： Hiroki Kanai , Yasuo Inoue , Yoshifumi Takamoto
发明人： Hiroki Kanai , Yasuo Inoue , Yoshifumi Takamoto
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F9/383 , G06F12/0215 , G06F13/1631 , G06F2212/6022
摘要： An information processing system which reduces an access latency from a memory read request of a processor to a response thereto and also prevents reduction of the effective performance of a system bus caused by an increase in the access latency. In the information processing system, a memory controller is connected with the processor via a first bus and connected with a memory via a second bus, and a buffer memory is provided in the memory controller. The control circuit is controlled, before a memory access from the processor is carried out, to estimate an address to be possibly next accessed on the basis of addresses accessed in the past and to prefetch into the buffer memory, data stored in an address area continuous to the address and having a data size of twice or more an access unit of the processor.
摘要翻译：一种信息处理系统，其将访问延迟从处理器的存储器读取请求减少到对其的响应，并且还防止由于访问等待时间的增加而导致的系统总线的有效性能的降低。在信息处理系统中，存储器控制器经由第一总线与处理器连接，并经由第二总线与存储器连接，并且在存储器控制器中提供缓冲存储器。在执行来自处理器的存储器访问之前，控制电路被控制以基于过去访问的地址来估计可能下一次被访问的地址并预取到缓冲存储器中，存储在连续的地址区域中的数据并且具有处理器的访问单元的两倍或更多的数据大小。

2. 发明授权

US5903442A Hard disk drive and hard disk apparatus having bus and its installing method 失效
公开(公告)号：US5903442A
公开(公告)日：1999-05-11
申请号：US696801
申请日：1996-08-14
申请人： Hiroki Kanai , Mitsuo Ooyama , Yoshifumi Takamoto
发明人： Hiroki Kanai , Mitsuo Ooyama , Yoshifumi Takamoto
IPC分类号： G11B33/12 , G06F13/40 , G11B25/04 , H05K1/18
CPC分类号： G06F13/409
摘要： When a plurality of hard disks are connected by using a backplane, in order to enable a low-noise installation of the bus and a high-density installation of the hard disk to be simultaneously realized, a signal line of the bus and connectors are installed to the backplane, slots are set to installing regions of the drives, wirings of the signal lines between the connectors are set to, for example, a U-character shape, and a length of signal lines between the connectors is set to be longer than a distance between the connectors adjacent to the bus.

3. 发明授权

US5903724A Method of transferring packet data in a network by transmitting divided data packets 失效
标题翻译：通过发送划分的数据包在网络中传送分组数据的方法
公开(公告)号：US5903724A
公开(公告)日：1999-05-11
申请号：US708955
申请日：1996-09-06
申请人： Yoshifumi Takamoto , Hiroki Kanai , Tadahiro Takase , Katsuyoshi Kitai , Yoshimasa Masuoka
发明人： Yoshifumi Takamoto , Hiroki Kanai , Tadahiro Takase , Katsuyoshi Kitai , Yoshimasa Masuoka
IPC分类号： G06F13/00 , H04L1/16 , H04L1/18 , H04L12/70 , H04L29/06 , H04L29/08 , G06F3/00
CPC分类号： H04L29/06 , H04L1/1809 , H04L1/16 , H04L1/1874 , H04L69/324
摘要： A communication controller at the sending computer divides data transferred from a host into sub-ACK unit packets and transfers them sequentially to a destination without waiting for the sub-ACK's being subsequently provided by the destination. A communication controller at the receiving computer issues a sub-ACK to the sending computer for each of the sub-ACK unit packet, if the sub-ACK packet has been normally received and otherwise issues retransmission request for the sub-ACK unit packets and merges data included in the sub-ACK unit packets into the initial data, after they are normally received.
摘要翻译：发送计算机上的通信控制器将从主机传送的数据分割为子ACK单元分组，并将它们顺序地传送到目的地，而不必等待目的地随后提供的副ACK。如果副ACK分组已被正常接收，则在接收计算机上的通信控制器向发送计算机发送子ACK，以便对于每个子ACK单元分组发送子ACK，并且另外发出用于子ACK单元分组的重发请求并合并包含在子ACK单元中的数据在它们被正常接收之后被分组成初始数据。

4. 发明授权

US06449631B1 Method and apparatus for transmitting data in a network wherein acknowledgment signals are transmitted to acknowledge receipt of data 失效
标题翻译：用于在网络中发送数据的方法和装置，其中发送确认信号以确认数据的接收
公开(公告)号：US06449631B1
公开(公告)日：2002-09-10
申请号：US09292680
申请日：1999-04-16
申请人： Yoshifumi Takamoto , Hiroki Kanai , Tadahiro Takase , Katsuyoshi Kitai , Yoshimasa Masuoka
发明人： Yoshifumi Takamoto , Hiroki Kanai , Tadahiro Takase , Katsuyoshi Kitai , Yoshimasa Masuoka
IPC分类号： G06F1516
CPC分类号： H04L29/06 , H04L1/16 , H04L1/1809 , H04L1/1874 , H04L69/324
摘要： A communication controller at the sending computer divides data transferred from a host into sub-ACK unit packets, and transfers them sequentially to a destination without waiting for the sub-ACK's being subsequently provided by the destination. A communication controller at the receiving computer issues a sub-ACK to the sending computer for each of the sub-ACK unit packet, if the sub-ACK packet has been normally received and otherwise issues retransmission request for the sub-ACK unit packets and merges data included in the sub-ACK unit packets into the initial data, after they are normally received.
摘要翻译：发送计算机上的通信控制器将从主机传送的数据分割为子ACK单元分组，并将它们顺序地传送到目的地，而不等待目的地随后提供的副ACK。如果副ACK分组已被正常接收，则在接收计算机上的通信控制器向发送计算机发送子ACK，以便对于每个子ACK单元分组发送子ACK，并且另外发出用于子ACK单元分组的重发请求并合并包含在子ACK单元中的数据在它们被正常接收之后被分组成初始数据。

5. 发明授权

US6043988A Hard disk drive and hard disk apparatus having bus and its installing method 有权
标题翻译：具有总线的硬盘驱动器和硬盘设备及其安装方法
公开(公告)号：US6043988A
公开(公告)日：2000-03-28
申请号：US252811
申请日：1999-02-19
申请人： Hiroki Kanai , Mitsuo Ooyama , Yoshifumi Takamoto
发明人： Hiroki Kanai , Mitsuo Ooyama , Yoshifumi Takamoto
IPC分类号： G06F13/40 , H05K1/02 , H05K1/14
CPC分类号： H05K1/0228 , G06F13/409 , H05K2201/044 , H05K2201/09236 , H05K2201/09263
摘要： When a plurality of hard disks are connected by using a backplane, in order to enable a low-noise installation of the bus and a high-density installation of the hard disk to be simultaneously realized, a signal line of the bus and connectors are installed to the backplane, slots are set to installing regions of the drives, wirings of the signal lines between the connectors are set to, for example, a U-character shape, and a length of signal lines between the connectors is set to be longer than a distance between the connectors adjacent to the bus.
摘要翻译：当通过使用背板连接多个硬盘时，为了实现总线的低噪声安装和同时实现硬盘的高密度安装，总线和连接器的信号线被安装将插槽设置为安装驱动器的区域，将连接器之间的信号线的布线设置为例如U字形，并且将连接器之间的信号线的长度设置为长于邻近总线的连接器之间的距离。

6. 发明授权

US06470391B2 Method for transmitting data via a network in a form of divided sub-packets 失效
标题翻译：用于以划分的子分组的形式通过网络发送数据的方法
公开(公告)号：US06470391B2
公开(公告)日：2002-10-22
申请号：US09850139
申请日：2001-05-08
申请人： Yoshifumi Takamoto , Hiroki Kanai , Tadahiro Takase , Katsuyoshi Kitai , Yoshimasa Masuoka
发明人： Yoshifumi Takamoto , Hiroki Kanai , Tadahiro Takase , Katsuyoshi Kitai , Yoshimasa Masuoka
IPC分类号： G06F1516
CPC分类号： H04L29/06 , H04L1/16 , H04L1/1809 , H04L1/1874 , H04L69/324
摘要： A communication controller at the sending computer divides data transferred from a host into sub-ACK unit packets, and transfers them sequentially to a destination without waiting for the sub-ACK's being subsequently provided by the destination. A communication controller at the receiving computer issues a sub-ACK to the sending computer for each of the sub-ACK unit packet, if the sub-ACK packet has been normally received and otherwise issues retransmission request for the sub-ACK unit packets and merges data included in the sub-ACK unit packets into the initial data, after they are normally received.
摘要翻译：发送计算机上的通信控制器将从主机传送的数据分割为子ACK单元分组，并将它们顺序地传送到目的地，而不等待目的地随后提供的副ACK。如果副ACK分组已被正常接收，则在接收计算机上的通信控制器向发送计算机发送子ACK，以便对于每个子ACK单元分组发送子ACK，并且另外发出用于子ACK单元分组的重发请求并合并包含在子ACK单元中的数据在它们被正常接收之后被分组成初始数据。

7. 发明申请

US20110282963A1 STORAGE DEVICE AND METHOD OF CONTROLLING STORAGE DEVICE 审中-公开
标题翻译：存储装置和控制存储装置的方法
公开(公告)号：US20110282963A1
公开(公告)日：2011-11-17
申请号：US12743861
申请日：2010-05-11
申请人： Shohei Shimahara , Hiroki Kanai , Ryosuke Matsubara
发明人： Shohei Shimahara , Hiroki Kanai , Ryosuke Matsubara
IPC分类号： G06F15/16
CPC分类号： G06F3/0656 , G06F3/061 , G06F3/0617 , G06F3/0619 , G06F3/065 , G06F3/067 , G06F11/2056 , G06F11/2089 , G06F12/0866
摘要： Disclosed is a storage device 10 in which CPUs 132 are redundantly configured, and which is thus capable of performing dual-writing of data into cache memories 134 respectively coupled to the CPUs 132. In the storage device 10, general-purpose processors each including an NTB_Port 72, PCI_Ports 73 and a Memory_I/F 74 are used as CPUs 132 of the CPUs 132. In the storage device 10, when a first PCIe_Port 73 determines not to perform the dual-writing, a first NTB_Port 1322 writes data into only one of the cache memories 134, and when the first PCIe_Port 73 determines to perform the dual-writing, the first NTB_Port 1322 writes data into one of the cache memories 134 while writing the data into the other one of the cache memories 134 via the other one of the CPUs 132.
摘要翻译：公开了一种存储装置10，其中CPU 132被冗余地配置，并且因此能够将数据双重写入到分别耦合到CPU 132的高速缓存存储器134中。在存储装置10中，通用处理器包括 NTB_Port 72，PCI_Ports 73和Memory_I / F 74用作CPU 132的CPU 132.在存储装置10中，当第一PCIe_Port 73确定不执行双重写入时，第一NTB_Port 1322将数据写入仅一个的高速缓冲存储器134，并且当第一PCIe_Port 73确定执行双重写入时，第一NTB_Port 1322将数据经由另一个将数据写入另一个高速缓存存储器134中，将数据写入高速缓冲存储器134之一的CPU 132。

8. 发明申请

US20090271539A1 STORAGE CONTROLLING UNIT 审中-公开
标题翻译：存储控制单元
公开(公告)号：US20090271539A1
公开(公告)日：2009-10-29
申请号：US12496684
申请日：2009-07-02
申请人： Akira Fujibayashi , Hiroki Kanai
发明人： Akira Fujibayashi , Hiroki Kanai
IPC分类号： G06F3/00
CPC分类号： G06F3/0658 , G06F3/0607 , G06F3/0632 , G06F3/067
摘要： Provided is a storage controller capable of changing a system configuration with scalability. A storage controller blade of the storage controller includes: interface units that each connect to one of a host computer and a disk device; a processor unit that controls a configuration of the storage controller and data access; a memory unit that stores a data cache and configuration information on the interface unit and the processor unit; and a mutual connection unit that connects the interface units, the processor unit, and the memory unit to one another. The processor unit recognizes a form of connection to another storage controller blade over the mutual network, and the connection path to another storage controller blade is set in the mutual connection unit based on the recognized form of connection.
摘要翻译：提供了能够以可扩展性改变系统配置的存储控制器。存储控制器的存储控制器刀片包括：各自连接到主计算机和盘设备之一的接口单元; 处理器单元，其控制存储控制器的配置和数据访问; 存储单元，其在接口单元和处理器单元上存储数据高速缓存和配置信息; 以及将接口单元，处理器单元和存储器单元彼此连接的相互连接单元。处理器单元通过相互网络识别与另一存储控制器刀片的连接形式，并且基于所识别的连接形式将在另一个存储控制器刀片的连接路径设置在相互连接单元中。

9. 发明授权

US07320051B2 Storage device control apparatus and control method for the storage device control apparatus 失效
标题翻译：用于存储装置控制装置的存储装置控制装置和控制方法
公开(公告)号：US07320051B2
公开(公告)日：2008-01-15
申请号：US11606878
申请日：2006-12-01
申请人： Hiroki Kanai
发明人： Hiroki Kanai
IPC分类号： G06F13/00
CPC分类号： G06F3/0607 , G06F3/0626 , G06F3/0656 , G06F3/0658 , G06F3/0689
摘要： A storage device control apparatus includes a mounting part and an internal connection part. The mounting part can removably mount channel control unit, each with a host interface controller formed therein for receiving data I/O requests, disk control units, each with a disk interface controller formed therein for performing I/O control of the data to storage volumes storing data in response to the data I/O requests, cache memory units, each with a memory formed therein for storing the data, and storage control units, each with the host interface controller, the disk interface controller, and the memory formed therein. The internal connection part connects the channel control units, the disk control units, the cache memory units, and the storage control units in a communicable manner.
摘要翻译：存储装置控制装置包括安装部和内部连接部。安装部分可移除地安装通道控制单元，每个通道控制单元具有形成在其中的主机接口控制器，用于接收数据I / O请求，磁盘控制单元，每个具有形成在其中的磁盘接口控制器，用于执行数据到存储卷的I / O控制响应于数据I / O请求存储数据，高速缓冲存储器单元，每个具有形成在其中的存储器用于存储数据;以及存储控制单元，每个存储控制单元具有主机接口控制器，磁盘接口控制器和形成在其中的存储器。内部连接部分以可通信的方式连接通道控制单元，盘控制单元，高速缓冲存储器单元和存储控制单元。

10. 发明授权

US07287125B2 Disk array device, method for controlling the disk array device and storage system 失效
标题翻译：磁盘阵列设备，磁盘阵列设备和存储系统的控制方法
公开(公告)号：US07287125B2
公开(公告)日：2007-10-23
申请号：US11545514
申请日：2006-10-11
申请人： Seiji Kaneko , Hiroki Kanai
发明人： Seiji Kaneko , Hiroki Kanai
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F3/0611 , G06F3/0658 , G06F3/0659 , G06F3/067 , G06F3/0689 , G06F12/0815 , G06F12/0817 , Y10S707/99952
摘要： A disk array device is equipped with a plurality of input/output channels that receive data input/output requests from an external device, a plurality of cache memories provided for the corresponding respective input/output channels, each of the cache memories connected to each of the corresponding respective input/output channels, a disk drive device, a disk control module that performs data input/output to and from the disk drive device, and a communication module that communicatively connects the input/output channels with the disk control module. The disk array device also includes a consistency maintaining module that can perform a consistency maintaining processing to maintain consistency of data stored in each of the cache memories. According to the content of the data input/output request received from the external device, an execution order of a response processing to respond to the external device according to the data input/output request and the consistency maintaining processing is controlled.
摘要翻译：磁盘阵列装置配备有从外部设备接收数据输入/输出请求的多个输入/输出通道，为相应的相应输入/输出通道提供的多个高速缓存存储器，每个缓存存储器连接到对应的各个输入/输出通道，磁盘驱动器装置，对磁盘驱动装置执行数据输入/输出的磁盘控制模块，以及将输入/输出通道与磁盘控制模块通信连接的通信模块。磁盘阵列设备还包括一致性维护模块，该模块可以执行一致性维持处理以保持存储在每个高速缓冲存储器中的数据的一致性。根据从外部设备接收的数据输入/输出请求的内容，控制根据数据输入/输出请求和一致性维护处理对外部设备进行响应的响应处理的执行顺序。

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