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    • 1. 发明授权
    • Amplitude setting circuit
    • 振幅设定电路
    • US07501878B2
    • 2009-03-10
    • US11276140
    • 2006-02-15
    • Hirohisa SuzukiKazuo HasegawaEiji Akama
    • Hirohisa SuzukiKazuo HasegawaEiji Akama
    • H03K17/14
    • H03K5/02H03K19/00369H04L27/08
    • An amplitude setting circuit for setting an amplitude level of its output signal corresponding to an input signal. By setting a current flowing through a first diode-connected transistor (Q5) and a current flowing through a first drive transistor (Q1) to be in a predetermined relationship, variation with temperature in potential at a first connection point of the first drive transistor (Q1) and a first conductivity-type transistor (M1) is removed, and by setting a current flowing through a second diode-connected transistor (Q6) and a current flowing through a second drive transistor (Q4) to be in a predetermined relationship, variation with temperature in potential at a second connection point of a second conductivity-type transistor (M2) and the second drive transistor (Q4) is removed.
    • 一种幅度设定电路,用于设定与输入信号对应的其输出信号的幅度电平。 通过将流过第一二极管连接的晶体管(Q5)的电流和流过第一驱动晶体管(Q1)的电流设定为预定关系,在第一驱动晶体管的第一连接点 Q1)和第一导电型晶体管(M1)被去除,并且通过将流过第二二极管连接的晶体管(Q6)的电流和流过第二驱动晶体管(Q4)的电流设定为预定关系, 在第二导电型晶体管(M2)和第二驱动晶体管(Q4)的第二连接点处的电位温度的变化被去除。
    • 2. 发明申请
    • AMPLITUDE SETTING CIRCUIT
    • 振幅设定电路
    • US20060192605A1
    • 2006-08-31
    • US11276140
    • 2006-02-15
    • Hirohisa SuzukiKazuo HasegawaEiji Akama
    • Hirohisa SuzukiKazuo HasegawaEiji Akama
    • H03L5/00
    • H03K5/02H03K19/00369H04L27/08
    • An amplitude setting circuit for setting an amplitude level of its output signal corresponding to an input signal. By setting a current flowing through a first diode-connected transistor (Q5) and a current flowing through a first drive transistor (Q1) to be in a predetermined relationship, variation with temperature in potential at a first connection point of the first drive transistor (Q1) and a first conductivity-type transistor (M1) is removed, and by setting a current flowing through a second diode-connected transistor (Q6) and a current flowing through a second drive transistor (Q4) to be in a predetermined relationship, variation with temperature in potential at a second connection point of a second conductivity-type transistor (M2) and the second drive transistor (Q4) is removed.
    • 一种幅度设定电路,用于设定与输入信号对应的其输出信号的幅度电平。 通过将流过第一二极管连接晶体管(Q 5)的电流和流过第一驱动晶体管(Q1)的电流设定为预定关系,在第一驱动器的第一连接点处的电位温度变化 晶体管(Q1)和第一导电型晶体管(M1)被去除,并且通过将流经第二二极管连接晶体管(Q 6)的电流和流过第二驱动晶体管(Q4)的电流设置为 处于预定关系时,除去第二导电型晶体管(M2)和第二驱动晶体管(Q4)的第二连接点处的电位温度的变化。
    • 3. 发明授权
    • Pressure sensor mounting method, tire and wheel having pressure sensor, and tire pressure detection device
    • 压力传感器安装方法,具有压力传感器的轮胎和轮胎以及轮胎压力检测装置
    • US08176776B2
    • 2012-05-15
    • US12223250
    • 2007-01-24
    • Hirohisa SuzukiEiji AkamaKazuo Hasegawa
    • Hirohisa SuzukiEiji AkamaKazuo Hasegawa
    • B60C23/02
    • B60C23/0408
    • The accuracy of a measurement value obtained by a tire pressure detection device is lowered by a centrifugal force and an inertial force during travel. A pressure sensor (30) displaces a diaphragm (20) in its vertical direction (32) according to the pressure. The pressure sensor (30) is arranged in a tire (2) with the vertical direction (32) directed to a direction parallel to a rotation axis (34) instead of the tire circumferential direction or radial direction. The pressure sensor (30) is mounted onto a substrate with the vertical direction (32) of its diaphragm (20) directed in parallel to the substrate surface and the substrate is bonded to a tread portion of the tire (2) and a wheel rim portion while adjusting the vertical direction (32) of the diaphragm (20) with the direction of the rotation axis (34).
    • 由轮胎压力检测装置获得的测量值的精度通过离心力和行驶期间的惯性力而降低。 压力传感器(30)根据压力在其垂直方向(32)上移动隔膜(20)。 代替轮胎周向或径向,压力传感器(30)布置在轮胎(2)中,其中垂直方向(32)指向平行于旋转轴线(34)的方向。 压力传感器(30)安装在基板上,其隔膜(20)的垂直方向(32)平行于基板表面并且基板结合到轮胎(2)的胎面部分,轮缘 同时沿着旋转轴线(34)的方向调节隔膜(20)的垂直方向(32)。
    • 4. 发明申请
    • Pressure Sensor Mounting Method, Tire and Wheel Having Pressure Sensor, and Tire Pressure Detection Device
    • 压力传感器安装方法,带压力传感器的轮胎和轮胎,轮胎压力检测装置
    • US20100147063A1
    • 2010-06-17
    • US12223250
    • 2007-01-24
    • Hirohisa SuzukiEiji AkamaKazuo Hasegawa
    • Hirohisa SuzukiEiji AkamaKazuo Hasegawa
    • B60C23/04
    • B60C23/0408
    • The accuracy of a measurement value obtained by a tire pressure detection device is lowered by a centrifugal force and an inertial force during travel. A pressure sensor (30) displaces a diaphragm (20) in its vertical direction (32) according to the pressure. The pressure sensor (30) is arranged in a tire (2) with the vertical direction (32) directed to a direction parallel to a rotation axis (34) instead of the tire circumferential direction or radial direction. The pressure sensor (30) is mounted onto a substrate with the vertical direction (32) of its diaphragm (20) directed in parallel to the substrate surface and the substrate is bonded to a tread portion of the tire (2) and a wheel rim portion while adjusting the vertical direction (32) of the diaphragm (20) with the direction of the rotation axis (34).
    • 由轮胎压力检测装置获得的测量值的精度通过离心力和行驶期间的惯性力而降低。 压力传感器(30)根据压力在其垂直方向(32)上移动隔膜(20)。 代替轮胎周向或径向,压力传感器(30)布置在轮胎(2)中,其中垂直方向(32)指向平行于旋转轴线(34)的方向。 压力传感器(30)安装在基板上,其隔膜(20)的垂直方向(32)平行于基板表面并且基板结合到轮胎(2)的胎面部分,轮缘 同时沿着旋转轴线(34)的方向调节隔膜(20)的垂直方向(32)。
    • 5. 发明授权
    • Delay circuit and ring oscillator using the same
    • 延迟电路和环形振荡器使用相同
    • US07288978B2
    • 2007-10-30
    • US11275808
    • 2006-01-30
    • Hirohisa SuzukiKazuo HasegawaEiji Akama
    • Hirohisa SuzukiKazuo HasegawaEiji Akama
    • H03H11/26
    • H03K5/133H03K3/0315H03K2005/00026H03K2005/00156H03K2005/00202
    • In a delay circuit, when a first conductivity-type transistor (M6) becomes conductive on the basis of one level of its input signal, a first current path is formed through a source side transistor (M4), the first conductivity-type transistor (M6), and a second drive transistor (M9) between a source power line and a sink power line, and its output signal being the delayed inverse of the one level of the input signal is output from a connection point of another source side transistor (M5) and a sink side transistor (M11), and when a second conductivity-type transistor (M7) becomes conductive on the basis of the other level of the input signal, a second current path is formed through a first drive transistor (M3), the second conductivity-type transistor (M7), and another sink side transistor (M10), and the output signal being the delayed inverse of the other level of the input signal is output from the connection point.
    • 在延迟电路中,当第一导电型晶体管(M 6)基于其输入信号的一个电平导通时,通过源极侧晶体管(M 4)形成第一电流路径,第一导电型 晶体管(M 6)和源极电源线和吸收电力线之间的第二驱动晶体管(M9),并且其输出信号是输入信号的一个电平的延迟的反相,从另一个的连接点输出 源极侧晶体管(M5)和漏极侧晶体管(M11),并且当第二导电型晶体管(M7)基于输入信号的其他电平导通时,形成第二电流路径 第一驱动晶体管(M 3),第二导电型晶体管(M7)和另一个漏极侧晶体管(M10),并且作为输入信号的另一个电平的延迟反相的输出信号从 连接点。
    • 6. 发明授权
    • Amplitude adjusting circuit
    • 幅度调节电路
    • US07262650B2
    • 2007-08-28
    • US11333547
    • 2006-01-18
    • Hirohisa SuzukiKazuo HasegawaEiji Akama
    • Hirohisa SuzukiKazuo HasegawaEiji Akama
    • H03L5/00
    • H03K25/02
    • An amplitude adjusting circuit comprises a first current mirror where a variable current of a variable current source is copied into each of 1st-3rd transistors; a second current mirror where the variable current is copied into each of 11th-13th transistors; a third current mirror having 6th-7th transistors where a current through the 2nd transistor copied from the variable current flows through the 6th transistor; a fourth current mirror having 8th-9th transistors where a current through the 12th transistor copied from the variable current flows through the 8th transistor; an inverter that has 1st-2nd conductivity type transistors and produces an output signal corresponding to a current level of the 7th or 9th transistor; a fifth current mirror having 15th-14th transistors where a current through the 14th transistor copied from the 15th transistor's becomes a current sourced by the 7th transistor; and a sixth current mirror having 5th-4th transistors where a current through the 4th transistor copied from the 5th transistor's becomes a current sunk by the 9th transistor.
    • 振幅调整电路包括第一电流镜,其中可变电流源的可变电流被复制到第一至第三晶体管的每一个中; 第二电流镜,其中可变电流被复制到第十一至第十三晶体管的每一个中; 具有第六晶体管的第三电流镜,其中从可变电流复制的通过第二晶体管的电流流过第六晶体管; 具有第八晶体管的第四电流镜,其中从可变电流复制的第十二晶体管的电流流过第八晶体管; 具有第1〜第2导电型晶体管并产生与第7或第9晶体管的电流电平对应的输出信号的反相器; 具有第十五至第十四晶体管的第五电流镜,其中从第十五晶体管复制的通过第十四晶体管的电流变为由第七晶体管产生的电流; 以及具有第五至第四晶体管的第六电流镜,其中通过第五晶体管复制的第四晶体管的电流由第九晶体管成为电流。
    • 7. 发明申请
    • Clock Extracting Circuit
    • 时钟提取电路
    • US20060188048A1
    • 2006-08-24
    • US11275805
    • 2006-01-30
    • Hirohisa SuzukiKazuo HasegawaEiji Akama
    • Hirohisa SuzukiKazuo HasegawaEiji Akama
    • H04L7/02
    • H04L7/033H03L7/0812H04L7/0066H04L7/0087H04L25/4904
    • A clock extracting circuit for receiving an encoded signal and for extracting a clock signal from the encoded signal. The circuit comprises an edge detector that detects rising and falling edges of the encoded signal and produces edge detection pulses indicating the edges being detected; a mask signal generator producing a mask signal which is inverted in response to the edge detection pulses, which are produced one for each period of the received encoded signal, on the basis of the edge detection pulses; a mask signal delay section delaying the mask signal by a delay time controllable and outputting the delayed mask signal; a clock generator producing the clock signal on the basis of edges of the delayed mask signal; and a delay controller that controls the delay time of the mask signal delay section so as to set a duty ratio of the produced clock signal to a predetermined value.
    • 一种时钟提取电路,用于接收编码信号并从编码信号中提取时钟信号。 该电路包括边缘检测器,其检测编码信号的上升沿和下降沿,并产生指示所检测的边缘的边缘检测脉冲; 掩模信号发生器,其根据所述边缘检测脉冲产生响应于所述边缘检测脉冲反相的掩蔽信号,所述边缘检测脉冲是针对接收到的编码信号的每个周期产生的一个; 屏蔽信号延迟部分,将屏蔽信号延迟延迟时间可控并输出延迟的屏蔽信号; 基于延迟的掩码信号的边沿产生时钟信号的时钟发生器; 以及延迟控制器,其控制所述掩模信号延迟部分的延迟时间,以将所产生的时钟信号的占空比设定为预定值。
    • 10. 发明申请
    • Delay Circuit and Ring Oscillator Using The Same
    • 延迟电路和环形振荡器使用它
    • US20060197572A1
    • 2006-09-07
    • US11275808
    • 2006-01-30
    • Hirohisa SuzukiKazuo HasegawaEiji Akama
    • Hirohisa SuzukiKazuo HasegawaEiji Akama
    • H03H11/26
    • H03K5/133H03K3/0315H03K2005/00026H03K2005/00156H03K2005/00202
    • In a delay circuit, when a first conductivity-type transistor (M6) becomes conductive on the basis of one level of its input signal, a first current path is formed through a source side transistor (M4), the first conductivity-type transistor (M6), and a second drive transistor (M9) between a source power line and a sink power line, and its output signal being the delayed inverse of the one level of the input signal is output from a connection point of another source side transistor (M5) and a sink side transistor (M11), and when a second conductivity-type transistor (M7) becomes conductive on the basis of the other level of the input signal, a second current path is formed through a first drive transistor (M3), the second conductivity-type transistor (M7), and another sink side transistor (M10), and the output signal being the delayed inverse of the other level of the input signal is output from the connection point.
    • 在延迟电路中,当第一导电型晶体管(M 6)基于其输入信号的一个电平导通时,通过源极侧晶体管(M 4)形成第一电流路径,第一导电型 晶体管(M 6)和源极电源线和吸收电力线之间的第二驱动晶体管(M9),并且其输出信号是输入信号的一个电平的延迟的反相,从另一个的连接点输出 源极侧晶体管(M5)和漏极侧晶体管(M11),并且当第二导电型晶体管(M7)基于输入信号的其他电平导通时,形成第二电流路径 第一驱动晶体管(M 3),第二导电型晶体管(M7)和另一个漏极侧晶体管(M10),并且作为输入信号的另一个电平的延迟反相的输出信号从 连接点。